AD1881A Fast Delivery |IC PHOENIX CO.,LIMITED

AD1881A ,AC?7 SoundMAX?CodecSpecifications subject to change without notice.REV. 0–2–AD1881ADIGITAL DECIMATION AND INTERPOLATIO ..
AD1881A JST ,AC?7 SoundMAX CodecFEATURESPHAT™ Stereo 3D Stereo EnhancementDesigned for AC’97 Analog I/O ComponentSplit Power Suppli ..
AD1881AJST ,AC?7 SoundMAX CodecSPECIFICATIONSSTANDARD TEST CONDITIONS UNLESS OTHERWISE NOTEDTemperature 25 °CDAC Test ConditionsDi ..
AD1881AJST ,AC?7 SoundMAX CodecFEATURESVariable Sample RateMobile Low Power Mixer ModeTrue Line-Level OutputDigital Audio Mixer Mo ..
AD1881AJST-REEL ,AC’97 SoundMAX® CodecSPECIFICATIONSSTANDARD TEST CONDITIONS UNLESS OTHERWISE NOTEDTemperature 25 °CDAC Test ConditionsDi ..
AD1881AJSTZ ,AC’97 SoundMAX® CodecFEATURESVariable Sample RateMobile Low Power Mixer ModeTrue Line-Level OutputDigital Audio Mixer Mo ..
AD8334ACPZ ,Quad VGA with Ultralow Noise Preamplifier and Programmable RINapplications.− the operating level of the detec-+tor. Then an example applica-ERRORtion revolving a ..
AD8335ACPZ ,Quad Low Noise, Low Cost Variable Gain Amplifierapplications, the PrAs can be powered down, significantly of ×8 (18.06 dB) and accepts input signal ..
AD8335ACPZ-REEL7 ,Quad Low Noise, Low Cost Variable Gain AmplifierFEATURES Low noise preamplifier (PrA) Voltage noise = 1.3 nV/√Hz typical 61 60 59 58 53 55 52 51 49 ..
AD8342ACPZ-REEL7 ,LF to 500MHz Active Receive Mixerapplications that require converted to a single-ended signal through the use of a match-wide bandwi ..
AD8342ACPZ-REEL7 ,LF to 500MHz Active Receive MixerFEATURES FUNCTIONAL BLOCK DIAGRAM Broadband RF port: LF to 500 MHz VPDC PWDN EXRB COMMConversion ga ..
AD8343ARU ,DC-to-2.5 GHz High IP3 Active MixerAPPLICATIONSCellular Base StationsWireless LANSatellite ConvertersSONET/SDH RadioRadio LinksRF Inst ..

AD1881A
AC?7 SoundMAX?Codec
REV.0
AC’97 SoundMAX® Codec
FUNCTIONAL BLOCK DIAGRAM
SYNC
BIT_CLK
MIC1
MIC2
AUX
VIDEO
LINE_OUT_L
MONO_OUT
LINE_IN
PHONE_IN
LINE_OUT_R
XTL_OUTXTL_IN
CS1EAPDMODE
RESET
SDATA_IN
CS0
SDATA_OUT
PC_BEEP
LNLVL_OUT_R
LNLVL_OUT_L
AC’97 2.1 FEATURES
Variable Sample Rate
True Line-Level Output
Supports Secondary Codec Modes
AC’97 FEATURES
Designed for AC’97 Analog I/O Component
48-Lead LQFP Package
Multibit �� Converter Architecture for Improved
S/N Ratio Greater than 90 dB
16-Bit Stereo Full-Duplex Codec
Four Analog Line-Level Stereo Inputs for Connection
from LINE, CD, VIDEO, and AUX
Two Analog Line-Level Mono Inputs for Speakerphone
and PC BEEP
Mono MIC Input Switchable from Two External
Sources
High Quality CD Input with Ground Sense
Stereo Line-Level Output
Mono Output for Speakerphone or Internal Speaker
Power Management Support
ENHANCED FEATURES
Mobile Low Power Mixer Mode
Digital Audio Mixer Mode
Full Duplex Variable 8 kHz to 48 kHz Sampling Rate
with 1 Hz Resolution
PHAT™ Stereo 3D Stereo Enhancement
Split Power Supplies (3.3 V Digital/5 V Analog)
Extended 6-Bit Master Volume Control
Audio Amp Power-Down Signal
SoundMAX is a registered trademark and PHAT is a trademark of Analog Device, Inc.
AD1881A–SPECIFICATIONS
ANALOG INPUT
MASTER VOLUME
PROGRAMMABLE GAIN AMPLIFIER—ADC
ANALOG MIXER—INPUT GAIN/AMPLIFIERS/ATTENUATORS
Step Size (+12 dB to –34.5 dB): (All Steps Tested)
Input Gain/Attenuation Range: MIC, LINE, AUX, CD, VIDEO, PHONE_IN, DAC
Step Size (0 dB to –45 dB): (All Steps Tested) PC_BEEP
*Guaranteed, not tested.
Specifications subject to change without notice.
Temperature25°C
Digital Supply (VDD)3.3V
Analog Supply (VCC)5.0V
Sample Rate (FS)48kHz
Input Signal1008Hz
STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED
DAC Test Conditions
Calibrated
–3 dB Attenuation Relative to Full-Scale
Input 0 dB
10 kΩ Output Load
ADC Test Conditions
Calibrated
0 dB Gain
Input –3.0 dB Relative to Full-Scale
AD1881A
DIGITAL DECIMATION AND INTERPOLATION FILTERS*
ANALOG-TO-DIGITAL CONVERTERS
ADC Crosstalk*
Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L)
LINE_IN to Other
Gain Error (Full-Scale Span Relative to Nominal Input Voltage)
Gain Error (Full-Scale Span Relative to Nominal Input Voltage)
ANALOG OUTPUT
Output Capacitance*
External Load Capacitance
VREF
*Guaranteed, not tested.
Specifications subject to change without notice.
AD1881A–SPECIFICATIONS
STATIC DIGITAL SPECIFICATIONS
POWER SUPPLY
CLOCK SPECIFICATIONS*
POWER-DOWN MODE
*Guaranteed, not tested.
Specifications subject to change without notice.
TIMING PARAMETERS1 (GUARANTEED OVER OPERATING TEMPERATURE RANGE)
BIT_CLK High Pulsewidth
Propagation Delay
NOTES
1Guaranteed, not tested.
2Output jitter is directly dependent on crystal input jitter.
Specifications subject to change without notice.
AD1881A
Figure 1.Cold Reset
Figure 2.Warm Reset
Figure 3.Clock Timing
Figure 4.Data Setup and Hold
Figure 5.Signal Rise and Fall Time
Figure 6.AC Link Low Power Mode Timing
Figure 7.ATE Test Mode
ABSOLUTE MAXIMUM RATINGS*
Analog Input Voltage (Signal Pins)
Digital Input Voltage (Signal Pins)
*Stresses greater than those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
ENVIRONMENTAL CONDITIONS
Ambient Temperature Rating
TAMB = TCASE – (PD × θCA)
TCASE = Case Temperature in °C
PD = Power Dissipation in W
θCA = Thermal Resistance (Case-to-Ambient)
θJA = Thermal Resistance (Junction-to-Ambient)
θJC = Thermal Resistance (Junction-to-Case)
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD1881A features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATION
48-Lead LQFP
SS2
EAPD/CHAIN_INLNLVL_OUT_RCS0NCNCNC
LINE_OUT_R
LINE_OUT_L
CX3D
RX3D
FILT_L
FILT_R
AFILT2
PHONE_IN
AUX_L
AUX_R
VIDEO_L
CD_GND_REF
DVDD1
XTL_IN
XTL_OUT
SDATA_OUT
BIT_CLK
SDATA_IN
SYNC
RESET
PC_BEEP
NC = NO CONNECT
AFILT1
CD_R
MIC1MIC2
LINE_IN_L
MONO_OUT
LINE_IN_R
CS1
CD_L
VIDEO_R
MODE
DVSS1
DVSS2
DVDD2VREFOUT
VREF
AVSS1
AVDD1
DD2
LNLVL_OUT_L
AD1881A
PIN FUNCTION DESCRIPTIONS
Digital I/O
Miscellaneous Connections
Analog I/O
These signals connect the AD1881A component to analog sources and sinks, including microphones and speakers.
Filter/Reference
These signals are connected to resistors, capacitors, or specific voltages.
Power and Ground Signals
DVSS1
AVDD1
No Connects
Figure 8.Block Diagram Register Map
AD1881A
PRODUCT OVERVIEW
The AD1881A meets the Audio Codec ’97 2.0 and 2.1 Extensions. In
addition, the AD1881A SoundMAX Codec is designed to meet all
requirements of the Audio Codec ’97, Component Specification, Revi-
sion 1.03, © 1996, Intel Corporation, found at www.Intel.com.
The AD1881A also includes some other Codec enhanced fea-
tures such as the built-in PHAT Stereo 3D enhancement.
The AD1881A is an analog front end for high performance PC
audio applications. The AC’97 architecture defines a 2-chip
audio solution comprising a digital audio controller, plus a high
quality analog component that includes Digital-to-Analog
Converters (DACs), Analog-to-Digital Converters (ADCs),
mixer and I/O.
The main architectural features of the AD1881A are the high
quality analog mixer section, two channels of Σ∆ ADC conversion,
two channels of Σ∆ DAC conversion with Data Direct Scram-
bling (D2S) rate generators. The AD1881A’s left channel ADC
and DAC are compatible for modem applications supporting irra-
tional sample rates and modem filtering requirements.
FUNCTIONAL DESCRIPTION
This section overviews the functionality of the AD1881A and
is intended as a general introduction to the capabilities of the
device. Detailed reference information may be found in the
descriptions of the Indexed Control Registers.
Analog Inputs
The Codec contains a stereo pair of Σ∆ ADCs. Inputs to the
ADC may be selected from the following analog signals: tele-
phony (PHONE_IN), mono microphone (MIC1 or MIC2),
stereo line (LINE_IN), auxiliary line input (AUX), stereo CD
ROM (CD), stereo audio from a video source (VIDEO) and
post-mixed stereo or mono line output (LINE_OUT).
Analog Mixing
PHONE_IN, MIC1 or MIC2, LINE_IN, AUX, CD and VIDEO
can be mixed in the analog domain with the stereo output from the
DACs. Each channel of the stereo analog inputs may be inde-
pendently gained or attenuated from +12 dB to –34.5 dB in 1.5 dB
steps. The summing path for the mono inputs (PHONE_IN, MIC1,
and MIC2 to LINE_OUT) duplicates mono channel data on both
the left and right LINE_OUT. Additionally, the PC attention sig-
nal (PC_BEEP) may be mixed with the line output. A switch
allows the output of the DACs to bypass the PHAT Stereo
3D enhancement.
Digital Audio Mode
The AD1881A is designed with a Digital Audio Mode (DAM)
that allows mixing of all analog inputs independent of the DAC
output signal path. Mixed analog input signals may be sent to
the ADCs for processing by the controller or the host, and may
be used during simultaneous capture and playback at different
sample rates.
Analog-to-Digital Signal Path
The selector sends left and right channel information to the
programmable gain amplifier (PGA). The PGA following the
selector allows independent gain control for each channel entering
the ADC from 0 dB to +22.5 dB in 1.5 dB steps. Each channel
of the ADC is independent, and can process left and right chan-
nel data at different sample rates.
Sample Rates and D2S
The AD1881A default mode sets the Codec to operate at 48 kHz
sample rates. The converter pairs may process left and right
channel data at different sample rates. The AD1881A sample
rate generator allows the Codec to instantaneously change and
process sample rates from 8 kHz to 48 kHz with a resolution
of 1 Hz. The in-band integrated noise and distortion artifacts
introduced by rate conversions are below –90 dB. The AD1881A
uses a 4-bit D/A structure and Data Directed Scrambling (D2S)
to enhance noise immunity on motherboards and in PC enclo-
sures, and to suppress idle tones below the device’s quantization
noise floor. The D2S process pushes noise and distortion artifacts
caused by errors in the multibit DAC to frequencies beyond the
auditory response of the human ear and then filters them.
Digital-to-Analog Signal Path
The analog output of the DAC may be gained or attenuated from
+12 dB to –34.5 dB in 1.5 dB steps, and summed with any of
the analog input signals. The summed analog signal enters the
Master Volume stage where each channel of the mixer output may
be attenuated from 0 dB to –94.5 dB in 1.5 dB steps or muted.
Line-Level Outputs
The AD1881A offers a true line-level output for notebook dock-
ing station and home theater applications. The line-level output
does not change with master volume settings.
Host-Based Echo Cancellation Support
The AD1881A supports time correlated I/O data format by pre-
senting MIC data on the left channel of the ADC and the mono
summation of left and right output on the right channel. The
ADC is splittable; left and right ADC data can be sampled at
different rates.
Power Management Modes
The AD1881A is designed to meet ACPI power consumption
requirements through flexible power management control of all
internal resources.
Indexed Control Registers
76h
NOTES
All registers not shown and bits containing an X are assumed to be reserved.
Odd register addresses are aliased to the next lower even address.
Reserved registers should not be written.
AD1881A
Reset (Index 00h)
Note: Writing any value to this register performs a register reset, which causes all registers to revert to their default values (except
74h, which forces the serial configuration). Reading this register returns the ID code of the part and a code for the type of 3D Stereo
Enhancement.
ID[9:0]Identify Capability. The ID decodes the capabilities of AD1881A based on the following:
SE[4:0]Stereo Enhancement. The 3D stereo enhancement identifies the Analog Devices 3D stereo enhancement.
Master Volume Registers (Index 02h)
RMV[5:0]Right Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from
0 dB to a maximum attenuation of –94.5 dB.
LMV[5:0]Left Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from 0dB to
a maximum attenuation of –94.5 dB.Master Volume Mute. When this bit is set to “1,” the channel is muted.
Master Volume Mono (Index 06h)
MMV[4:0]Mono Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output fromdB to a maximum attenuation of –46.5 dB.
MMMMono Master Volume Mute. When this bit is set to “1,” the channel is muted.
PC Beep Register (Index 0Ah)
PCV[3:0]PC Beep Volume Control. The least significant bit represents 3 dB attenuation. This register controls the output
from 0 dB to a maximum attenuation of –45 dB. The PC Beep is routed to Left and Right Line outputs even when
the RESET pin is asserted. This is so that Power on Self-Test (POST) codes can be heard by the user in case of a
hardware problem with the PC.
PCMPC Beep Mute. When this bit is set to “1,” the channel is muted.
Phone Volume (Index 0Ch)
PHV[4:0]Phone Volume. Allows setting the Phone Volume Attenuator in 32 steps. The LSB represents 1.5 dB, and the
range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
PHMPhone Mute. When this bit is set to “1,” the channel is muted.
MIC Volume (Index 0Eh)
MCV[4:0]MIC Volume Gain. Allows setting the MIC Volume attenuator in 32 steps. The LSB represents 1.5 dB, and the
range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
M20Microphone 20 dB Gain Block
0 = Disabled; Gain = 0 dB.
1 = Enabled; Gain = 20 dB.
MCMMIC Mute. When this bit is set to “1,” the channel is muted.
Line In Volume (Index 10h)
RLV[4:0]Right Line In Volume. Allows setting the Line In right channel attenuator in 32 steps. The LSB represents 1.5dB,
and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
LLV[4:0]Line In Volume Left. Allows setting the Line In left channel attenuator in 32 steps. The LSB represents 1.5 dB, and
the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.Line In Mute. When this bit is set to “1,” the channel is muted.

Partno	Mfg	Dc	Qty	Available	Descript
AD1881A	AD	N/a	500	avai	AC?7 SoundMAX?Codec