AD1878JD-AD1879JD Fast Delivery |IC PHOENIX CO.,LIMITED

AD1879JD ,High Performance 16-/18-Bit Stereo ADCsSPECIFICATIONSTEST CONDITIONS UNLESS OTHERWISE NOTEDSupply Voltages ±5VAmbient Temperature 25 °CInp ..
AD1881 ,AC97 SoundMAX CodecFEATURESExternal Power AmpAC’97 2.1-CompliantSplit Power Supplies (3.3 V Digital/5 V Analog)Greater ..
AD1881A ,AC?7 SoundMAX?CodecSpecifications subject to change without notice.REV. 0–2–AD1881ADIGITAL DECIMATION AND INTERPOLATIO ..
AD1881A JST ,AC?7 SoundMAX CodecFEATURESPHAT™ Stereo 3D Stereo EnhancementDesigned for AC’97 Analog I/O ComponentSplit Power Suppli ..
AD1881AJST ,AC?7 SoundMAX CodecSPECIFICATIONSSTANDARD TEST CONDITIONS UNLESS OTHERWISE NOTEDTemperature 25 °CDAC Test ConditionsDi ..
AD1881AJST ,AC?7 SoundMAX CodecFEATURESVariable Sample RateMobile Low Power Mixer ModeTrue Line-Level OutputDigital Audio Mixer Mo ..
AD8332 ,Dual VGA with Ultralow Noise Preamplifier and Programmable RINapplications. Excellent bandwidth uniformity is overload to a subsequent ADC. An external resistor ..
AD8332ARU ,Dual VGA with Ultralow Noise Preamplifier and Programmable RINGENERAL DESCRIPTION 0.4V100.2VThe AD8331/AD8332 are single- and dual-channel ultralow 0noise, linea ..
AD8334ACPZ ,Quad VGA with Ultralow Noise Preamplifier and Programmable RINapplications.− the operating level of the detec-+tor. Then an example applica-ERRORtion revolving a ..
AD8335ACPZ ,Quad Low Noise, Low Cost Variable Gain Amplifierapplications, the PrAs can be powered down, significantly of ×8 (18.06 dB) and accepts input signal ..
AD8335ACPZ-REEL7 ,Quad Low Noise, Low Cost Variable Gain AmplifierFEATURES Low noise preamplifier (PrA) Voltage noise = 1.3 nV/√Hz typical 61 60 59 58 53 55 52 51 49 ..
AD8342ACPZ-REEL7 ,LF to 500MHz Active Receive Mixerapplications that require converted to a single-ended signal through the use of a match-wide bandwi ..

AD1878JD-AD1879JD
High Performance 16-/18-Bit Stereo ADCs
FUNCTIONAL BLOCK DIAGRAM
REV.0High Performance
16-/18-Bit SD Stereo ADCs
FEATURES
Fully Differential Dual Channel Analog Inputs
103 dB Signal-to-Noise (AD1879 typ)
–98 dB THD+N (AD1879 typ)
0.001 dB Passband Ripple and 115 dB Stopband
Attenuation
Fifth-Order, 64 Times Oversampling SD Modulator
Single Stage, Linear Phase Decimator
256 3 FS Input Clock
APPLICATIONS
Digital Tape Recorders
Professional, DCC, and DAT
A/V Digital Amplifiers
CD-R
Sound Reinforcement
PRODUCT OVERVIEW
The AD1879 is a two-channel, 18-bit oversampling ADC based
on ∑Δ technology and intended primarily for digital audio appli-
cations. The AD1878 is identical to the 18-bit AD1879 except
that it outputs 16-bit data words. Statements in this data sheet
should be read as applying to both parts unless otherwise noted.
Each input channel of these ADCs is fully differential. Each
data conversion channel consists of a fifth order one-bit noise
shaping modulator and a digital decimation filter. An on-chip
voltage reference provides a voltage source to both channels sta-
ble over temperature and time. Digital output data from both
channels is time-multiplexed to a single, flexible serial interface.
The AD1878/AD1879 accepts a 256 × FS input master clock.
Input signals are sampled at 64 × FS on switched-capacitors,
eliminating external sample-and-hold amplifiers and minimizing
the requirements for antialias filtering at the input. With simpli-
fied antialiasing, linear phase can be preserved across the passband.
The AD1878/AD1879’s proprietary fifth-order differential
switched-capacitor modulator architecture shapes the one-bit
comparator’s quantization noise out of the audio passband. The
high order of the modulator randomizes the modulator output,
reducing idle tones in the AD1878/AD1879 to very low levels.
The AD1878/AD1879’s differential architecture provides in-
creased dynamic range and excellent common-mode rejection
characteristics. Because its modulator is single-bit, AD1878/
AD1879 is inherently monotonic and has no mechanism for
producing differential linearity errors.
The digital decimation filters are single-stage, 4095-tap finite
impulse response filters for filtering the modulator’s high fre-
quency quantization noise and reducing the 64 × FS single-bit
output data rate to a FS word rate. They provide linear
*. Patent Numbers 5055843, 5126653, and others pending.
phase and a narrow transition band that permits the digitization
of 20 kHz signals while preventing aliasing into the passband
even when using a 44.1 kHz sampling frequency. Passband
ripple is less the 0.001 dB, and stopband attenuation exceeds
115 dB.
The flexible serial output port produces data in twos-complement,
MSB-first format. Input and output signals are to TTL and
CMOS-compatible logic levels. The port is configured by pin
selections. The AD1878/AD1879 can operate in either master
or slave mode. Each 16-/18-bit output word of a stereo pair can
be formatted within a 32-bit field as either right-justified, I2S-
compatible, or at user-selected positions. The output can also be
truncated to 16-bits by formatting into a 16-bit field.
The AD1878/AD1879 consists of two integrated circuits in a
single ceramic 28-pin DIP package. The modulators and refer-
ence are fabricated in a BiCMOS process; the decimator and
output port, in a 1.0 μm CMOS process. Separating these func-
tions reduces digital crosstalk to the analog circuitry. Analog and
digital supply connections are separated to further isolate the
analog circuitry from the digital supplies.
The AD1878/AD1879 operates from ±5 V power supplies over
the temperature range of –25°C to +70°C.
AD1878/AD1879–SPECIFICATIONS
TEST CONDITIONS UNLESS OTHERWISE NOTED
Supply Voltages±5V
Ambient Temperature25°C
Input Clock (FCLOCK)12.288MHz
Input Signal974Hz
–0.5dB Full Scale
All minimums and maximums tested except as noted.
ANALOG PERFORMANCE
NOTESBoth channels connected together for mono operations as described below in “How to Extend SNR.”Differential gain imbalance manually trimmed to eliminate second harmonic. See “Applications Issues” below.
AD1878/AD1879
DIGITAL INPUTS
VIH
DIGITAL TIMING
32-Bit Frame LRCK Pulse Width
WCK Pulse Width
tRSET
POWER
Dissipation
Power Supply Rejection
TEMPERATURE RANGE
AD1878/AD1879
ABSOLUTE MAXIMUM RATINGS
AVSS2 to AVSS1
Analog Inputs
AGND to DGND
Reference Voltage
Soldering
DIGITAL FILTER CHARACTERISTICS
Decimation Factor
Passband Ripple
Stopband
NOTEStopband repeats itself at multiples of 64 × FS, where FS is the output word rate. Thus the digital filter will attenuate to 115 dB across the frequency spectrum
except for a range ±0.5458 × FS wide at multiples of 64 × FS.
Specifications subject to change without notice.
ORDERING GUIDE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1878/AD1879 features proprietary ESD protection circuitry, permanent dam-
age may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
DEFINITIONS
Dynamic Range
The ratio of a full-scale output signal to the integrated output
noise in the passband (0 kHz to 20 kHz), expressed in decibels
(dB). Dynamic range is measured with a –60 dB input signal
and is equal to (S/[THD+N]) + 60 dB.
Signal to (Noise + Distortion)
The ratio of the root-mean-square (rms) value of the fundamen-
tal input signal to the rms sum of all spectral components in the
passband, expressed in decibels (dB).
Signal to Total Harmonic Distortion (THD)
The ratio of the rms sum of all harmonically related spectral
components in the passband to the fundamental input signal,
expressed either as a percentage (%) or in decibels (dB).
Passband
The region of the frequency spectrum unaffected by the attenu-
ation of the digital decimator’s filter.
Passband Ripple
The peak-to-peak variation in amplitude response from equal
amplitude input signal frequencies within the passband, ex-
pressed in decibels.
Stopband
The region of the frequency spectrum attenuated by the digi-
tal decimator’s filter to the degree specified by “stopband
attenuation.”
Gain Error
With a near full-scale input, the ratio of actual output to ex-
pected output, expressed as a percentage.
Interchannel Gain Mismatch
With near full-scale inputs, the ratio of outputs of the two stereo
channels, expressed in decibels.
Gain Drift
Change in response to a near full-scale input with a change in
temperature, expressed as parts-per-million (ppm) per °C.
Midscale Offset Error
Output response to a midscale input (i.e., zero volts dc), ex-
pressed in least-significant bits (LSBs).
Midscale Drift
Change in midscale offset error with a change in temperature,
expressed as parts-per-million (ppm) of full scale per °C.
Crosstalk
Ratio of response on one channel with a grounded input to a
full-scale 1 kHz sine-wave input on the other channel, expressed
in decibels.
Interchannel Phase Deviation
Difference in input sampling times between stereo channels, ex-
pressed as a phase difference in degrees between 1 kHz inputs.
Power Supply Rejection
With analog inputs grounded, energy at the output when a
300 mV p-p signal is applied to power supply pins, expressed in
decibels of full scale.
Group Delay
Intuitively, the time interval required for an input pulse to ap-
Group Delay Variation
The difference in group delays at different input frequencies.
Specified as the difference between largest and the smallest
group delays in the passband, expressed in microseconds (μs).
AD1878/AD1879 PIN LIST
THEORY OF OPERATION Modulator Noise-Shaping
The stereo, differential analog modulators of the AD1878/
AD1879 employ a proprietary feedforward and feedback archi-
tecture that passes input signals in the audio band with a unity
transfer function yet simultaneously shape the quantization
noise generated by the one-bit comparator out of the audio
band. See Figure 1. Without the ∑Δ architecture, this quantiza-
tion noise would be spread uniformly from dc to one-half the
oversampling frequency, 64 × FS. (Regardless of architecture,
64 times oversampling by itself significantly reduces the quanti-
zation noise in the audio band if the input is properly dithered.
However, the noise reduction is only [log2 64] × 3 dB = 18 dB.)
AD1878/AD1879
The AD1878/AD1879’s patented ∑Δ architectures “shape” the
quantization noise-transfer function in a nonuniform manner.
Through careful design, this transfer function can be specified to
high-pass filter the quantization noise out of the audio band into
higher frequency regions. See Figure 27. The Analog Devices’
AD1878/AD1879 also incorporates feedback resonators from
the third integrator’s output to the second integrator’s input and
from the fifth integrator’s output to the fourth integrators’ input.
These resonators do not affect the signal transfer function but
allow flexible placement of zeros in the noise transfer function.
For the AD1878/AD1879, these zeros were placed near the high
frequency end of the audio passband, reducing the quantization
noise in a region where it otherwise would have been increasing.
Oversampling by 64 simplifies the implementation of a high per-
formance audio analog-to-digital conversion system. Antialias
requirements are minimal; a single pole of filtering will usually
suffice to eliminate inputs near FS and its higher multiples.
A fifth-order architecture was chosen both to strongly shape the
noise out of the audio band and to help break up the idle tones
produced in all ∑Δ architectures. These architectures have a ten-
dency to generate periodic patterns with a constant dc input, a
response that looks like a tone in the frequency domain. These
idle tones have a direct frequency dependence on the input dc
offset and indirect dependence on temperature and time as it
affects dc offset. The human ear operates effectively like a spec-
trum analyzer and can be sensitive to tones below the integrated
noise floor, depending on frequency and level. The AD1878/
AD1879 suppresses idle tones typically 110 dB or better below
full-scale input levels.
Previously it was thought that higher-order modulators could
not be designed to be globally stable. However, the AD1878/
AD1879’s modulator was designed, simulated, and exhaustively
tested to remain stable for any input within a wide tolerance of
its rated input range. The AD1878/AD1879 was designed to
reset itself should it ever be overdriven and go unstable. It will
reset itself within 5 μs at a 48 kHz sampling frequency. Any such
reset events will be invisible to the user since overdriving the in-
puts will produce a “clipped” waveform at the output.
The AD1878/AD1879 modulator architecture has been imple-
mented using switched-capacitors. A systems benefit is that ex-
ternal sample-and-hold amplifiers are unnecessary since the
capacitors perform the sample-and-hold function Coefficient
weights are created out of varying capacitor sizes. The dominant
noise source in this design is kT/C noise, and the input capaci-
tors are accordingly very large to achieve the AD1878/AD1879’s
performance levels. (Each 6 dB improvement in dynamic range
requires a quadrupling of input capacitor size, as well as an
increase in size of the op amps to drive them.) This AD1878/
AD1879 thermal noise has been controlled to properly dither the
input to an 18-bit level. (Note that 16-bit results from either the
AD1878 or AD1879 will be underdithered.)
With capacitors of adequate size and op amps of adequate drive,
a well-designed switched-capacitor modulator will be relatively
insensitive to jitter on the sampling clock. The key issue is
whether the capacitors have had sufficient time to charge or
discharge during the clock period. A properly designed switched
continuous-time modulators, which are very sensitive to the
exact location of sampling clock edges.
See Figures 20–23 for illustrations of the AD1878/AD1879’s
typical analog performance resulting from this design. Signal-
to-noise+distortion is shown under a range of conditions. Note
the very good linearity performance of the AD1878/AD1879 as
a consequence of its single-bit ∑Δ architecture in Figure 24.
The common-mode rejection (Figure 25) graph illustrates the
benefits of the AD1878/AD1879’s differential architecture. The
excellent channel separation shown in Figure 26 is the result of
careful chip design and layout. The relatively small change in
gain over temperature (Figure 31) results from a robust refer-
ence design.
The output of the AD1878/AD1879 modulators is a stereo
bitstream at 64 × FS (3.072 MHz for FS = 48 kHz). Spectral
analysis of these bits would show that they contain a high qual-
ity replica of the input in the audio band and an enormous
amount of quantization noise at higher frequencies. The input
signal can be recreated directly if these bits are fed into a prop-
erly designed analog low-pass filter.
Digital Filter Characteristics
The digital decimator accepts the modulators’ stereo bitstream
and simultaneously performs two operations on it. First, the
decimator low-pass filters the quantization noise that the modu-
lator shaped to high frequencies and filters any other out-of-
audio-band input signals. Second, it reduces the data rate to an
output word rate equal to FS. The high frequency bitstream is
reduced to stereo 16-/18-bit words at 48 kHz (or other desired
FS). The one-bit quantization noise, other high-frequency com-
ponents of the bitstream, and analog signals in the stopband are
attenuated by at least 115 dB.
The AD1878/AD1879 decimator implements a symmetric Finite
Impulse Response (FIR) filter, resulting in its linear phase re-
sponse. This filter achieves a narrow transition band (0.0923 ×
FS), high stopband attenuation (> 115 dB), and low passband
ripple (< 0.001 dB). The narrow transition band allows the
unattenuated digitization of 20 kHz input signals with FS as low
as 44.1 kHz. The stopband attenuation is sufficient to eliminate
modulator quantization noise from affecting the output. Low
passband ripple prevents the digital filter from coloring the
audio signal. For this level of performance, 4095 22-bit coeffic-
ients (taps) were required in each channel of this filter. The
AD1878/AD1879’s decimator employs a proprietary single-
stage, multiplier-free structure developed in conjunction with
Ensoniq Corporation. See Figures 28 and 29 for the digital
filter’s characteristics.
The output from the decimator is available as a single serial
output, multiplexed between left and right channels.
Note that the digital filter itself is operating at 64 × FS. As a
consequence, Nyquist images of the passband, transition band,
and stopband will be repeated in the frequency spectrum at
multiples of 64 × FS. Thus the digital filter will attenuate to
115 dB across the frequency spectrum except for a window
±0.5458 × FS wide centered at multiples of 64 × FS. Any input
signals, clock noise, or digital noise in these frequency windows
Sample Delay
The sample delay or “group delay” of the AD1878/AD1879 is
dominated by the processing time of the digital decimation fil-
ter. FIR filters convolve a vector representing time samples of
the input with an equal-sized vector of coefficients. After each
convolution, the input vector is updated by adding a new
sample at one end of the “pipeline” and eliminating the oldest
input sample at the other. For an FIR filter, the time at which a
step input appears at the output will be approximately when that
step input is halfway through the input sample vector pipeline.
The input sample vector is updated every 64 × FS. Thus, the
sample delay will be given by the equation,
Group Delay = (40964 2) /(64 × FS) = 32 / FS
For the most common sample rates this can be summarized as:
Due to the linear phase properties of FIR filters, the group delay
variation, or differences in group delay at different frequencies is
zero.
OPERATING FEATURES
Voltage Reference
The AD1878/AD1879 includes a +3 V on-board reference
which determines the AD1878/AD1879’s input range. This ref-
erence is buffered to both channels of the AD1878/AD1879’s
modulator, providing a well-matched reference to minimize
interchannel gain mismatch. The reference should be bypassed
with 10 μF tantalum capacitors as shown in Figure 2. The inter-
nal reference can be overpowered by applying an external refer-
ence at the REFR (Pin 14) and REFL (Pin 15) pins, allowing
multiple AD1878/AD1879s to be calibrated to the same gain.
Note that the reference pins still must be bypassed as shown.
Sample Clock
An external master clock supplied to CLOCK (Pin 26) drives
the AD1878/AD1879 modulator, decimator, and digital inter-
face. As with any analog-to-digital conversion system, the sam-
pling clock must be low jitter to prevent conversion errors.
The input clock operates at 256 × FS. The clock is divided down
to obtain the 64 × FS clock required for the modulator. The out-
put word rate will be at FS itself. This relationship is illustrated
for popular sample rates below:
The AD1878/AD1879 serial interface supports both “master”
and “slave” modes. Note that even in slave mode it is presumed
that the serial interface clocks are derived from the master clock
The AD1878/AD1879 decimator makes use of dynamic logic to
minimize die area. There is, therefore, a minimum clock fre-
quency that the AD1878/AD1879 will support specified in
“Specifications” above. Operation of the AD1878/AD1879 at
lower frequencies will cause the device to consume excessive
power and may damage the converter.
Reset
The active LO RESET pin (Pin 24) allows initializing the
AD1879. This is of value only for synchronizing multiple
AD1878/AD1879s in Master Mode—WCK Output. Unless you
are interested in synchronizing multiple AD1878/AD1879s, we
recommend tying RESET HI. The reset function is useful for
nothing else. In fact, there is a maximum specification on
RESET LO; excessive power consumption may occur with loss
of reliability if left LO too long due to the dynamic logic on the
chip.
Figure 14 illustrates the timing parameters for RESET to
accomplish synchronization of multiple Master Mode—Word
Clock Output ADCs. (This sequence is not necessary for syn-
chronizing multiple AD1878/AD1879s in other modes. See
“Synchronizing Multiple AD1878/AD1879s” below.) Note that
RESET first has to be LO for at least four CLOCK periods
(three CLOCKs plus tRSET plus tRHLD, to be more precise).
Then RESET must be HI for a minimum of one CLOCK and a
maximum of two CLOCKs. Then RESET must he LO for at
least another four CLOCKs. From the time when RESET goes
HI again, exactly 127 CLOCKs will occur before LRCK goes
LO.
Analog Power Down
The AD1878/AD1879 features a power-down mode that
reduces current to the analog modulator. It is controlled by
the active HI APD (Pin 11). The power savings are specified in
“Specifications.” The converter is still “alive” in the power-
down state but will not produce valid results for all audio-band
inputs.
Power consumption can be further reduced by slowing down
the master clock input to the minimum clock frequency,
FCLOCK, specified for the AD1878/AD1879.
APPLICATIONS ISSUES
Recommended Input Structure
The AD1878/AD1879 input structure is fully differential for
improved common-mode rejection properties and increased
dynamic range. Since each input pin sees ±3 V swings, each
channel’s input signal effectively swings ±6 V, i.e., across a
12 V range.
In most cases, a single-ended-to-differential input circuit is
required. Shown in Figure 2 is our recommended circuit, based
on extensive experimentation. Note that to maximize signal
swing, the op amps in this circuit are powered by ±12 V or
greater supplies. The AD1878/AD1879 itself requires ±5 V
supplies. If ±5 V supplies are not already available in your sys-
tem, Figure 3 illustrates our recommended circuit for generat-
ing these supplies.
AD1878/AD1879
RIGHT INPUT
NE5532 OR OP-275100pF
249kΩVSS
LEFT
INPUT
100pFV
10µF
Figure 2.AD1878/AD1879 Recommended Input StructureCC
AGNDSSDD
DGND
+12V < VCC < +18V
–12V > VSS > – 18V
Figure 3.AD1878/AD1879 Recommended Power Condi-
tioning Circuit (If ±5 V Supplies Are Not Already Available)
The trim potentiometers shown in Figure 2 connecting the
minus (–) inputs of the driving op amps permit trimming out dc
offset, if desired.
Note that the driving op amp feedback resistors are all slightly
different values. These values produce a slight differential gain
imbalance and were derived empirically to minimize second
harmonic distortion on average and produce the best overall
THD without part-by-part trimming. Replacing one of these
feedback resistors in each channel with a trim potentiometer
allows trimming the differential gain imbalance for part-by-part
optimal performance. We have done this in the lab by parallel-
ing 100 kΩ trim potentiometers around the 5.49 kΩ and
5.36 kΩ input feedback resistors for the VIN plus (+) signals
that can be found in Figure 2. By trimming gain imbalance, sec-
ond harmonic distortion can always be eliminated. In “Specifi-
the input structure shown in Figure 2. The trimmed specifica-
tions are based on a part-by-part trim of this differential gain to
eliminate the second harmonic.
The input circuit of Figure 2 could be implemented with a
single pair of operational amplifiers per channel, one inverting
and one noninverting. The recommended architecture shown in
Figure 2 using three inverting op amps per channel provides iso-
lation of the op amp inputs from charge dumped back from the
AD1878/AD1879’s input capacitors when these large capacitors
switch. The performance from a two op amp per channel input
structure is not quite as good as the structure recommended,
but it is close and may be adequate in many applications.
Layout and Decoupling Considerations
Obtaining the best possible performance from a state-of-the-art
data converter like the AD1878/AD1879 requires close atten-
tion to board layout. From extensive experimentation, we have
discovered principles that produce typical values of 103 dB dy-
namic range and 98 dB S/(THD+N) in your system. Schematics
of our AD1878/AD1879 Evaluation Board, which implements
these recommendations, are available from Analog Devices.
The principles and their rationales are listed below in descend-
ing order of importance. The first two pertain to bypassing and
are illustrated in Figure 4.
Figure 4.AD1878/AD1879 Recommended Bypassing and
Oscillator CircuitsThe digital bypassing of the AD1878/AD1879 is the most
critical item on the board layout. There are two pairs of digi-
tal supply pins of the part, each pair on opposite sides (Pins 5
and 6 and Pins 22 and 23). The user should tie a bypass ca-
pacitor set (0.1 μF ceramic and 10 μF tantalum) on EACH
pair of supply pins as close to the pins as possible. The traces
between these package pins and the capacitors should be as
short and as wide as possible. This will prevent digital supply
current transients from being inductively transmitted to the
inputs of the part.The analog input bypassing is the second most critical item.
Use 0.01 μF NPO ceramic capacitors from each input pin to
the analog ground plane, with a clear ground path from the
bypass capacitor to the AGND pin on the same side of the
package (Pins 10 and 18). The trace between this package

Partno	Mfg	Dc	Qty	Available	Descript
AD1878JD		N/a	4	avai	High Performance 16-/18-Bit Stereo ADCs
AD1879JD	AD	N/a	33	avai	High Performance 16-/18-Bit Stereo ADCs