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AD1877JR
Single-Supply 16-Bit Stereo ADC
FUNCTIONAL BLOCK DIAGRAMREV.A
Single-Supply
16-Bit �� Stereo ADC
FEATURES
Single 5 V Power Supply
Single-Ended Dual-Channel Analog Inputs
92 dB (Typ) Dynamic Range
90 dB (Typ) S/(THD+N)
0.006 dB Decimator Passband Ripple
Fourth-Order, 64-Times Oversampling �� Modulator
Three-Stage, Linear-Phase Decimator
256 � FS or 384 � FS Input Clock
Less than 100 �W (Typ) Power-Down Mode
Input Overrange Indication
On-Chip Voltage Reference
Flexible Serial Output Interface
28-Lead SOIC Package
APPLICATIONS
Consumer Digital Audio Receivers
Digital Audio Recorders, Including Portables
CD-R, DCC, MD and DAT
Multimedia and Consumer Electronic Equipment
Sampling Music Synthesizers
Digital Karaoke Systemsone-bit comparator’s quantization noise out of the audio pass-
band. The high order of the modulator randomizes the modulator
output, reducing idle tones in the AD1877 to very low levels.
Because its modulator is single-bit, AD1877 is inherently
monotonic and has no mechanism for producing differential
linearity errors.
The input section of the AD1877 uses autocalibration to correct
any dc offset voltage present in the circuit, provided that the inputs
are ac coupled. The single-ended dc input voltage can swing
between 0.7 V and 3.8 V typically. The AD1877 antialias input
circuit requires four external 470 pF NPO ceramic chip filter
capacitors, two for each channel. No active electronics are
needed. Decoupling capacitors for the supply and reference pins
are also required.
The dual digital decimation filters are triple-stage, finite impulse
response filters for effectively removing the modulator’s high
frequency quantization noise and reducing the 64 × FS single-bit
output data rate to an FS word rate. They provide linear phase
and a narrow transition band that properly digitizes 20 kHz signals
at a 44.1 kHz sampling frequency. Passband ripple is less than
0.006 dB, and stopband attenuation exceeds 90 dB.
(Continued on Page 6)
PRODUCT OVERVIEWThe AD1877 is a stereo, 16-bit oversampling ADC based on
Sigma Delta (∑∆) technology intended primarily for digital
audio bandwidth applications requiring a single 5 V power supply.
Each single-ended channel consists of a fourth-order one-bit
noise shaping modulator and a digital decimation filter. An on-
chip voltage reference, stable over temperature and time, defines
the full-scale range for both channels. Digital output data from
both channels are time-multiplexed to a single, flexible serial
interface. The AD1877 accepts a 256 × FS or a 384 × FS input
clock (FS is the sampling frequency) and operates in both serial
port “master” and “slave” modes. In slave mode, all clocks must
be externally derived from a common source.
Input signals are sampled at 64 × FS onto internally buffered
switched-capacitors, eliminating external sample-and-hold ampli-
fiers and minimizing the requirements for antialias filtering at the
input. With simplified antialiasing, linear phase can be preserved
across the passband. The on-chip single-ended to differential signal
converters save the board designer from having to provide them
externally. The AD1877’s internal differential architecture provides
increased dynamic range and excellent power supply rejection
characteristics. The AD1877’s proprietary fourth-order differen-
tial switched-capacitor ∑∆ modulator architecture shapes the
*. Patent Numbers 5055843, 5126653, and others pending.
AD1877–SPECIFICATIONS
TEST CONDITIONS UNLESS OTHERWISE NOTEDSupply Voltages5.0V
Ambient Temperature25°C
Input Clock (FCLKIN) [256 × FS]12.288MHz
Input Signal991.768Hz
–0.5dB Full Scale
Measurement Bandwidth23.2 Hz to 19.998 kHz
Load Capacitance on Digital Outputs50pF
Input Voltage HI (VIH)2.4V
Input Voltage LO (VIL)0.8V
Master Mode, Data I2S-Justified (Refer to Figure 14).
Device Under Test (DUT) bypassed and decoupled as shown in Figure 3.
DUT is antialiased and ac coupled as shown in Figure 2. DUT is calibrated.
Values in bold typeface are tested, all others are guaranteed but not tested.
ANALOG PERFORMANCEVREF
DC Accuracy
*VIN p-p = VREF × 1.333.
DIGITAL I/OInput Voltage LO (VIL)
Output Voltage LO (VOL @ IOL = 2 mA)
DIGITAL TIMING (Guaranteed over 0°C to 70°C, DVDD = AVDD = 5 V ± 5%. Refer to Figures 17–19.)FCLKIN
tCPWH
tRPWL
tBPWL
tBPWH
tDLYCKB
tDLYBWR
tDLYLRDT
tSETWBS
tDLYBDT
POWERSupplies
Dissipation
AD1877
AD1877
TEMPERATURE RANGESpecifications Guaranteed
Functionality Guaranteed
DIGITAL FILTER CHARACTERISTICSDecimation Factor
Passband Ripple
Stopband
48 kHz FS (at Recommended Crystal Frequencies)
NOTESStopband repeats itself at multiples of 64 × FS, where FS is the output word rate. Thus the digital filter will attenuate to 0 dB across the frequency spectrum except
for a range ±0.55 × FS wide at multiples of 64 × FS.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGSAVDD to AGND/AGNDL/AGNDR
Digital Inputs
Analog Inputs
ORDERING GUIDE
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD1877 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
PIN FUNCTION DESCRIPTIONS
DEFINITIONS
Dynamic RangeThe ratio of a full-scale output signal to the integrated output
noise in the passband (20 Hz to 20 kHz), expressed in decibels
(dB). Dynamic range is measured with a –60 dB input signal
and is equal to (S/[THD+N]) 60 dB. Note that spurious har-
monics are below the noise with a –60 dB input, so the noise
level establishes the dynamic range. The dynamic range is speci-
fied with and without an A-Weight filter applied.
Signal to (Total Harmonic Distortion + Noise)
(S/(THD + N))The ratio of the root-mean-square (rms) value of the fundamen-
tal input signal to the rms sum of all other spectral components
in the passband, expressed in decibels (dB).
Signal to Total Harmonic Distortion (S/THD)The ratio of the rms value of the fundamental input signal to the
rms sum of all harmonically related spectral components in the
passband, expressed in decibels.
PassbandThe region of the frequency spectrum unaffected by the attenu-
ation of the digital decimator’s filter.
Passband RippleThe peak-to-peak variation in amplitude response from equal-
amplitude input signal frequencies within the passband,
expressed in decibels.
StopbandThe region of the frequency spectrum attenuated by the digital
decimator’s filter to the degree specified by “stopband
attenuation.”
Gain ErrorWith a near full-scale input, the ratio of actual output to
expected output, expressed as a percentage.
Interchannel Gain MismatchWith identical near full-scale inputs, the ratio of outputs of the
two stereo channels, expressed in decibels.
Gain DriftChange in response to a near full-scale input with a change in
temperature, expressed as parts-per-million (ppm) per °C.
Midscale Offset ErrorOutput response to a midscale dc input, expressed in least-
significant bits (LSBs).
Midscale DriftChange in midscale offset error with a change in temperature,
expressed as parts-per-million (ppm) per °C.
Crosstalk (EIAJ Method)Ratio of response on one channel with a grounded input to a
full-scale 1 kHz sine-wave input on the other channel, expressed
in decibels.
Power Supply RejectionWith no analog input, signal present at the output when a
300 mV p-p signal is applied to power supply pins, expressed in
decibels of full scale.
Group DelayIntuitively, the time interval required for an input pulse to
appear at the converter’s output, expressed in milliseconds
(ms). More precisely, the derivative of radian phase with respect
to radian frequency at a given frequency.
Group Delay VariationThe difference in group delays at different input frequencies.
Specified as the difference between largest and the smallest
group delays in the passband, expressed in microseconds (µs).
AD1877(Continued from Page 1 )
The flexible serial output port produces data in twos-comple-
ment, MSB-first format. The input and output signals are TTL
compatible. The port is configured by pin selections. Each 16-bit
output word of a stereo pair can be formatted within a 32-bit
field of a 64-bit frame as either right-justified, I2S-compatible,
Word Clock controlled or left-justified positions. Both 16-bit
samples can also be packed into a 32-bit frame, in left-justified
and I2S-compatible positions.
The AD1877 is fabricated on a single monolithic integrated circuit
using a 0.8 µm CMOS double polysilicon, double metal process,
and is offered in a plastic 28-lead SOIC package. Analog and
digital supply connections are separated to isolate the analog cir-
cuitry from the digital supply and reduce digital crosstalk.
The AD1877 operates from a single 5 V power supply over the
temperature range of 0°C to 70°C, and typically consumes less
than 260 mW of power.
THEORY OF OPERATION�� Modulator Noise-Shaping
The stereo, internally differential analog modulator of the
AD1877 employs a proprietary feedforward and feedback archi-
tecture that passes input signals in the audio band with a unity
transfer function yet simultaneously shapes the quantization
noise generated by the one-bit comparator out of the audio
band. See Figure 1. Without the ∑∆ architecture, this quantiza-
tion noise would be spread uniformly from dc to one-half the
oversampling frequency, 64 × FS.
Figure 1.Modulator Noise-Shaper (One Channel)
∑∆ architectures “shape” the quantization noise-transfer function
in a nonuniform manner. Through careful design, this transfer
function can be specified to high-pass filter the quantization
noise out of the audio band into higher frequency regions. The
AD1877 also incorporates a feedback resonator from the fourth
integrator’s output to the third integrator’s input. This resonator
does not affect the signal transfer function but allows the flexible
placement of a zero in the noise transfer function for more effec-
tive noise shaping.
Oversampling by 64 simplifies the implementation of a high per-
formance audio analog-to-digital conversion system. Antialias
requirements are minimal; a single pole of filtering will usually
suffice to eliminate inputs near FS and its higher multiples.
A fourth-order architecture was chosen both to strongly shape
the noise out of the audio band and to help break up the idle
tones produced in all ∑∆ architectures. These architectures have
offset and indirect dependence on temperature and time as it
affects dc offset. The AD1877 suppresses idle tones 20 dB or
better below the integrated noise floor.
The AD1877’s modulator was designed, simulated, and exhaus-
tively tested to remain stable for any input within a wide tolerance
of its rated input range. The AD1877 is designed to internally
reset itself should it ever be overdriven, to prevent it from going
instable. It will reset itself within 5 µs at a 48 kHz sampling
frequency after being overdriven. Overdriving the inputs will
produce a waveform “clipped” to plus or minus full scale.
See TPCs 1 through 16 for illustrations of the AD1877’s
typical analog performance as measured by an Audio Precision
System One. Signal-to(distortion + noise) is shown under a
range of conditions. Note that there is a small variance between
the AD1877 analog performance specifications and some of the
performance plots. This is because the Audio Precision System
One measures THD and noise over a 20 Hz to 24 kHz band-
width, while the analog performance is specified over a 20 Hz to
20 kHz bandwidth (i.e., the AD1877 performs slightly better
than the plots indicate). The power supply rejection (TPC 5)
graph illustrates the benefits of the AD1877’s internal differen-
tial architecture. The excellent channel separation shown in
TPC 6 is the result of careful chip design and layout.
Digital Filter CharacteristicsThe digital decimator accepts the modulator’s stereo bitstream
and simultaneously performs two operations on it. First, the
decimator low-pass filters the quantization noise that the modu-
lator shaped to high frequencies and filters any other out-of
audio-band input signals. Second, it reduces the data rate to an
output word rate equal to FS. The high frequency bitstream is
decimated to stereo 16-bit words at 48 kHz (or other desired
FS). The out-of-band one-bit quantization noise and other high
frequency components of the bitstream are attenuated by at
least 90 dB.
The AD1877 decimator implements a symmetric Finite Impulse
Response (FIR) filter which possesses a linear phase response.
This filter achieves a narrow transition band (0.1 × FS), high
stopband attenuation (> 90 dB), and low passband ripple
(< 0.006 dB). The narrow transition band allows the unattenu-
ated digitization of 20 kHz input signals with FS as low as
44.1 kHz. The stopband attenuation is sufficient to eliminate
modulator quantization noise from affecting the output. Low
passband ripple prevents the digital filter from coloring the
audio signal. See TPC 7 for the digital filter’s characteristics.
The output from the decimator is available as a single serial
output, multiplexed between left and right channels.
Note that the digital filter itself is operating at 64 × FS. As a
consequence, Nyquist images of the passband, transition band,
and stopband will be repeated in the frequency spectrum at
multiples of 64 × FS. Thus the digital filter will attenuate to
greater than 90 dB across the frequency spectrum except for a
window ±0.55 × FS wide centered at multiples of 64 × FS. Any
input signals, clock noise, or digital noise in these frequency
windows will not be attenuated to the full 90 dB. If the high
frequency signals or noise appear within the passband images
within these windows, they will not be attenuated at all, and
Sample DelayThe sample delay or “group delay” of the AD1877 is dominated
by the processing time of the digital decimation filter. FIR fil-
ters convolve a vector representing time samples of the input
with an equal-sized vector of coefficients. After each convolu-
tion, the input vector is updated by adding a new sample at one
end of the “pipeline” and discarding the oldest input sample at
the other. For an FIR filter, the time at which a step input appears
at the output will be when that step input is half way through
the input sample vector pipeline. The input sample vector
is updated every 64 × FS. The equation which expresses the
group delay for the AD1877 is:
Group Delay (sec) = 36/FS (Hz)
For the most common sample rates this can be summarized as:
Due to the linear phase properties of FIR filters, the group
delay variation, or differences in group delay at different fre-
quencies is essentially zero.
OPERATING FEATURES
Voltage Reference and External Filter CapacitorsThe AD1877 includes a +2.25 V on-board reference that deter-
mines the AD1877’s input range. The left and right reference
pins (14 and 15) should be bypassed with a 0.1 µF ceramic chip
capacitor in parallel with a 4.7 µF tantalum as shown below in
Figure 3. Note that the chip capacitor should be closest to the
pin. The internal reference can be overpowered by applying an
external reference voltage at the VREFL (Pin 14) and VREFR
(Pin 15) pins, allowing multiple AD1877s to be calibrated to
the same gain. It is not possible to overpower the left and right
reference pins individually; the external reference voltage
should be applied to both Pin 14 and Pin 15. Note that the ref-
erence pins must still be bypassed as shown in Figure 3.
It is possible to bypass each reference pin (VREFL and VREFR)
with a capacitor larger than the suggested 4.7 µF, however it is
not recommended. A larger capacitor will have a longer charge-
up time which may extend into the autocalibration period, yield-
ing incorrect results.
The AD1877 requires four external filter capacitors on Pins 11,
12, 17 and 18. These capacitors are used to filter the single-to
differential converter outputs, and are too large for practical
integration onto the die. They should be 470 pF NPO ceramic
chip type capacitors as shown in Figure 3, placed as close to the
AD1877 package as possible.
Sample ClockAn external master clock supplied to CLKIN (Pin 28) drives
the AD1877 modulator, decimator, and digital interface. As
with any analog-to-digital conversion system, the sampling clock
must be low jitter to prevent conversion errors. If a crystal oscil-
lator is used as the clock source, it should be bypassed with a
0.1 µF capacitor, as shown below in Figure 3.
For the AD1877, the input clock operates at either 256 × FS or
384 × FS as selected by the 384/256 pin. When 384/256 is HI,
the 384 mode is selected and when 384/256 is LO, the 256
mode is selected. In both cases, the clock is divided down to
obtain the 64 × FS clock required for the modulator. The out-
put word rate itself will be at FS. This relationship is illustrated
for popular sample rates below:
The AD1877 serial interface will support both master and slave
modes. Note that in slave mode it is required that the serial
interface clocks are externally derived from a common source.
In master mode, the serial interface clock outputs are internally
derived from CLKIN.
Reset, Autocalibration and Power DownThe active LO RESET pin (Pin 23) initializes the digital deci-
mation filter and clears the output data buffer. While in the reset
state, all digital pins defined as outputs of the AD1877 are
driven to ground (except for BCLK, which is driven to the state
defined by RDEDGE (Pin 6)). Analog Devices recommends
resetting the AD1877 on initial power up so that the device is
properly calibrated. The reset signal must remain LO for the
minimum period specified in “Specifications” above. The reset
pulse is asynchronous with respect to the master clock, CLKIN.
If, however, multiple AD1877s are used in a system, and it is
desired that they leave the reset state at the same time, the
common reset pulse should be made synchronous to CLKIN
(i.e., RESET should be brought HI on a CLKIN falling edge).
Multiple AD1877s can be synchronized to each other by using
a single master clock and a single reset signal to initialize all
devices. On coming out of reset, all AD1877s will begin sam-
pling at the same time. Note that in slave mode, the AD1877 is
inactive (and all outputs are static, including WCLK) until the
first rising edge of LRCK after the first falling edge of LRCK.
This initial low going then high going edge of LRCK can be used
to “skew” the sampling start-up time of one AD1877 relative to
other AD1877s in a system. In the Data Position Controlled by
WCLK Input mode, WCLK must be HI with LRCK HI, then
WCLK HI with LRCK LO, then WCLK HI with LRCK HI
before the AD1877 starts sampling.
The AD1877 achieves its specified performance without the
need for user trims or adjustments. This is accomplished
through the use of on-chip automatic offset calibration that
takes place immediately following reset. This procedure nulls
out any offsets in the single-to-differential converter, the analog
modulator and the decimation filter. Autocalibration completes
in approximately 8192 × (1/(FLRCK) seconds, and need only be
performed once at power-up in most applications. [In slave
mode, the 8192 cycles required for autocalibration do not start
until after the first rising edge of LRCK following the first fall-
ing edge of LRCK.] The autocalibration scheme assumes that
the inputs are ac coupled. DC coupled inputs will work with the
AD1877The AD1877 also features a power-down mode. It is enabled by
the active LO RESET Pin 23 (i.e., the AD1877 is in powerdown
mode while RESET is held LO). The power savings are speci-
fied in the ‘’Specifications’’ section above. The converter is shut
down in the power-down state and will not perform conversions.
The AD1877 will be reset upon leaving the power-down state, and
autocalibration will commence after the RESET pin goes HI.
Power consumption can be further reduced by slowing down the
master clock input (at the expense of input passband width).
Note that a minimum clock frequency, FCLKIN, is specified for
the AD1877.
Tag Overrange OutputThe AD1877 includes a TAG serial output (Pin 27) which is
provided to indicate status on the level of the input voltage. The
TAG output is at TTL compatible logic levels. A pair of unsigned
binary bits are output, synchronous with LRCK (MSB then
LSB), that indicate whether the current signal being converted
is: more than 1 dB under full scale; within 1 dB under full scale;
within 1 dB over full scale; or more than 1 dB over full scale.
The timing for the TAG output is shown in TPCs 7 through 16.
Note that the TAG bits are not “sticky,” i.e., they are not peak
reading, but rather change with every sample. Decoding of these
two bits is as follows:
APPLICATIONS ISSUES
Recommended Input StructureThe AD1877 input structure is single-ended to allow the board
designer to achieve a high level of functional integration. The
very simple recommended input circuit is shown in Figure 2.
Note the 1 µF ac coupling capacitor which allows input level
shifting for 5 V only operation, and for autocalibration to
properly null offsets. The 3 dB point of the single-pole antialias
RC filter is 240 kHz, which results in essentially no attenuation
at 20 kHz. Attenuation at 3 MHz is approximately 22 dB, which
is adequate to suppress FS noise modulation. If the analog inputs
are externally ac coupled, then the 1 µF ac coupling capacitors
shown in Figure 2 are not required.
Figure 2.Recommended Input Structure for Externally
DC Coupled Inputs
Analog Input Voltage SwingThe single-ended input range of the analog inputs is specified in
relative terms in the “Specifications” section of this data sheet.
The input level at which clipping occurs linearly tracks the voltage
reference level, i.e., if the reference is high relative to the typical
2.25 V, the allowable input range without clipping is corre-
spondingly wider; if the reference is low relative to the typical
2.25 V, the allowable input range is correspondingly narrower.
Thus the maximum input voltage swing can be computed using
the following ratio:
Layout and Decoupling ConsiderationsObtaining the best possible performance from the AD1877
requires close attention to board layout. Adhering to the follow-
ing principles will produce typical values of 92 dB dynamic
range and 90 dB S/(THD+N) in target systems. Schematics and
layout artwork of the AD1877 Evaluation Board, which implement
these recommendations, are available from Analog Devices.
The principles and their rationales are listed below. The first
two pertain to bypassing and are illustrated in Figure 3.
Figure 3.Recommended Bypassing and Oscillator Circuits
There are two pairs of digital supply pins on opposite sides of
the part (Pins 4 and 5 and Pins 24 and 25). The user should
tie a bypass chip capacitor (10 nF ceramic) in parallel with a
decoupling capacitor (1 µF tantalum) on EACH pair of supply
pins as close to the pins as possible. The traces between these
package pins and the capacitors should be as short and as wide
as possible. This will prevent digital supply current transients
from being inductively transmitted to the inputs of the part.
Use a 0.1 µF chip analog capacitor in parallel with a 1.0 µF
tantalum capacitor from the analog supply (Pin 9) to the analog
ground plane. The trace between this package pin and the
capacitor should be as short and as wide as possible.
The AD1877 should be placed on a split ground plane. The
digital ground plane should be placed under the top end of the
package, and the analog ground plane should be placed under
The ground planes should be tied together at one spot under-
neath the center of the package with an approximately 3 mm
trace. This ground plane technique also minimizes RF transmis-
sion and reception.
Figure 4.Recommended Ground Plane
Each reference pin (14 and 15) should be bypassed with a 0.1 µF
ceramic chip capacitor in parallel with a 4.7 µF tantalum capaci-
tor. The 0.1 µF chip cap should be placed as close to the pack-
age pin as possible, and the trace to it from the reference pin
should be as short and as wide as possible. Keep this trace away
from any analog traces (Pins 10, 11, 12, 17, 18, 19)! Coupling
between input and reference traces will cause even order har-
monic distortion. If the reference is needed somewhere else on
the printed circuit board, it should be shielded from any signal
dependent traces to prevent distortion.
Wherever possible, minimize the capacitive load on the digital
outputs of the part. This will reduce the digital spike currents
drawn from the digital supply pins and help keep the IC sub-
strate quiet.
How to Extend SNRA cost-effective method of improving the dynamic range and
SNR of an analog-to-digital conversion system is to use multiple
AD1877 channels in parallel with a common analog input. This
technique makes use of the fact that the noise in independent
modulator channels is uncorrelated. Thus every doubling of the
number of AD1877 channels used will improve system dynamic
range by 3 dB. The digital outputs from the corresponding deci-
mator channels have to be arithmetically averaged to obtain the
improved results in the correct data format. A microprocessor,
either general-purpose or DSP, can easily perform the averaging
operation.
Shown below in Figure 5 is a circuit for obtaining a 3 dB
improvement in dynamic range by using both channels of a
single AD1877 with a mono input. A stereo implementation
would require using two AD1877s and using the recommended
input structure shown in Figure 2. Note that a single microproces-
sor would likely be able to handle the averaging requirements
for both left and right channels.
Figure 5.Increasing Dynamic Range By Using Two
AD1877 Channels
DIGITAL INTERFACE
Modes of OperationThe AD1877’s flexible serial output port produces data in
two’s-complement, MSB-first format. The input and output sig-
nals are TTL logic level compatible. Time multiplexed serial
data is output on SOUT (Pin 26), left channel then right chan-
nel, as determined by the left/right clock signal LRCK (Pin 1).
Note that there is no method for forcing the right channel to
precede the left channel. The port is configured by pin selec-
tions. The AD1877 can operate in either master or slave mode,
with the data in right-justified, I2S-compatible, Word Clock
controlled or left-justified positions.
The various mode options are pin-programmed with the Slave/
Master Pin (7), the Right/Left Justify Pin (21), and the MSB
Delay Pin (22). The function of these pins is summarized as
follows:
