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AD1876JN
16-Bit 100 kSPS Sampling ADC
FUNCTIONAL BLOCK DIAGRAMREV.A
16-Bit 100 kSPS
Sampling ADC
FEATURES
Autocalibrating
0.002% THD
90 dB S/(N+D)
1 MHz Full Power Bandwidth
On-Chip Sample & Hold Function
23 Oversampling for Audio Applications
16-Pin DIP Package
Serial Twos Complement Output Format
Low Input Capacitance–typ 50 pF
AGND Sense for Improved Noise Immunity
PRODUCT DESCRIPTIONThe AD1876 is a 16-bit serial output sampling A/D converter
which uses a switched capacitor/charge redistribution architecture
to achieve a 100kSPS conversion rate (10 μs total conversion
time). Overall performance is optimized by digitally correcting
internal nonlinearities through on-chip autocalibration.
The circuitry of the AD1876 is partitioned onto two monolithic
chips, a digital control chip fabricated with Analog Devices’
DSP CMOS process and an analog ADC chip fabricated with
the BiMOS II process. Both chips are contained in a single
package.
The serial output interface requires an external clock and
sample command signal. The output data rate may be as high
as 2.08 MHz, and is controlled by the external clock. The twos
complement format of the output data is MSB first and is di-
rectly compatible with the NPC SM5805 digital decimation fil-
ter used in consumer audio products. The AD1876 is also
compatible with a variety of DSP processors.
The AD1876 is packaged in a space saving 16-pin plastic DIP
and operates from +5 V and ±12 V supplies; typical power con-
sumption is 235 mW. The digital supply (VDD) is isolated from
the linear supplies (VEE and VCC) for reduced digital crosstalk.
Separate analog and digital grounds are also provided.
AD1876–SPECIFICATIONSTOTAL HARMONIC DISTORTION (THD)
ANALOG INPUT
POWER SUPPLIES
NOTESVREF = 5.00 V; conversion rate = 96 kSPS; fIN = 1.06 kHz; VIN = –0.05 dB unless otherwise noted. All measurements referred to a 0 dB (10 V p-p) input signal.
Values are post calibration.Includes first 19 harmonics.Minimum value of S/(N+D) corresponds to 5.0 V reference; typical values of S/(N+D) correspond to 10.0 V reference.fa = 1008 Hz; fb = 1055 Hz. See Definition of Specifications section and Figure 14.See Applications section for recommended voltage reference circuit and Figure 11 for performance with other reference voltage values.See Applications section for recommended input buffer circuit.
*For explanation of input characteristics, see “Analog Input” section.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all devices at final electrical test at worst case temperature. Results from those tests are used to calculate outgoing
quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested.
(TMIN to TMAX, VCC = +12 V 6 5%, VEE = –12 V 6 5%, VDD = +5 V 6 10%)1
ORDERING GUIDE
TIMING SPECIFICATIONS1
DIGITAL SPECIFICATIONSSpecifications subject to change without notice.
Specifications shown in boldface are tested on all devices at final electrical test at worst case temperature. Results from those tests are used to calculate outgoing qual-
ity levels. All min and max specifications are guaranteed, although only those shown in boldface are tested.
AD1876
ABSOLUTE MAXIMUM RATINGS*VCC to VEE . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +26.4 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VCC to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +18 V
VEE to AGND . . . . . . . . . . . . . . . . . . . . . . . . –18 V to +0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3 V
Digital Inputs to DGND . . . . . . . . . . . . . . . . . . . 0 V to 5.5 V
Analog Inputs, VREF to AGND . . . . . . . . . . . (VCC + 0.3 V) to
(VEE – 0.3 V)
(TMIN to TMAX, VCC = +12 V 6 5%, VEE = –12 V 6 5%, VDD = +5 V 6 10%, VREF = 5.00 V)Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C, 10 sec
Storage Temperature . . . . . . . . . . . . . . . . . . –60°C to +100°C
*Stresses greater than those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational section of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect device
reliability.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1876 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
(TMIN to TMAX, VCC = +12 V 6 5%, VEE = –12 V 6 5%, VDD = +5 V 6 10%)
AD1876
CLK
BUSY
CAL
tCALBtCLtCB
tCTFigure 1.AD1876 Calibration Timing
DOUT CLK
CLK
SAMPLE
BUSY
tS (=1/fs)
tDCL
tCD
tCBtA
DOUTFigure 2.Recommended AD1876 Conversion Timing
Definition of Specifications
NYQUIST FREQUENCYAn implication of the Nyquist sampling theorem, the “Nyquist
Frequency” of a converter is that input frequency which is one-
half the sampling frequency of the converter.
TOTAL HARMONIC DISTORTIONTotal harmonic distortion (THD) is measured as the ratio of the
rms sum of the first nineteen harmonic components to the rms
value of a 1 kHz full-scale sine wave input signal and is ex-
pressed in percent (%) or decibels (dB). For input signals or
harmonics that are above the Nyquist frequency, the aliased
component is used.
SIGNAL-TO-NOISE PLUS DISTORTION RATIOSignal-to-noise plus distortion (S/N+D) is defined to be the ra-
tio of the rms value of the measured input signal to the rms sum
of all other spectral components below the Nyquist frequency,
including harmonics but excluding dc.
D-RANGE DISTORTIOND-range distortion is the ratio of the distortion plus noise to the
signal at a signal amplitude of –60 dB. In this case, an A-weight
filter is used. The value specified for D-range performance is the
ratio measured plus 60 dB.
BANDWIDTHThe full power bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by 3 dB
for a full-scale input.
INTERMODULATION DISTORTION (IMD)With inputs consisting of sine waves at two frequencies, fa and
fb, any device with nonlinearities will create distortion products,
of order (m+n), at sum and difference frequencies of mfa ± nfb,
where m, n = 0, l, 2, 3.... Intermodulation terms are those for
which m or n is not equal to zero. For example, the second or-
der terms are (fa + fb) and (fa – fb), and the third order terms are
(2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb). The IMD products
are expressed as the decibel ratio of the rms sum of the mea-
sured input signals to the rms sum of the distortion terms. The
two signals applied to the converter are of equal amplitude, and
the peak value of their sum is –0.05 dB from full scale. The
IMD products are normalized to a 0 dB input signal.
APERTURE DELAYAperture delay is the time required after SAMPLE is taken
LOW for the internal sample-hold of the AD1876 to open, thus
holding the value of VIN.
PIN DESCRIPTIONType:AI = Analog Input.
DI = Digital Input.
DO = Digital Output.
P = Power.
NC = NO CONNECT
SAMPLE
VDD
DOUTCLK
BUSY
CAL
CLK
DOUT
DGND
VIN
VREF
VEEVCC
AGNDAGND SENSEPackage Pinout
AD1876held HIGH, DOUT will be forced LOW. In either case, DOUT
CLK will continue pulsing. Since the SAMPLE pin has no con-
trol over the actual calibration process, normal conversion tim-
ing may also be used for calibration. In this case, however, the
DOUT pin will output test information during those periods that
SAMPLE is LOW. BUSY going LOW will always indicate the
end of calibration.
A calibration sequence should be followed by one “dummy”
conversion to clear the internal circuitry of the AD1876 in order
to guarantee subsequent conversion accuracy.
In most applications, it is sufficient to calibrate the AD1876
only upon power-up, in which case care should be taken that the
power supplies and voltage reference have stabilized first.
CONVERSION CONTROLThe AD1876 is controlled by two signals: SAMPLE and CLK,
as shown in Figure 2. It is assumed that the part has been cali-
brated and the digital I/O pins have the levels shown at the start
of the timing diagram.
A conversion consists of an input acquisition followed by 17
clock pulses which are required to run the 16-bit internal suc-
cessive approximation routine. The analog input is acquired by
taking the SAMPLE line HIGH for a minimum acquisition time
of tA. The actual sample taken is the voltage present on VIN at
the instant the SAMPLE pin is brought LOW. Care should be
taken to ensure that this negative edge is well defined and jitter
free to reduce the uncertainty (noise) in ac signal acquisition.
On that edge the AD1876 commits itself to the initiated conver-
sion—the input at VIN is disconnected from the internal capaci-
tor array and the SAMPLE input will be ignored until the
conversion is completed (i.e., BUSY goes LOW). After a delay
of at least tSC (SAMPLE to CLK setup) the 17 CLK cycles are
applied. BUSY is asserted after the first positive edge on CLK
and reset after the 17th. Both the DOUT and the DOUT CLK out-
puts are generated in response to the rising edges of valid CLK
pulses. As indicated in the timing diagram, the 2s complement
output data is presented MSB first. This data may be captured
with the rising edge of DOUT CLK or the falling edge of CLK
provided tCH ≥ tCDH. The AD1876 will ignore CLK after BUSY
has gone LOW and not change DOUT or DOUT CLK until a new
sample is acquired. SAMPLE will no longer be ignored after
BUSY goes LOW, and so an acquisition may be initiated even
during the HIGH time of the 17th CLK pulse for maximum
throughput rate while enabling full settling of the sample/hold
circuitry. Note that if SAMPLE is already HIGH when BUSY
goes LOW, then an acquisition is immediately initiated and tA
starts from that time.
During signal acquisition and conversion, care should be taken
with the logic inputs to avoid digital feedthrough noise. It is not
recommended that CLK be running during VIN sampling. If a
continuous CLK is used, then the user must avoid CLK edges
at the instant of disconnecting VIN, i.e., the falling edge of
SAMPLE (see the tSC specifications). The LOW level time of
CLK (tCL) should be at least 100 ns to avoid the negative edge
transition disturbing the internal comparator’s settling (whose
decision is latched on the positive edge of each valid CLK). For
FUNCTIONAL DESCRIPTIONThe AD1876 is a 16-bit analog-to-digital converter including a
sample/hold input circuit, successive approximation register,
ground sensing circuitry, serial output port and a micro-
controller based autocalibration circuit. These functions are seg-
mented onto two monolithic chips, an analog signal processor
and a digital controller. Both chips are contained within the
AD1876 package.
The AD1876 employs a successive-approximation technique to
determine the value of the analog input voltage. However, in-
stead of the traditional laser-trimmed resistor-ladder approach,
the AD1876 uses a capacitor-array, charge-redistribution tech-
nique. An array of binary-weighted capacitors subdivides the
input value to perform the actual analog to digital conversion.
This capacitor array also serves a sample/hold function without
the need for additional external circuitry.
The autocalibration circuit within the AD1876 employs a
microcontroller and calibration DAC to measure and compen-
sate capacitor mismatch errors. As each error is determined, its
value is stored in on-chip memory (RAM). Subsequent conver-
sions use these RAM values to improve conversion accuracy.
The autocalibration routine may be invoked at any time. Auto-
calibration insures high performance while eliminating the need
for any user adjustments, and is described in detail below.
The microcontroller controls all of the various functions within
the AD1876. These include the actual successive approximation
routine, the autocalibration routine, the sample/hold operation,
and the serial data transmission.
AUTOCALIBRATIONThe AD1876 achieves rated performance without the need for
user trims or adjustments. This is accomplished through the use
of on-chip autocalibration.
In the autocalibration sequence, sample/hold offset is nulled by
internally connecting the input circuit to the ground sense cir-
cuit. The resulting offset voltage is measured and stored in
RAM for later use. Next, the capacitor representing the most
significant bit (MSB) is charged to the reference voltage. This
charge is then inverted and shared between the MSB capacitor
and one of equal size composed of all the least significant bits.
The difference in the summation of the charges in each of the
equally sized capacitors represents the amount of capacitor mis-
match. A calibration D/A converter (DAC) adds an appropriate
value of error correction voltage to cancel the mismatch. This
correction factor is also stored in RAM. This process is repeated
for each of the capacitors representing the remaining bits. The
accumulated values in RAM are then used during subsequent
conversions to adjust conversion results.
As shown in Figure 1, when CAL is taken HIGH the AD1876
internal circuitry is reset, the BUSY pin is driven HIGH and the
part prepares for calibration. This is a ‘hard’ reset and will inter-
rupt any conversion or calibration currently in progress. In order
to guarantee that all internal undefined states are cleared, the
CAL pin should he held HIGH for at least 4 CLK cycles. Ac-
tual calibration begins when the CAL pin is taken LOW and
completes in less than 5000 clock cycles or about 2.5 msec with
