AD1870AR-REEL ,Single-Supply 16-Bit Sigma Delta Stereo ADCcharacteristics. The AD1870’s proprietary fourth orderand a narrow transition band that properly di ..
AD1871YRS ,Stereo Audio, 24-bit, 96kHz, Multi-bit Sigma Delta ADCSPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AD1871YRSZ ,Stereo Audio, 24-bit, 96kHz, Multi-bit Sigma Delta ADCfeatures anMixing ConsolesSPI compatible serial control port that allows for convenientMusical Inst ..
AD1876JN ,16-Bit 100 kSPS Sampling ADCApplicationsBUFFERS11V16-Pin DIP PackageREFCAL8AGNDSerial Twos Complement Output FormatDACLow Input ..
AD1877JR ,Single-Supply 16-Bit Stereo ADCFEATURES FUNCTIONAL BLOCK DIAGRAMSingle 5 V Power SupplySingle-Ended Dual-Channel Analog InputsCLOC ..
AD1878JD ,High Performance 16-/18-Bit Stereo ADCsSpecifications subject to change without notice.–2– REV. 0AD1878/AD1879DIGITAL INPUTSMin Max UnitsV ..
AD8325ARU ,5 V CATV Line Driver Fine Step Output Power Controlapplications such as cablemodems that are designed to the MCNS-DOCSIS upstream –50V = 62dBmVOUTstan ..
AD8325ARU-REEL ,5 V CATV Line Driver Fine Step Output Power Controlapplications such as cablemodems that are designed to the MCNS-DOCSIS upstream –50V = 62dBmVOUTstan ..
AD8326ARE ,High Output Power Programmable CATV Line Driverapplicationssuch as data and telephony cable modems that are designed to–70the MCNS-DOCSIS upstream ..
AD8328ARQ ,5 V Upstream Cable Line DriverCHARACTERISTICSBandwidth (–3 dB) All Gain Codes (1–60 Decimal Codes) 107 MHzBandwidth Roll-Off f = ..
AD8328ARQ-REEL ,5 V Upstream Cable Line Driverspecifications. Typical insertion loss of 0.3 dB @ 10 MHz.2Guaranteed by design and characterizatio ..
AD8328ARQ-REEL ,5 V Upstream Cable Line Driverspecifications make the AD8328 –54@MAX GAIN,ideally suited for MCNS-DOCSIS and Euro-DOCSIS applica- ..
AD1870AR-AD1870AR-REEL
Single-Supply 16-Bit Sigma Delta Stereo ADC
FUNCTIONAL BLOCK DIAGRAMREV.A
Single-Supply
16-Bit �-� Stereo ADC
FEATURES
Single 5 V Power Supply
Single-Ended Dual-Channel Analog Inputs
92 dB (Typ) Dynamic Range
90 dB (Typ) S/(THD + N)
0.006 dB Decimator Pass-Band Ripple
Fourth Order, 64� Oversampling �-� Modulator
Three-Stage, Linear-Phase Decimator
256 � fS or 384 � fS Input Clock
Less than 100 �W (Typ) Power-Down Mode
Input Overrange Indication
On-Chip Voltage Reference
Flexible Serial Output Interface
28-Lead SOIC Package
APPLICATIONS
Consumer Digital Audio Receivers
Digital Audio Recorders, Including Portables
CD-R, DCC, MD, and DAT
Multimedia and Consumer Electronics Equipment
Sampling Music Synthesizersshapes the one-bit comparator’s quantization noise out of the
audio pass band. The high order of the modulator randomizes the
modulator output, reducing idle tones in the AD1870 to very
low levels. Because its modulator is single bit, the AD1870 is
inherently monotonic and has no mechanism for producing
differential linearity errors.
The input section of the AD1870 uses autocalibration to correct
any dc offset voltage present in the circuit, provided that the inputs
are ac-coupled. The single-ended dc input voltage can swing
between 0.7 V and 3.8 V typically. The AD1870 antialias input
circuit requires four external 470 pF NPO ceramic chip filter
capacitors, two for each channel. No active electronics are needed.
Decoupling capacitors for the supply and reference pins are
also required.
The dual-digital decimation filters are triple-stage, finite impulse
response filters for effectively removing the modulator’s high
frequency quantization noise and reducing the 64 × fS single-bit
output data rate to an fS word rate. They provide linear phase
and a narrow transition band that properly digitizes 20 kHz signals
at a 44.1 kHz sampling frequency. Pass-band ripple is less than
0.006 dB, and stop-band attenuation exceeds 90 dB.
(Continued on Page 7)
PRODUCT OVERVIEWThe AD1870 is a stereo, 16-bit oversampling ADC based on
sigma-delta (�-�) technology intended primarily for digital
audio bandwidth applications requiring a single 5 V power supply.
Each single-ended channel consists of a fourth order one-bit
noise shaping modulator and a digital decimation filter. An on-chip
voltage reference, stable over temperature and time, defines the
full-scale range for both channels. Digital output data from both
channels are time multiplexed to a single, flexible serial inter-
face. The AD1870 accepts a 256 × fS or a 384 × fS input clock
(fS is the sampling frequency) and operates in both serial port
Master and Slave Modes. In Slave Mode, all clocks must be ex-
ternally derived from a common source.
Input signals are sampled at 64 × fS onto internally buffered
switched capacitors, eliminating external sample-and-hold ampli-
fiers and minimizing the requirements for antialias filtering at the
input. With simplified antialiasing, linear phase can be preserved
across the pass band. The on-chip single-ended-to-differential sig-
nal converters save the board designer from having to provide
them externally. The AD1870’s internal differential architecture
provides increased dynamic range and excellent power supply
rejection characteristics. The AD1870’s proprietary fourth order
differential switched-capacitor �-� modulator architecture
*. Patent Numbers 5055843, 5126653; others pending.
AD1870–SPECIFICATIONS
TEST CONDITIONS UNLESS OTHERWISE NOTEDSupply Voltages5.0V
Ambient Temperature25°C
Input Clock (fCLKIN) [256 × fS]12.288MHz
Input Signal991.768Hz
–0.5dB Full Scale
Measurement Bandwidth23.2 Hz to 19.998 kHz
Load Capacitance on Digital Outputs50pF
Input Voltage HI (VIH)2.4V
Input Voltage LO (VIL)0.8V
Master Mode, Data I2S-Justified (Refer to Figure 14).
Device Under Test (DUT) bypassed and decoupled as shown in Figure 3.
DUT is antialiased and ac-coupled as shown in Figure 2. DUT is calibrated.
Values in bold typeface are tested; all others are guaranteed but not tested.
ANALOG PERFORMANCESignal to (THD + Noise)
Signal to THD
Analog Inputs
VREF
DC Accuracy
DIGITAL I/OInput Leakage (IIL @ VIL = 0 V)
DIGITAL TIMING (Guaranteed over –40°C to +85°C, DVDD = AVDD = 5 V ± 5%. Refer to Figures 17–19.)fCLKIN
tCPWH
tRPWL
tBPWL
tBPWH
tDLYCKB
tDLYBWR
tDLYLRDT
tSETWBS
tDLYBDT
POWERSupplies
Dissipation
AD1870
TEMPERATURE RANGE
DIGITAL FILTER CHARACTERISTICS*Stop band repeats itself at multiples of 64 × fS, where fS is the output word rate. Thus the digital filter will attenuate to 0 dB across the frequency spectrum except
for a range ±0.55 × fS wide at multiples of 64 × fS.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD1870 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
AD1870
PIN FUNCTION DESCRIPTIONS
DEFINITIONS
Dynamic RangeThe ratio of a full-scale output signal to the integrated output noise
in the pass band (20 Hz to 20 kHz), expressed in decibels (dB).
Dynamic range is measured with a –60 dB input signal and is equal
to (S/(THD + N)) 60 dB. Note that spurious harmonics are below
the noise with a –60 dB input, so the noise level establishes the
dynamic range. The dynamic range is specified with and with-
out an A-Weight filter applied.
Signal to Total Harmonic Distortion + Noise
(S/(THD + N))The ratio of the root-mean-square (rms) value of the fundamen-
tal input signal to the rms sum of all other spectral components
in the pass band, expressed in decibels.
Signal to Total Harmonic Distortion (S/THD)The ratio of the rms value of the fundamental input signal to the
rms sum of all harmonically related spectral components in the
pass band, expressed in decibels.
Pass BandThe region of the frequency spectrum unaffected by the attenu-
ation of the digital decimator’s filter.
Pass-Band RippleThe peak-to-peak variation in amplitude response from equal-
amplitude input signal frequencies within the pass band,
expressed in decibels.
Stop BandThe region of the frequency spectrum attenuated by the digi-
tal decimator’s filter to the degree specified by stop-band
attenuation.
Gain ErrorWith a near full-scale input, the ratio of actual output to
expected output, expressed as a percentage.
Interchannel Gain MismatchWith identical near full-scale inputs, the ratio of outputs of the
two stereo channels, expressed in decibels.
Gain DriftChange in response to a near full-scale input with a change in
temperature, expressed as parts-per-million (ppm) per °C.
Midscale Offset ErrorOutput response to a midscale dc input, expressed in least
significant bits (LSBs).
Midscale DriftChange in midscale offset error with a change in temperature,
expressed as parts-per-million (ppm) per °C.
Crosstalk (EIAJ Method)Ratio of response on one channel with a grounded input to a
full-scale 1 kHz sine wave input on the other channel, expressed
in decibels.
Power Supply RejectionWith no analog input, signal present at the output when a
300 mV p-p signal is applied to the power supply pins, ex-
pressed in decibels of full scale.
Group DelayIntuitively, the time interval required for an input pulse to
appear at the converter’s output, expressed in milliseconds
(ms). More precisely, the derivative of radian phase with respect
to radian frequency at a given frequency.
Group Delay VariationThe difference in group delays at different input frequencies.
Specified as the difference between the largest and smallest
group delays in the pass band, expressed in microseconds (µs).
AD1870 TPC 1.1 kHz Tone at –0.5 dBFS (16 k-Point FFT)
TPC 2.1 kHz Tone at –10 dBFS (16 k-Point FFT)
TPC 3.THD + N vs. Frequency at –0.5 dBFS
TPC 4.THD + N vs. Input Amplitude at 1 kHz
TPC 5.Power Supply Rejection to 300 mV p-p on AVDD
TPC 6.Channel Separation vs. Frequency at –0.5 dBFS
–Typical Performance Characteristics
(Continued from Page 1 )
The flexible serial output port produces data in two’s complement,
MSB-first format. The input and output signals are TTL
compatible. The port is configured by pin selections. Each 16-bit
output word of a stereo pair can be formatted within a 32-bit
field of a 64-bit frame as either right-justified, I2S compatible,
word clock controlled, or left-justified positions. Both 16-bit
samples can also be packed into a 32-bit frame, in left-justified
and I2S compatible positions.
The AD1870 is fabricated on a single monolithic integrated circuit
using a 0.5 µm CMOS double polysilicon, double metal process
and is offered in a plastic 28-lead SOIC package. Analog and
digital supply connections are separated to isolate the analog
circuitry from the digital supply and reduce digital crosstalk.
The AD1870 operates from a single 5 V power supply over the
temperature range of –40°C to +85°C and typically consumes
less than 260 mW of power.
THEORY OF OPERATION�-� Modulator Noise Shaping
The stereo, internally differential, analog modulator of the
AD1870 employs a proprietary feedforward and feedback archi-
tecture that passes input signals in the audio band with a unity
transfer function yet simultaneously shapes the quantization
noise generated by the one-bit comparator out of the audio
band (see Figure 1). Without the �-� architecture, this quanti-
zation noise would be spread uniformly from dc to one-half
the oversampling frequency, 64 × fS.
�-� architectures “shape” the quantization noise-transfer function
in a nonuniform manner. Through careful design, this transfer
function can be specified to high-pass filter the quantization
noise out of the audio band into higher frequency regions. The
AD1870 also incorporates a feedback resonator from the fourth
integrator’s output to the third integrator’s input. This resona-
tor does not affect the signal transfer function but allows the
flexible placement of a zero in the noise transfer function for
more effective noise shaping.
Oversampling by 64 simplifies the implementation of a high
performance audio analog-to-digital conversion system. Antialias
requirements are minimal; a single pole of filtering will usually
suffice to eliminate inputs near fS and its higher multiples.
A fourth order architecture was chosen both to strongly shape
the noise out of the audio band and to help break up the idle
tones produced in all �-� architectures. These architectures
have a tendency to generate periodic patterns with a constant dc
input, a response that looks like a tone in the frequency domain.
These idle tones have a direct frequency dependence on the input
dc offset and an indirect dependence on temperature and time
as it affects the dc offset. The AD1870 suppresses idle tones 20
dB or better below the integrated noise floor.
The AD1870’s modulator was designed, simulated, and ex-
haustively tested to remain stable for any input within a wide
tolerance of its rated input range. The AD1870 is designed to
internally reset itself should it ever be overdriven, to prevent it
from going unstable. It will reset itself within 5 µs at a 48 kHz
sampling frequency after being overdriven. Overdriving the inputs
will produce a waveform “clipped” to plus or minus full scale.
See TPCs 1 through 6 for illustrations of the AD1870’s typical
analog performance as measured by an Audio Precision System
One. Signal-to-(distortion + noise) is shown under a range of
conditions. Note that there is a small variance between the
AD1870 analog performance specifications and some of the
performance plots. This is because the Audio Precision System
One measures THD and noise over a 20 Hz to 24 kHz band-
width, while the analog performance is specified over a 20 Hz to
20 kHz bandwidth (i.e., the AD1870 performs slightly better
than the plots indicate). The power supply rejection graph (TPC 5)
illustrates the benefits of the AD1870’s internal differential ar-
chitecture. The excellent channel separation shown in TPC 6 is
the result of careful chip design and layout.
Digital Filter CharacteristicsThe digital decimator accepts the modulator’s stereo bit stream
and simultaneously performs two operations on it. First, the
decimator low-pass filters the quantization noise that the modu-
lator shaped to high frequencies and filters any other out-of-
audio-band input signals. Second, it reduces the data rate to an
output word rate equal to fS. The high frequency bit stream is
decimated to stereo 16-bit words at 48 kHz (or other desired
fS). The out-of-band one-bit quantization noise and other high
frequency components of the bit stream are attenuated by at
least 90 dB.
The AD1870 decimator implements a symmetric finite impulse
response (FIR) filter that possesses a linear phase response.
This filter achieves a narrow transition band (0.1 × fS), high
TPC 7.Digital Filter Signal Transfer Function to fS
AD187044.1 kHz. The stop-band attenuation is sufficient to eliminate
modulator quantization noise from affecting the output. Low
pass-band ripple prevents the digital filter from coloring the
audio signal. See TPC 7 for the digital filter’s characteristics.
The output from the decimator is available as a single serial
output, multiplexed between left and right channels.
Note that the digital filter itself is operating at 64 × fS. As a
consequence, Nyquist images of the pass-band, transition band,
and stop band will be repeated in the frequency spectrum at
multiples of 64 × fS. Thus the digital filter will attenuate to
greater than 90 dB across the frequency spectrum, except for a
window ±0.55 × fS wide centered at multiples of 64 × fS. Any in-
put signals, clock noise, or digital noise in these frequency
windows will not be attenuated to the full 90 dB. If the high
frequency signals or noise appear within the pass-band images
within these windows, they will not be attenuated at all, and
input antialias filtering should therefore be applied.
Sample DelayThe sample delay or “group delay” of the AD1870 is dominated
by the processing time of the digital decimation filter. FIR filters
convolve a vector representing time samples of the input with
an equal-sized vector of coefficients. After each convolution, the
input vector is updated by adding a new sample at one end of
the “pipeline” and discarding the oldest input sample at the
other. For a FIR filter, the time at which a step input appears at
the output will be when that step input is halfway through
the input sample vector pipeline. The input sample vector
is updated every 64 × fS. The equation that expresses the
group delay for the AD1870 is:
Group Delay (sec) = 36/fS (Hz)
For the most common sample rates, this can be summarized as:
Due to the linear phase properties of FIR filters, the group
delay variation, or differences in group delay at different
frequencies, is essentially zero.
OPERATING FEATURES
Voltage Reference and External Filter CapacitorsThe AD1870 includes a 2.25 V on-board reference that deter-
mines the AD1870’s input range. The left and right reference
pins (Pin 14 and Pin 15) should be bypassed with a 0.1 µF
ceramic chip capacitor in parallel with a 4.7 µF tantalum as
shown in Figure 3. Note that the chip capacitor should be clos-
est to the pin. The internal reference can be overpowered by
applying an external reference voltage at the VREFL (Pin 14) and
VREFR (Pin 15) pins, allowing multiple AD1870s to be calibrated
to the same gain. It is not possible to overpower the left and
right reference pins individually; the external reference voltage
should be applied to both Pin 14 and Pin 15. Note that the ref-
erence pins must still be bypassed as shown in Figure 3.
While it is possible to bypass each reference pin (VREFL and
The AD1870 requires four external filter capacitors on Pins 11,
12, 17, and 18. These capacitors are used to filter the single-to-
differential converter outputs and are too large for practical
integration onto the die. They should be 470 pF NPO ceramic
chip type capacitors, as shown in Figure 3, placed as close to
the AD1870 package as possible.
Sample ClockAn external master clock supplied to CLKIN (Pin 28) drives
the AD1870 modulator, decimator, and digital interface. As
with any analog-to-digital conversion system, the sampling clock
must be low jitter to prevent conversion errors. If a crystal oscil-
lator is used as the clock source, it should be bypassed with a
0.1 µF capacitor, as shown below in Figure 3.
For the AD1870, the input clock operates at either 256 × fS or
384 × fS as selected by the 384/256 pin. When 384/256 is HI,
the 384 Mode is selected; when 384/256 is LO, the 256
Mode is selected. In both cases, the clock is divided down to
obtain the 64 × fS clock required for the modulator. The output
word rate itself will be at fS. This relationship is illustrated for
popular sample rates below:
The AD1870 serial interface will support both Master and Slave
Modes. Note that in Slave Mode it is required that the serial
interface clocks be externally derived from a common source.
In Master Mode, the serial interface clock outputs are internally
derived from CLKIN.
Reset, Autocalibration, and Power-DownThe active LO RESET pin (Pin 23) initializes the digital deci-
mation filter and clears the output data buffer. While in the reset
state, all digital pins defined as outputs of the AD1870 are
driven to ground (except for BCLK, which is driven to the state
defined by RDEDGE (Pin 6)). Analog Devices recommends
resetting the AD1870 on initial power-up so that the device is
properly calibrated. The reset signal must remain LO for the
minimum period specified in the Specifications section. The reset
pulse is asynchronous with respect to the master clock, CLKIN.
If, however, multiple AD1870s are used in a system, and it is
desired that they leave the reset state at the same time, the
common reset pulse should be made synchronous to CLKIN
(i.e., RESET should be brought HI on a CLKIN falling edge).
Multiple AD1870s can be synchronized to each other by using
a single master clock and a single reset signal to initialize all
devices. On coming out of reset, all AD1870s will begin sam-
pling at the same time. Note that in Slave Mode, the AD1870
is inactive (and all outputs are static, including WCLK) until
the first rising edge of LRCK after the first falling edge of
LRCK. This initial low going then high going edge of LRCK can
be used to “skew” the sampling start-up time of one AD1870
relative to other AD1870s in a system. In the data position con-
trolled by the WCLK Input Mode, WCLK must be HI with
The AD1870 achieves its specified performance without the
need for user trims or adjustments. This is accomplished through
the use of on-chip automatic offset calibration that takes place
immediately following reset. This procedure nulls out any off-
sets in the single-to-differential converter, the analog modulator,
and the decimation filter. Autocalibration completes in approxi-
mately 8192 × (1/(FLRCK) seconds and need only be performed
once at power-up in most applications. (In Slave Mode, the 8192
cycles required for autocalibration do not start until after the
first rising edge of LRCK following the first falling edge of
LRCK.) The autocalibration scheme assumes that the inputs
are ac-coupled. DC-coupled inputs will work with the AD1870,
but the autocalibration algorithm will yield an incorrect offset
compensation.
The AD1870 also features a Power-Down Mode. It is enabled
by the active LO RESET Pin 23 (i.e., the AD1870 is in Power-
Down Mode while RESET is held LO). The power savings are
specified in the Specifications section. The converter is shut
down in the power-down state and will not perform conversions.
The AD1870 will be reset upon leaving the power-down state, and
autocalibration will commence after the RESET pin goes HI.
Power consumption can be further reduced by slowing down the
master clock input (at the expense of input pass band width).
Note that a minimum clock frequency, fCLKIN, is specified for
the AD1870.
TAG Overrange OutputThe AD1870 includes a TAG serial output (Pin 27) that is pro-
vided to indicate status on the level of the input voltage. The
TAG output is at TTL compatible logic levels. A pair of unsigned
binary bits are output, synchronous with LRCK (MSB then
LSB), that indicate whether the current signal being converted
is: more than 1 dB under full scale, within 1 dB under full scale,
within 1 dB over full scale, or more than 1 dB over full scale.
The timing for the TAG output is shown in Figures 7–16. Note
that the TAG Bits are not “sticky”; i.e., they are not peak read-
ing, but rather change with every sample. Decoding of these two
bits is as follows:
APPLICATION ISSUES
Recommended Input StructureThe AD1870 input structure is single-ended to allow the board
designer to achieve a high level of functional integration. The
very simple recommended input circuit is shown in Figure 2. Note
the 1 µF ac-coupling capacitor, which allows input level shifting
for 5 V only operation and for autocalibration to properly null
offsets. The 3 dB point of the single-pole antialias RC filter is
240 kHz, which results in essentially no attenuation at 20 kHz.
Attenuation at 3 MHz is approximately 22 dB, which is adequate
to suppress fS noise modulation. If the analog inputs are exter-
nally ac-coupled, the 1 µF ac-coupling capacitors shown in
Figure 2 are not required.
Figure 2.Recommended Input Structure for Externally
DC-Coupled Inputs
Analog Input Voltage SwingThe single-ended input range of the analog inputs is specified in
relative terms in the Specifications section. The input level at
which clipping occurs linearly tracks the voltage reference
level; i.e., if the reference is high relative to the typical 2.25
V, the allowable input range without clipping is correspondingly
wider, and if the reference is low relative to the typical 2.25 V,
the allowable input range is correspondingly narrower.
Thus the maximum input voltage swing can be computed using
the following ratio:
AD1870
Layout and Decoupling ConsiderationsObtaining the best possible performance from the AD1870
requires close attention to board layout. Adhering to the follow-
ing principles will produce typical values of 92 dB dynamic range
and 90 dB S/(THD + N) in target systems. Schematics and lay-
out artwork of the AD1870 Evaluation Board, which implement
these recommendations, are available from Analog Devices.
The principles and their rationales are listed below. The first
two pertain to bypassing and are illustrated in Figure 3.
Figure 3.Recommended Bypassing and Oscillator Circuits
There are two pairs of digital supply pins on opposite sides of
the part (Pins 4 and 5 and Pins 24 and 25). The user should tie
a bypass chip capacitor (10 nF ceramic) in parallel with a decou-
pling capacitor (1 µF tantalum) on each pair of supply pins as
close to the pins as possible. The traces between these package
pins and the capacitors should be as short and as wide as pos-
sible. This will prevent digital supply current transients from
being inductively transmitted to the inputs of the part.
Use a 0.1 µF chip analog capacitor in parallel with a 1.0 µF
tantalum capacitor from the analog supply (Pin 9) to the analog
ground plane. The trace between this package pin and the
capacitor should be as short and as wide as possible.
The AD1870 should be placed on a split ground plane. The
digital ground plane should be placed under the top end of the
package, and the analog ground plane should be placed under
the bottom end of the package as shown in Figure 4. The split
should be between Pins 8 and 9 and between Pins 20 and 21.
The ground planes should be tied together at one spot under-
neath the center of the package with an approximately 3 mm
trace. This ground plane technique also minimizes RF transmis-
sion and reception.
Figure 4.Recommended Ground Plane
Each reference pin (Pin 14 and Pin 15) should be bypassed with
a 0.1 µF ceramic chip capacitor in parallel with a 4.7 µF tantalum
capacitor. The 0.1 µF chip cap should be placed as close to the
package pin as possible, and the trace to it from the reference
pin should be as short and as wide as possible. Keep this trace
away from any analog traces (Pins 10, 11, 12, 17, 18, 19). Cou-
pling between input and reference traces will cause even order
harmonic distortion. If the reference is needed somewhere else
on the printed circuit board, it should be shielded from any signal
dependent traces to prevent distortion.
Wherever possible, minimize the capacitive load on the digital
outputs of the part. This will reduce the digital spike currents
drawn from the digital supply pins and help keep the IC sub-
strate quiet.
How to Extend SNRA cost-effective method of improving the dynamic range and
SNR of an analog-to-digital conversion system is to use multiple
AD1870 channels in parallel with a common analog input. This
technique makes use of the fact that the noise in independent
modulator channels is uncorrelated. Thus every doubling of the
number of AD1870 channels used will improve the system dy-
namic range by 3 dB. The digital outputs from the correspond-
ing deci-mator channels must be arithmetically averaged to
obtain the improved results in the correct data format. A micro-
processor, either general purpose or DSP, can easily perform
the averaging operation.
