AD1868N-AD1868N-J-AD1868R-AD1868R-J Fast Delivery |IC PHOENIX CO.,LIMITED

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AD1868N-AD1868N-J-AD1868R-AD1868R-J
Single Supply Dual 18-Bit Audio DAC
FUNCTIONAL BLOCK DIAGRAM
REV.ASingle Supply
Dual 18-Bit Audio DAC
FEATURES
Dual Serial Input, Voltage Output DACs
Single +5 V Supply
0.004% THD+N (typ)
Low Power: 50 mW (typ)
108 dB Channel Separation (min)
Operates at 83 Oversampling
16-Pin Plastic DIP or SOIC Package
APPLICATIONS
Portable Compact Disc Players
Portable DAT Players and Recorders
Automotive Compact Disc Players
Automotive DAT Players
Multimedia Workstations
PRODUCT DESCRIPTION
The AD1868 is a complete dual 18-bit DAC offering excellent
performance while requiring a single +5 V power supply. It is
fabricated on Analog Devices’ ABCMOS wafer fabrication pro-
cess. The monolithic chip includes CMOS logic elements, bipo-
lar and MOS linear elements, and laser-trimmed thin-film
resistor elements. Careful design and layout techniques have re-
sulted in low distortion, low noise, high channel separation, and
low power dissipation.
The DACs on the AD1868 chip employ a partially segmented
architecture. The first three MSBs of each DAC are segmented
into seven elements. The 15 LSBs are produced using standard
R-2R techniques. The segments and R-2R resistors are laser
trimmed to provide extremely low total harmonic distortion.
The AD1868 requires no deglitcher or trimming circuitry. Low
noise is achieved through the use of two noise-reduction capacitors.
Each DAC is equipped with a high performance output ampli-
fier. These amplifiers achieve fast settling and high slew rate,
producing ±1 V signals at load currents up to ±1 mA. The
buffered output signal range is 1.5 V to 3.5 V. Reference volt-
ages of 2.5 V are provided, eliminating the need for “False
Ground” networks.
A versatile digital interface allows the AD1868 to be directly
connected to all digital filter chips. Fast CMOS logic elements
allow for an input clock rate of up to 13.5 MHz. This allows for
operation at 2×, 4×, 8×, or 16× the sampling frequency for each
channel. The digital input pins of the AD1868 are TTL and
+5 V CMOS compatible.
*. Patent Numbers: 3,961,326; 4,141,004; 4,349,811;
4,857,862; and patents pending.
The AD1868 operates on +5 V power supplies. The digital sup-
ply, VL, can be separated from the analog supply, VS, for re-
duced digital feedthrough. Separate analog and digital ground
pins are also provided. In systems employing a single +5 volt
power supply, VL and VS should be connected together. In bat-
tery operated systems, operation will continue even with reduced
supply voltage. Typically, the AD1868 dissipates 50 mW.
The AD1868 is packaged in either a 16-pin plastic DIP or a 16-
pin plastic SOIC package. Operation is guaranteed over the tem-
perature range of –35°C to +85°C and over the voltage supply
range of 4.75 V to 5.25 V.
PRODUCT HIGHLIGHTSSingle-supply operation @ +5 V.50 mW power dissipation (typical).THD+N is 0.004% (typical).Signal-to-Noise Ratio is 97.5 dB (typical).108 dB channel separation (minimum).Compatible with all digital filter chips.16-pin DIP and 16-pin SOIC packages.No deglitcher required.No external adjustments required.
AD1868–SPECIFICATIONS(typical at TA = +258C and +5 V supplies unless otherwise noted)
*Above 115 dB.
Specifications subject to change without notice.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
ABSOLUTE MAXIMUM RATINGS*
VL to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 V to 6 V
VS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 V to 6 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . .±0.3 V
Digital Inputs to DGND . . . . . . . . . . . . . . . . . . . . .–0.3 to VL
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+300°C, 10 sec
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Typical Performance of the AD1868
FREQUENCY – kHz
THD +N – dB
16.518.520.5
Figure 1.THD+N vs. Frequency
VOLTAGE SUPPLY
THD +N – dB
Figure 3.THD+N vs. Supply Voltage
THD +N – dB
TEMPERATURE – °C
Figure 5.THD+N vs. Temperature
Figure 2.Channel Separation vs. Frequency
INPUT AMPLITUDE – dB
GAIN LINEARITY ERROR – dB
–100–80–60–40–10–20
Figure 4.Gain Linearity Error vs. Input Amplitude
SUPPLY MODULATION FREQUENCY – Hz
PSRR – dB
102103104105
Figure 6.Power Supply Rejection Ratio vs. Frequency
AD1868
PIN CONFIGURATION9
DGND
NRL
AGND
NRR
VBR
AD1868
TOP VIEW
(Not To Scale)
VOR
VOL
VBL
DEFINITION OF SPECIFICATIONS
Total Harmonic Distortion + Noise
Total harmonic distortion plus noise (THD+N) is defined as
the ratio of the square root of the sum of the squares of the am-
plitudes of the harmonics and noise to the amplitude of the fun-
damental input frequency. It is usually expressed in percent (%)
or decibels (dB).
D-Range Distortion
D-range distortion is the ratio of the amplitude of the signal at
an amplitude of –60 dB to the amplitude of the distortion plus
noise. In this case, an A-weight filter is used. The value speci-
fied for D-range performance is the ratio measured plus 60 dB.
Signal-to-Noise Ratio
The signal-to-noise ratio is defined as the ratio of the amplitude
of the output when a full-scale output is present to the ampli-
tude of the output with no signal present. It is expressed in
decibels (dB) and measured using an A-weight filter.
Gain Linearity
Gain linearity is a measure of the deviation of the actual output
amplitude from the ideal output amplitude. It is determined by
measuring the amplitude of the output signal as the amplitude
of that output signal is digitally reduced to a lower level. A per-
fect D/A converter exhibits no difference between the ideal and
actual amplitudes. Gain linearity is expressed in decibels (dB).
Midscale Error
Midscale error is the difference between the analog output and
the bias when the twos complement input code representing
midscale is loaded in the input register. Midscale error is ex-
pressed in mV.
ORDERING GUIDE
PIN DESIGNATIONS
FUNCTIONAL DESCRIPTION
The AD1868 is a complete, voltage output dual 18-bit digital
audio DAC which operates with a single +5 volt supply. As
shown in the block diagram, each channel contains a voltage
reference, an 18-bit DAC, an output amplifier, an 18-bit input
latch, and an 18-bit serial-to-parallel input register.
The voltage reference section provides a reference voltage and a
false ground voltage for each channel. The low noise bandgap
circuits produce reference voltages that are unaffected by
changes in temperature, time, and power supply.
The output amplifier uses both MOS and bipolar devices and
incorporates an NPN class-A output stage. It is designed to pro-
duce high slew rate, low noise, low distortion, and optimal fre-
quency response.
Each 18-bit DAC uses a combination of segmented decoder
and R-2R architecture to achieve good integral and differential
linearity. The resistors which form the ladder structure are fab-
ricated with silicon-chromium thin film. Laser trimming of
these resistors further reduces linearity error, resulting in low
output distortion.
The input registers are fabricated with CMOS logic gates.
These gates allow fast switching speeds and low power con-
sumption, contributing to the fast digital timing, low glitch, and
low power dissipation of the AD1868.
DGND
NRL
AGND
NRR
VBR
VBL
VOL
VOR
Functional Block Diagram
ANALOG CIRCUIT CONSIDERATIONS
GROUNDING RECOMMENDATIONS
The AD1868 has two ground pins, designated as AGND (Pin
12) and DGND (Pin 7). The analog ground, AGND, serves as
the “high quality” reference ground for analog signals and as a
return path for the supply current from the analog portion of the
device. The system analog common should be located as close
as possible to Pin 12 to minimize any voltage drop which may
develop between these two points, although the internal circuit
is designed to minimize signal dependence of the analog return
current.
The digital ground, DGND, returns ground current from the
digital logic portion of the device. This pin should be connected
to the digital common node in the system. As shown in Figure
7, the analog and digital grounds should be joined at one point
in the system. When these two grounds are remotely connected
such as at the power supply ground, care should be taken to
minimize the voltage difference between the DGND and AGND
pins in order to ensure the specified performance.
POWER SUPPLIES AND DECOUPLING
The AD1868 has three power supply input pins. VS (Pins 9 and
15) provides the supply voltages which operate the analog por-
tion of the device including the 18-bit DACs, the voltage refer-
ences, and the output amplifiers. The VS supplies are designed
to operate with a +5 V supply. These pins should be decoupled
to analog common using a 0.1 μF capacitor. Good engineering
practice suggests that the bypass capacitors be placed as close as
possible to the package pins. This minimizes the inherent induc-
tive effects of printed circuit board traces.
VL (Pin 1) operates the digital portions of the chip including the
input shift registers and the input latching circuitry. VL is also
designed to operate with a +5 V supply. This pin should be by-
passed to digital common using a 0.1 μF capacitor, again placed
as close as possible to the package pin. Figure 7 illustrates the cor-
rect connection of the digital and analog supply bypass capacitors.
DAC, the AD1868 can continue to function at supply voltages
as low as 3.5 V. Because of its unique design, the power require-
ments of the AD1868 diminish as the battery voltage drops, fur-
ther extending the operating time of the system.
Figure 7.Recommended Circuit Schematic
NOISE REDUCTION CAPACITORS
The AD1868 has two noise reduction pins designated as NRL
(Pin 13) and NRR (Pin 11). It is recommended that external
noise reduction capacitors be connected from these pins to
AGND to reduce the output noise contributed by the voltage
reference circuitry. As shown in Figure 7, each of these pins
should be bypassed to AGND with a 4.7 μF or larger capacitor.
The connections between the capacitors, package pins and
AGND should be as short as possible to achieve the lowest
noise.
USING VBL AND VBR
The AD1868 has two bias voltage reference pins, designated as
VBR (Pin 8) and VBL (Pin 16). These pins supply a dc reference
voltage equal to the center of the output voltage swing. These
bias voltages replace “False Ground” networks previously required
in single-supply audio systems. At the same time, they allow dc-
coupled systems, improving audio performance.
Figure 8a illustrates the traditional approach used to generate
False Ground voltages in single-supply audio systems. This cir-
cuit requires additional power and circuit board space.9
–VS
DGND
CLK
DATA
+VL
+VS
TRIM
MSB
ADJ
IOUT
AGND
VOUTNC
AD1868
VOL
VOR
Figure 8b.Circuitry Using Voltage Biases
The AD1868 eliminates the need for “False Ground” circuitry.
VBR and VBL generate the required bias voltages previously
generated by the “False Ground.” As shown in Figure 8b, VBR
and VBL may be used as the reference point in each output
channel. This permits a dc-coupled output signal path. This
eliminates ac-coupling capacitors and improves low frequency
performance. It should be noted that these bias outputs have
relatively high output impedance and will not drive output
currents larger than 100 μA without degrading the specified
performance.
DISTORTION PERFORMANCE AND TESTING
The THD+N figure of an audio DAC represents the amount of
undesirable signal produced during reconstruction and playback
of an audio waveform. Therefore, the THD+N specification
provides a direct method to classify and choose an audio DAC
for a desired level of performance.
Figure 1 illustrates the typical THD+N versus frequency perfor-
mance of the AD1868. It is evident that the THD+N perfor-
mance of the AD1868 remains stable at all three levels through
a wide range of frequencies. A load impedance of at least 2 kΩ is
recommended for best THD+N performance.
Analog Devices tests and grades all AD1868s on the basis of
THD+N performance. During the distortion test, a high speed
digital pattern generator transmits digital data to each channel
of the device under test. Eighteen-bit data is latched into the
DAC at 352.8 kHz (8× FS). The test waveform is a 990.5 Hz
sine wave with 0 dB, –20 dB, and –60 dB amplitudes. A 4096-
point FFT calculates total harmonic distortion + noise,
signal-to-noise ratio, and D-range. No deglitchers or external
adjustments are used.
DIGITAL CIRCUIT CONSIDERATIONS
INPUT DATA
The AD1868 digital input port employs five signals: Data Left
(DL), Data Right (DR), Latch Left (LL), Latch Right (LR) and
Clock (CLK). DL and DR are the serial inputs for the left and
right DACs, respectively. Input data bits are clocked into the in-
put register on the rising edge of CLK. The falling edges of LL
and LR cause the last 18 bits which were clocked into the serial
registers to be shifted into the DACs, thereby updating the re-
spective DAC outputs. For systems using only a single latch sig-
nal, LL and LR may be connected together. For systems using
only one DATA signal, DR and DL may be connected together.
Data is transmitted to the AD1868 in a bit stream composed of
18-bit words with a serial, twos complement, MSB first format.
Left and right channels share the Clock (CLK) signal.
Figure 9 illustrates the general signal requirements for data
transfer for the AD1868.
CLK
Figure 9.Control Signals

Partno	Mfg	Dc	Qty	Available	Descript
AD1868N	AD	N/a	25	avai	Single Supply Dual 18-Bit Audio DAC
AD1868N-J \|AD1868NJ	AD	N/a	63	avai	Single Supply Dual 18-Bit Audio DAC
AD1868R	AD ?	N/a	10	avai	Single Supply Dual 18-Bit Audio DAC
AD1868R-J \|AD1868RJ	AD	N/a	235	avai	Single Supply Dual 18-Bit Audio DAC