AD1865P ,Complete Dual 18-Bit 16 3 FS Audio DACapplications. S*Protected by U.S. Patents Nos.: RE 30,586; 3,961,326; 4,141,004; 18. Low Power—only ..
AD1865R ,Complete Dual 18-Bit 16 x Fs Audio DACapplications. S*Protected by U.S. Patents Nos.: RE 30,586; 3,961,326; 4,141,004; 18. Low Power—only ..
AD1866N ,Single Supply Dual 16-Bit Audio DACFEATURESDual Serial Input, Voltage Output DACsSingle +5 Volt SupplyAD186616-BIT0.005% THD+NDACV 1 1 ..
AD1866R ,Single Supply Dual 16-Bit Audio DACSpecifications subject to change without notice.
AD1866RZ , Single Supply Dual 16-Bit Audio DAC
AD1868N ,Single Supply Dual 18-Bit Audio DACSpecifications subject to change without notice.*Stresses greater than those listed under “Absolute ..
AD8321AR-REEL ,Gain Programmable CATV Line DriverFEATURES FUNCTIONAL BLOCK DIAGRAMLinear in dB Gain Response Over >53 dB RangeVCC GNDDrives Low Dist ..
AD8322ARU ,5 V CATV Line Driver Coarse Step Output Power ControlFEATURES FUNCTIONAL BLOCK DIAGRAMSupports DOCSIS Standard for Reverse PathV (7 PINS)CCTransmissionG ..
AD8322ARU-REEL ,5 V CATV Line Driver Coarse Step Output Power Controlapplications such as cable@ MAX GAINmodems that are designed to the MCNS-DOCSIS upstream –60standar ..
AD8323 ,5 V CATV Line Driver Fine Stepapplications such as cableP = 60dBmV @ MAX GAINOmodems that are designed to the MCNS-DOCSIS upstrea ..
AD8323ARU ,5 V CATV Line Driver Fine Step Output Power ControlCHARACTERISTICSSpecified AC Voltage Output = 60 dBmV, Max Gain 116 mV p-pNoise Figure Max Gain, f = ..
AD8323ARU ,5 V CATV Line Driver Fine Step Output Power Controlapplications such as cableP = 60dBmV @ MAX GAINOmodems that are designed to the MCNS-DOCSIS upstrea ..
AD1865N-K-AD1865P
Complete Dual 18-Bit 16 3 FS Audio DAC
FUNCTIONAL BLOCK DIAGRAM
(DIP Package)+VS
TRIM
MSB
DGND
AGND
VOUT
IOUT
–VS
IOUT
+VL
VOUT
TRIM
MSB
CLK
AGND
NC = NO CONNECTComplete Dual 18-Bit
16 3 FS Audio DAC
FEATURES
Dual Serial Input, Voltage Output DACs
No External Components Required
110 dB SNR
0.003% THD+N
Operates at 16 3 Oversampling per Channel65 Volt Operation
Cophased Outputs
116 dB Channel Separation
Pin Compatible with AD1864
DIP or SOIC Packaging
APPLICATIONS
Multichannel Audio Applications
Compact Disc Players
Multivoice Keyboard Instruments
DAT Players and Recorders
Digital Mixing Consoles
Multimedia Workstations
PRODUCT DESCRIPTIONThe AD1865 is a complete, dual 18-bit DAC offering excellent
THD+N and SNR while requiring no external components. Two
complete signal channels are included. This results in cophased
voltage or current output signals and eliminates the need for
output demultiplexing circuitry. The monolithic AD1865 chip
includes CMOS logic elements, bipolar and MOS linear ele-
ments and laser-trimmed thin-film resistor elements, all fabri-
cated on Analog Devices’ ABCMOS process.
The DACs on the AD1865 chip employ a partially segmented
architecture. The first four MSBs of each DAC are segmented
into 15 elements. The 14 LSBs are produced using standard R-2R
techniques. Segment and R-2R resistors are laser trimmed to pro-
vide extremely low total harmonic distortion. This architecture
minimizes errors at major code transitions resulting in low out-
put glitch and eliminating the need for an external deglitcher.
When used in the current output mode, the AD1865 provides
two –1 mA output signals.
Each channel is equipped with a high performance output am-
plifier. These amplifiers achieve fast settling and high slew rate,
producing –3 V signals at load currents up to 8 mA. Each out-
put amplifier is short-circuit protected and can withstand indefi-
nite short circuits to ground.
The AD1865 was designed to balance two sets of opposing re-
quirements, channel separation and DAC matching. High chan-
nel separation is the result of careful layout. At the same time,
both channels of the AD1865 have been designed to ensure
matched gain and linearity as well as tracking over time and
temperature. This assures optimum performance when used in
stereo and multi-DAC per channel applications.
*. Patents Nos.: RE 30,586; 3,961,326; 4,141,004;
4,349,811; 4,855,618; 4,857,862.A versatile digital interface allows the AD1865 to be directly
connected to standard digital filter chips. This interface employs
five signals: Data Left (DL), Data Right (DR), Latch Left (LL),
Latch Right (LR) and Clock (CLK). DL and DR are the serial
input pins for the left and right DAC input registers. Input data
bits are clocked into the input register on the rising edge of
CLK. A low-going latch edge updates the respective DAC out-
put. For systems using only a single latch signal, LL and LR
may be connected together. For systems using only one DATA
signal, DR and DL may be connected together.
The AD1865 operates with –5 V power supplies. The digital
supply, VL, can be separated from the analog supplies, VS and
–VS, for reduced digital feedthrough. Separate analog and digital
ground pins are also provided. The AD1865 typically dissipates
only 225 mW, with a maximum power dissipation of 260 mW.
The AD1865 is packaged in both a 24-pin plastic DIP and a
28-pin SOIC package. Operation is guaranteed over the temper-
ature range of –25°C to +70°C and over the voltage supply
range of –4.75 V to –5.25 V.
PRODUCT HIGHLIGHTS11.The AD1865 is a complete dual 18-bit audio DAC.
12.110 dB signal-to-noise ratio for low noise operation.
13.THD+N is typically 0.003%.
14.Interchannel gain and midscale matching.
15.Output voltages and currents are cophased.
16.Low glitch for improved sound quality.
17.Both channels are 100% tested at 16 · FS.
18.Low Power—only 225 mW typ, 260 mW max.
19.Five-wire interface for individual DAC control.
AD1865–SPECIFICATIONS
(TA = +258C, +VL = +VS = +5 V and –VS = –5 V, FS = 705.6 kHz, no MSB adjustment
or deglitcher)ACCURACY
POWER SUPPLY
TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS*VL to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 V to 6.0 V
VS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 V to 6.0 V
–VS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . .–6.0 V to 0 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V
Digital Inputs to DGND . . . . . . . . . . . . . . . . . . . . .–0.3 to VL
Short Circuit Protection . . . . . . . .Indefinite Short to Ground
Soldering (10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . .+300°C
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1865 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE*N = Plastic DIP, R = Small Outline IC Package.
PIN DESIGNATIONS
PINOUT
(24-Pin DIP Package)
AD1865
TOTAL HARMONIC DISTORTION + NOISETotal harmonic distortion plus noise (THD+N) is defined as
the ratio of the square root of the sum of the squares of the am-
plitudes of the harmonics and noise to the value of the funda-
mental input frequency. It is usually expressed in percent.
THD+N is a measure of the magnitude and distribution of lin-
earity error, differential linearity error, quantization error and
noise. The distribution of these errors may be different, depend-
ing on the amplitude of the output signal. Therefore, to be most
useful, THD+N should be specified for both large (0 dB) and
small (–20 dB, –60 dB) signal amplitudes. THD+N measure-
ments for the AD1865 are made using the first 19 harmonics
and noise out to 30 kHz.
SIGNAL-TO-NOISE RATIOThe signal-to-noise ratio is defined as the ratio of the amplitude
of the output when a full-scale code is entered to the amplitude
of the output when a midscale code is entered. It is measured
using a standard A-Weight filter. SNR for the AD1865 is mea-
sured for noise components out to 30 kHz.
CHANNEL SEPARATIONChannel separation is defined as the ratio of the amplitude of a
full-scale signal appearing on one channel to the amplitude of
that same signal which couples onto the adjacent channel. It is
usually expressed in dB. For the AD1865 channel separation is
measured in accordance with EIAJ Standard CP-307, Section
D-RANGE DISTORTION
D-Range distortion is equal to the value of the total harmonic
distortion + noise (THD+N) plus 60 dB when a signal level of
–60 dB below full scale is reproduced. D-Range is tested with a
1 kHz input sine wave. This is measured with a standard A-Weight
filter as specified by EIAJ Standard CP-307.
GAIN ERRORThe gain error specification indicates how closely the output of
a given channel matches the ideal output for given input data. It
is expressed in % of FSR and is measured with a full-scale out-
put signal.
INTERCHANNEL GAIN MATCHINGThe gain matching specification indicates how closely the ampli-
tudes of the output signals match when producing identical in-
put data. It is expressed in % of FSR (Full-Scale Range = 6 V
for the AD1865) and is measured with full-scale output signals.
MIDSCALE ERRORMidscale error is the deviation of the actual analog output of a
given channel from the ideal output (0 V) when the twos
complement input code representing half scale is loaded into the
input register of the DAC. It is expressed in mV and is mea-
sured with half-scale output signals.
INTERCHANNEL MIDSCALE MATCHINGThe midscale matching specification indicates how closely the
amplitudes of the output signals of the two channels match
when the twos complement input code representing half scale is
loaded into the input register of both channels. It is expressed in
mV and is measured with half-scale output signals.
FUNCTIONAL DESCRIPTIONThe AD1865 is a complete, monolithic, dual 18-bit audio DAC.
No external components are required for operation. As shown in
the block diagram, each chip contains two voltage references,
two output amplifiers, two 18-bit serial input registers and two
18-bit DACs.
The voltage reference section provides a reference voltage for
each DAC circuit. These voltages are produced by low-noise
bandgap circuits. Buffer amplifiers are also included. This com-
bination of elements produces reference voltages that are unaf-
fected by changes in temperature and age.
The output amplifiers use both MOS and bipolar devices and
incorporate an all NPN output stage. This design technique
produces higher slew rate and lower distortion than previous
techniques. Frequency response is also improved. When com-
bined with the appropriate on-chip feedback resistor, the output
op amps convert the output current to output voltages.
The 18-bit D/A converters use a combination of segmented de-
coder and R-2R architecture to achieve consistent linearity and
differential linearity. The resistors which form the ladder struc-
ture are fabricated with silicon chromium thin film. Laser trim-
ming of these resistors further reduces linearity errors resulting
in low output distortion.
The input registers are fabricated with CMOS logic gates.
These gates allow the achievement of fast switching speeds and
low power consumption, contributing to the low glitch and low
power dissipation of the AD1865.
+VS
TRIM
MSB
DGND
AGND
VOUT
IOUT
–VS
IOUT
+VL
VOUT
TRIM
MSB
CLK
AGND
NC = NO CONNECTAD1865 Block Diagram (DIP Package)
FREQUENCY – kHz16Figure 1.THD+N (dB) vs. Frequency (kHz)Figure 2.
THD+N – %
TEMPERATURE – °C Figure 3.THD+N (%) vs. Temperature (°C)
LOAD RESISTANCE – W
THD+N – dBFigure 4.THD+N (dB) vs. Load Resistance (W)
Figure 5.
GROUNDING RECOMMENDATIONSThe AD1865 has three ground pins, two labeled AGND and
one labeled DGND. AGND, the analog ground pins, are the
“high quality” ground references for the device. To minimize
distortion and reduce crosstalk between channels, the analog
ground pins should be connected together only at the analog
common point in the system. As shown in Figure 6, the AGND
pins should not be connected at the chip.
NC = NO CONNECT
–ANALOG
SUPPLY
DIGITAL
SUPPLY
VOUT
ANALOG
SUPPLY
VOUTFigure 6.Recommended Circuit Schematic
The digital ground pin returns ground current from the digital
logic portions of the AD1865 circuitry. This pin should be con-
nected to the digital common pin in the system. Other digital
logic chips should also be referred to that point. The analog and
digital grounds should be connected together at one point in the
system, preferably at the power supply.
POWER SUPPLIES AND DECOUPLINGThe AD1865 has three power supply input pins. –VS provides
the supply voltages which operate the analog portions of the
DAC including the voltage references, output amplifiers and
control amplifiers. The –VS supplies are designed to operate
from –5 V supplies. Each supply should be decoupled to analog
common using a 0.1 mF capacitor in parallel with a 10 mF
capacitor. Good engineering practice suggests that the bypass
capacitors be placed as close as possible to the package pins.
This minimizes the parasitic inductive effects of printed circuit
board traces.
The +VL supply operates the digital portions of the chip includ-
ing the input shift registers and the input latching circuitry.
This supply should be bypassed to digital common using a
0.1 mF capacitor in parallel with a 10 mF capacitor. +VL oper-
ates with a +5 V supply. In order to assure proper operation of
the AD1865, –VS must be the most negative power supply volt-
age at all times.
Though separate positive power supply pins are provided for
the analog and digital portions of the AD1865, it is also possible
to use the AD1865 in systems featuring a single +5 V power
supply. In this case, both the +VS and +VL input pins should be
connected to the single +5 V power supply. This feature allows
AD1865–Analog Circuit ConsiderationAs with most linear circuits, changes in the power supplies will
affect the output of the DAC. Analog Devices recommends that
well regulated power supplies with less than 1% ripple be incor-
porated into the design of an audio system.
DISTORTION PERFORMANCE AND TESTINGThe THD+N figure of an audio DAC represents the amount of
undesirable signal produced during reconstruction and playback
of an audio waveform. The THD+N specification, therefore,
provides a direct method to classify and choose an audio DAC
for a desired level of performance. Figure 1 illustrates the typ-
ical THD+N performance of the AD1865 versus frequency. A
load impedance of at least 1.5 kW is recommended for best
THD+N performance.
Analog Devices tests and grades all AD1865s on the basis of
THD+N performance. During the distortion test, a high-speed
digital pattern generator transmits digital data to each channel
of the device under test. Eighteen-bit data is transmitted at
705.6 kHz (16 · FS). The test waveform is a 990.5 Hz sine wave
with 0 dB, –20 dB and –60 dB amplitudes. A 4096 point FFT
calculates total harmonic distortion + noise, signal-to-noise ratio,
D-Range and channel separation. No deglitchers or MSB trims
are used in the testing of the AD1865.
OPTIONAL MSB ADJUSTMENTUse of optional adjust circuitry allows residual distortion error
to be eliminated. This distortion is especially important when
low amplitude signals are being reproduced. The MSB adjust
circuitry is shown in Figure 7. The trim potentiometer should
be adjusted to produce the lowest distortion using an input sig-
nal with a –60 dB amplitude.
NC = NO CONNECTFigure 7.Optional THD+N Adjust Circuitry
