AD1864N-K ,Complete Dual 18-Bit Audio DACFEATURESDIP BLOCK DIAGRAMSDual Serial Input, Voltage Output DACsNo External Components Required1 24 ..
AD1864P ,Complete Dual 18-Bit Audio DACApplications: VOUT 17 VOUT+ +Compact Disc Players+V 9 16L –VLMultivoice Keyboard InstrumentsDR 10 1 ..
AD1865N ,Complete Dual 18-Bit 16 x Fs Audio DACSPECIFICATIONSor deglitcher)Parameter Min Typ Max UnitRESOLUTION 18 BitsDIGITAL INPUTS V 2.0 +V VIH ..
AD1865N-J ,Complete Dual 18-Bit 16 x Fs Audio DACSpecifications subject to change without notice.–2–REV. 0AD1865ABSOLUTE MAXIMUM RATINGS**Stresses g ..
AD1865N-J ,Complete Dual 18-Bit 16 x Fs Audio DACComplete Dual 18-Bita16 3 F Audio DACSAD1865*FUNCTIONAL BLOCK DIAGRAM
AD1865N-K ,Complete Dual 18-Bit 16 3 FS Audio DACSPECIFICATIONSor deglitcher)Parameter Min Typ Max UnitRESOLUTION 18 BitsDIGITAL INPUTS V 2.0 +V VIH ..
AD8320ARP ,Serial Digital Controlled Variable Gain Line DriverFEATURESFUNCTIONAL BLOCK DIAGRAM8-Bit Serial Gain ControlV/V/LSB Linear Gain ResponseVCC GND36 dB G ..
AD8321AR ,Gain Programmable CATV Line DriverSpecificationsREV. 0Information furnished by Analog Devices is believed to be accurate andreliable. ..
AD8321AR-REEL ,Gain Programmable CATV Line DriverFEATURES FUNCTIONAL BLOCK DIAGRAMLinear in dB Gain Response Over >53 dB RangeVCC GNDDrives Low Dist ..
AD8322ARU ,5 V CATV Line Driver Coarse Step Output Power ControlFEATURES FUNCTIONAL BLOCK DIAGRAMSupports DOCSIS Standard for Reverse PathV (7 PINS)CCTransmissionG ..
AD8322ARU-REEL ,5 V CATV Line Driver Coarse Step Output Power Controlapplications such as cable@ MAX GAINmodems that are designed to the MCNS-DOCSIS upstream –60standar ..
AD8323 ,5 V CATV Line Driver Fine Stepapplications such as cableP = 60dBmV @ MAX GAINOmodems that are designed to the MCNS-DOCSIS upstrea ..
AD1864N-AD1864N-J-AD1864N-K-AD1864P
Complete Dual 18-Bit Audio DAC
REV.A
Complete Dual
18-Bit Audio DAC
FEATURES
Dual Serial Input, Voltage Output DACs
No External Components Required
Operates at 8 3 Oversampling per Channel65 V to 612 V Operation
Cophased Outputs
115 dB Channel Separation60.3% Interchannel Gain Matching
0.0017% THD+N
APPLICATIONS
Multichannel Audio Applications:
Compact Disc Players
Multivoice Keyboard Instruments
DAT Players and Recorders
Digital Mixing Consoles
Multimedia Workstations
PRODUCT DESCRIPTIONThe AD1864 is a complete dual 18-bit DAC offering excellent
THD+N, while requiring no external components. Two com-
plete signal channels are included. This results in cophased
voltage or current output signals and eliminates the need for
output demultiplexing circuitry. The monolithic AD1864 chip
includes CMOS logic elements, bipolar and MOS linear
elements and laser-trimmed thin-film resistor elements, all
fabricated on Analog Devices BiMOS II process.
The DACs on the AD1864 chip employ a partially-segmented
architecture. The first four MSBs of each DAC are segmented
into 15 elements. The 14 LSBs are produced using standard
R-2R techniques. Segment and R-2R resistors are laser-
trimmed to provide extremely low total harmonic distortion.
This architecture minimizes errors at major code transitions
resulting in low output glitch and eliminating the need for an
external deglitcher. When used in the current output mode, the
AD1864 provides two cophased ±1 mA output signals.
Each channel is equipped with a high performance output
amplifier. These amplifiers achieve fast settling and high slew
rate, producing ±3 V signals at load currents up to 8 mA. Each
output amplifier is short-circuit protected and can withstand
indefinite short circuits to ground.
The AD1864 was designed to balance two sets of opposing
requirements, channel separation and DAC matching. High
channel separation is the result of careful layout techniques. At
the same time, both channels of the AD1864 have been designed
to ensure matched gain and linearity as well as tracking over time
and temperature. This assures optimum performance when used in
stereo and multi-DAC per channel applications.
A versatile digital interface allows the AD1864 to be directly
connected to standard digital filter chips. This interface employs
five signals: Data Left (DL), Data Right (DR), Latch Left (LL),
Latch Right (LR) and Clock (CLK). DL and DR are the serial
input pins for the left and right DAC input registers. Input data
bits are clocked into the input register on the rising edge of
CLK. A low going latch edge updates the respective DAC
output. For systems using only a single latch signal, LL and LR
may be connected together. For systems using only one DATA
signal, DR and DL may be connected together.
The AD1864 operates from ±5 V to ±12 V power supplies. The
digital supplies, VL and –VL, can be separated from the analog
supplies, VS and –VS, for reduced digital feedthrough. Separate
analog and digital ground pins are also provided. The AD1864
typically dissipates only 225 mW, with a maximum power
dissipation of 265 mW.
The AD1864 is packaged in both a 24-pin plastic DIP and a
28-pin PLCC. Operation is guaranteed over the temperature
range of –25°C to +70°C and over the voltage supply range of
±4.75 V to ±13.2 V.
PRODUCT HIGHLIGHTSThe AD1864 is a complete dual 18-bit audio DAC.108 dB signal-to-noise ratio for low noise operation.THD+N is typically 0.0017%.Interchannel gain and midscale matching.Output voltages and currents are cophased.Low glitch for improved sound quality.Both channels are 100% tested at 8 × FS.Low Power—only 225 mW typ, 265 mW max.Five-wire Interface for individual DAC control.
DIP BLOCK DIAGRAMS
–VS
OUTI
+VL
OUTV
TRIM
MSB
CLK
AGND+V–V
TRIM
MSB
DGND
AGND
OUTV
OUTI
AD1864–SPECIFICATIONS
(TA = +258C, 6VL = 6VS = 65 V, FS = 352.8 kHz, without MSB adjustment
unless otherwise noted)ACCURACY
DRIFT (0°C to +70°C)
TOTAL HARMONIC DISTORTION + NOISE*
CHANNEL SEPARATION*
SIGNAL-TO-NOISE RATIO*
D-RANGE* (WITH A-WEIGHT FILTER)
POWER SUPPLY
TEMPERATURE RANGE
FREQUENCY – kHz
THD+N – dBFigure 1. THD+N vs. Frequency
Figure 2. Channel Separation vs. Frequency
Figure 3. THD+N vs. Temperature
Figure 4. Power Dissipation vs. Supply Voltage
Figure 5. THD+N vs. Load Resistance
Figure 6. Gain Linearity Error vs. Input Amplitude
AD1864
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1864 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*VL to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . .0 V to 13.2 V
VS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . .0 V to 13.2 V
–VL to DGND . . . . . . . . . . . . . . . . . . . . . . . . .–13.2 V to 0 V
–VS to AGND . . . . . . . . . . . . . . . . . . . . . . . . .–13.2 V to 0 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V
Digital Inputs to DGND . . . . . . . . . . . . . . . . . . .–0.3 V to VL
Short-Circuit Protection . . . . . . . .Indefinite Short to Ground
Soldering (10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . .+300°C
*Stresses greater than those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PIN CONFIGURATIONS
DIP Package
PLCC Package
IOUT
AGND
VOUT
–VL
MSB
TRIM–V+V
TRIM
MSB
IOUT
AGND
VOUTL
PIN FUNCTION DESCRIPTIONS
ORDERING GUIDE
TOTAL HARMONIC DISTORTION + NOISETotal Harmonic Distortion plus Noise (THD+N) is defined as
the ratio of the square root of the sum of the squares of the
amplitudes of the harmonics and noise to the value of the
fundamental input frequency. It is usually expressed in percent.
THD+N is a measure of the magnitude and distribution of
linearity error, differential linearity error, quantization error and
noise. The distribution of these errors may be different, depending
on the amplitude of the output signal. Therefore, to be most
useful, THD+N should be specified for both large (0 dB) and
small (–20 dB, –60 dB) signal amplitudes. THD+N measure-
ments for the AD1864 are made using the first 19 harmonics
and noise out to 30 kHz.
SIGNAL-TO-NOISE RATIOThe Signal-to-Noise Ratio is defined as the ratio of the ampli-
tude of the output when a full- scale code is entered to the
amplitude of the output when a midscale code is entered. It is
measured using a standard A-Weight filter. SNR for the
AD1864 is measured for noise components up to 30 kHz.
CHANNEL SEPARATIONChannel separation is defined as the ratio of the amplitude of a
full-scale signal appearing on one channel to the amplitude of
that same signal which couples onto the adjacent channel. It is
usually expressed in dB. For the AD1864 channel separation is
measured in accordance with EIAJ Standard CP-307, Section 5.5.
D-RANGE DISTORTIOND-Range distortion is equal to the value of the total harmonic
distortion + noise (THD+N) plus 60 dB when a signal level of
60 dB below full-scale is reproduced. D-Range is tested with a
1 kHz input sine wave. This is measured with a standard
A-Weight filter as specified by EIAJ Standard CP-307.
GAIN ERRORThe gain error specification indicates how closely the output of
a given channel matches the ideal output for given input data. It
is expressed in % of FSR and is measured with a full-scale output
signal.
INTERCHANNEL GAIN MATCHINGThe gain matching specification indicates how closely the
amplitudes of the output signals match when producing
identical input data. It is expressed in % of FSR (Full-Scale
Range = 6 V for the AD1864) and is measured with full-scale
output signals.
MIDSCALE ERRORMidscale error is the deviation of the actual analog output of a
given channel from the ideal output (0 V) when the twos comple-
ment input code representing half scale is loaded into the input
register of the DAC. It is expressed in mV.
INTERCHANNEL MIDSCALE MATCHINGThe midscale matching specification indicates how closely the
amplitudes of the output signals of the two channels match
when the twos complement input code representing half scale is
loaded into the input register of both channels. It is expressed in
mV and is measured with half-scale output signals.
–VS
OUTI
+VL
OUTV
TRIM
MSB
CLK
AGND
OUT
OUTDIP Block Diagram
FUNCTIONAL DESCRIPTIONThe AD1864 is a complete, monolithic, dual 18-bit audio DAC.
No external components are required for operation. As shown in
the block diagram, each chip contains two voltage references,
two output amplifiers, two 18-bit serial input registers and two
18-bit DACs.
The voltage reference section provides a reference voltage for
each DAC circuit. These voltages are produced by low-noise
bandgap circuits. Buffer amplifiers are also included. This
combination of elements produces reference voltages that are
unaffected by changes in temperature and time.
The output amplifiers use both MOS and bipolar devices and
incorporate an all NPN output stage. This design technique
produces higher slew rate and lower distortion than previous
techniques. Frequency response is also improved. When
combined with the appropriate on-chip feedback resistor, the
output op amps convert the output current to output voltages.
The 18-bit D/A converters use a combination of segmented
decoder and R-2R architecture to achieve consistent linearity
and differential linearity. The resistors which form the ladder
structure are fabricated with silicon chromium thin film. Laser
trimming of these resistors further reduces linearity errors
resulting in low output distortion.
The input registers are fabricated with CMOS logic gates.
These gates allow the achievement of fast switching speeds and
low power consumption, contributing to the low glitch and low
power dissipation of the AD1864.
AD1864
GROUNDING RECOMMENDATIONSThe AD1864 has three ground pins, two labeled AGND and
one labeled DGND. AGND, the analog ground pins, are the
“high quality” ground references for the device. To minimize
distortion and reduce crosstalk between channels, the analog
ground pins should be connected together only at the analog
common point in the system. As shown in Figure 7, the AGND
pins should not be connected at the chip.
AD1864
VOUT
–ANALOG
SUPPLY
DIGITAL
SUPPLY
–DIGITAL
ANALOG
SUPPLYFigure 7. Recommended DIP Circuit Schematic
The digital ground pin returns ground current from the digital
logic portions of the AD1864 circuitry. This pin should be
connected to the digital common pin in the system. Other
digital logic chips should also be referred to that point. The
analog and digital grounds should be connected together at one
point in the system, preferably at the power supply.
POWER SUPPLIES AND DECOUPLINGThe AD1864 has four power supply pins. ±VS provides the
supply voltages that operate the analog portions of the DAC,
including the voltage references, output amplifiers and control
amplifiers. The ±VS supplies are designed to operate from ±5 V
to ±12 V. These supplies should be decoupled to analog
common using 0.1 μF capacitors. Good engineering practice
suggests that the bypass capacitors be placed as close as possible
to the package pins. This minimizes the parasitic inductive
effects of printed circuit board traces.
The ±VL supplies operate the digital portions of the chip,
including the input shift registers and the input latching
circuitry. These supplies should be bypassed to digital common
using 0.1 μF capacitors. ±VL operates with ±5 V to ±12 V
supplies. In order to assure proper operation of the AD1864,
–VS must be the most negative power supply voltage at all times.
Though separate positive and negative power supply pins are
provided for the analog and digital portions of the AD1864, it is
also possible to use the AD1864 in systems featuring a single
positive and a single negative power supply. In this case, the
+VS and +VL input pins should be connected to the positive
power supply. –VS and –VL should be connected to the single
negative supply. This feature allows reduction of the cost and
complexity of the system power supply.
As with most linear circuits, changes in the power supplies will
affect the output of the DAC. Analog Devices recommends that
well regulated power supplies with less than 1% ripple be
incorporated into the design of an audio system.
DISTORTION PERFORMANCE AND TESTINGThe THD+N figure of an audio DAC represents the amount of
undesirable signal produced during reconstruction and playback
of an audio waveform. The THD+N specification, therefore,
provides a direct method to classify and choose an audio DAC
for a desired level of performance. Figure 1 illustrates the typical
THD+N performance of the AD1864 versus frequency. A load
impedance of at least 1.5 kΩ is recommended for best THD+N
performance.
Analog Devices tests and grades all AD1864s on the basis of
THD+N performance. During the distortion test, a high speed
digital pattern generator transmits digital data to each channel
of the device under test. Eighteen-bit data is latched into the
DAC at 352.8 kHz (8 × FS). The test waveform is a 990.5 kHz
sine wave with 0 dB, –20 dB and –60 dB amplitudes. A 4096
point FFT calculates total harmonic distortion + noise,
signal-to-noise ratio, D-Range and channel separation. No
deglitchers or MSB trims are used.
OPTIONAL MSB ADJUSTMENTUse of optional adjust circuitry allows residual distortion error
to be eliminated. This distortion is especially important when
low amplitude signals are being reproduced. The MSB adjust
circuitry is shown in Figure 8. The trim pot should be adjusted
to produce the lowest distortion using an input signal with a
–60 dB amplitude.
