AD1859JRS ,Stereo, Single-Supply 18-Bit Integrated DACSPECIFICATIONSTEST CONDITIONS UNLESS OTHERWISE NOTEDSupply Voltages (AV , DV ) +5.0 VDD DDAmbient T ..
AD1859JRS-REEL ,Stereo, Single-Supply 18-Bit Integrated (Sigma Delta) DACspecifications).Attenuation setting is 0 dB.Values in bold typeface are tested; all others are guar ..
AD1861 ,16-Bit/18-Bit, 16 3 FS PCM Audio DACspecifications of THD+N and signal-to-noise ratioThe AD1851/AD1861 is a monolithic PCM audio DAC. T ..
AD1861N ,16-Bit/18-Bit, 16 X Fs PCM Audio DACsSPECIFICATIONSAMin Typ Max UnitsDIGITAL INPUTSV 2.0 +V VIH LV 0.8 VILI , V = V 1.0 μAIH IH LI , V = ..
AD1861N ,16-Bit/18-Bit, 16 X Fs PCM Audio DACsSpecifications subject to change without notice.16-BIT 16-BIT16-BIT 16-BIT –V +V–V +V 1 16S 1 16 S ..
AD1861N-J ,16-Bit/18-Bit, 16 X Fs PCM Audio DACsSPECIFICATIONSAMin Typ Max UnitsDIGITAL INPUTSV 2.0 +V VIH LV 0.8 VILI , V = V 1.0 μAIH IH LI , V = ..
AD8315ARM-REEL ,50 dB GSM PA ControllerSpecifications subject to change without notice.–2– REV. BAD8315Table I. Typical
AD8315ARM-REEL7 ,50 dB GSM PA ControllerSpecifications at Selected Frequencies at 25C (Mean and Sigma) 1 dB Dynamic RangeSlope – mV/dB In ..
AD8315ARMZ , 50 dB GSM PA Controller
AD8315ARMZ , 50 dB GSM PA Controller
AD8316ARM-REEL7 , Dual Output GSM PA Controller
AD8316ARM-REEL7 , Dual Output GSM PA Controller
AD1859JR-AD1859JRS
Stereo, Single-Supply 18-Bit Integrated DAC
Stereo, Single-Supply18-Bit Integrated SD DAC
PRODUCT OVERVIEWThe AD1859 is a complete 16-/18-bit single-chip stereo digital
audio playback subsystem. It comprises a variable rate digital
interpolation filter, a revolutionary multibit sigma-delta (∑Δ)
modulator with dither, a jitter-tolerant DAC, switched capacitor
and continuous time analog filters, and analog output drive cir-
cuitry. Other features include an on-chip stereo attenuator and
mute, programmed through an SPI-compatible serial control
port.
The key differentiating feature of the AD1859 is its asynchro-
nous master clock capability. Previous ∑Δ audio DACs re-
quired a high frequency master clock at 256 or 384 times the
intended audio sample rate. The generation and management
of this high frequency synchronous clock is burdensome to the
board level designer. The analog performance of conventional
single bit ∑Δ DACs is also dependent on the spectral purity of
the sample and master clocks. The AD1859 has a digital Phase
Locked Loop (PLL) which allows the master clock to be asyn-
chronous, and which also strongly rejects jitter on the sample
clock (left/right clock). The digital PLL allows the AD1859 to
be clocked with a single frequency (27 MHz for example) while
the sample frequency (as determined from the left/right clock)
can vary over a wide range. The digital PLL will lock to the
new sample rate in approximately 100 ms. Jitter components
15 Hz above and below the sample frequency are rejected by
6 dB per octave. This level of jitter rejection is unprecedented
in audio DACs.
The AD1859 supports continuously variable sample rates with
essentially linear phase response, and with an option for external
analog de-emphasis processing. The clock circuit includes an
on-chip oscillator, so that the user need only provide an external
crystal. The oscillator may be overdriven, if desired, with an ex-
ternal clock source.
(continued on page 7)
*SPI is a registered trademark of Motorola, Inc.REV.A
FEATURES
Complete, Low Cost Stereo DAC System in a Single Die
Package
Variable Rate Oversampling Interpolation Filter
Multibit SD Modulator with Triangular PDF Dither
Discrete and Continuous Time Analog Reconstruction
Filters
Extremely Low Out-of-Band Energy
64 Step (1 dB/Step) Analog Attenuator with Mute
Buffered Outputs with 2 kV Output Load Drive
Rejects Sample Clock Jitter
94 dB Dynamic Range, –88 dB THD+N Performance
Option for Analog De-emphasis Processing with
External Passive Components60.18 Maximum Phase Linearity Deviation
Continuously Variable Sample Rate Support
Digital Phase Locked Loop Based Asynchronous Master
Clock
On-Chip Master Clock Oscillator, Only External Crystal
Is Required
Power-Down Mode
Flexible Serial Data Port (I2S-Justified, Left-Justified,
Right-Justified and DSP Serial Port Modes)
SPI* Compatible Serial Control Port
Single +5 V Supply
28-Pin SOIC and SSOP Packages
APPLICATIONS
Digital Cable TV and Direct Broadcast Satellite Set-Top
Decoder Boxes
Digital Video Disc, Video CD and CD-I Players
High Definition Televisions, Digital Audio Broadcast
Receivers
CD, CD-R, DAT, DCC, ATAPI CD-ROM and MD Players
Digital Audio Workstations, Computer Multimedia
Products
FUNCTIONAL BLOCK DIAGRAM
16- OR 18-BIT
DIGITAL DATAINPUT
ASYNCHRONOUS
DE-EMPHASISSWITCH LEFT
COMMON MODE
ANALOG
OUTPUTS
DE-EMPHASIS
SWITCH RIGHT
DE-EMPHASISMUTEANALOG
SUPPLY
REFERENCE
FILTER ANDGROUND
CONTROL
DATAINPUT
DIGITAL
SUPPLY
POWER
DOWN/RESET
TEST CONDITIONS UNLESS OTHERWISE NOTEDSupply Voltages (AVDD, DVDD)+5.0V
Ambient Temperature25°C
Input Clock (FMCLK)27.1656MHz
Input Signal1001.2938Hz
–0.5dB Full Scale
Input Sample Rate44.1kHz
Measurement Bandwidth10 Hz to 20 kHz
Input Data Word Width18Bits
Load Capacitance100pF
Input Voltage HI (VIH)2.4V
Input Voltage LO (VIL)0.8V
NOTES2S-Justified Mode (Ref. Figure 3).
Device Under Test (DUT) is bypassed, decoupled and dc-coupled as shown in Figure 17 (no de-emphasis circuit).
Performance of the right and left channels are identical (exclusive of “Interchannel Gain Mismatch” and “Interchannel Phase Deviation” specifications).
Attenuation setting is 0 dB.
Values in bold typeface are tested; all others are guaranteed, not tested.
ANALOG PERFORMANCE
DIGITAL INPUTS
AD1859–SPECIFICATIONS
DIGITAL TIMING (Guaranteed over –40°C to +105°C, AVDD = DVDD = +5.0 V ± 10%)tMCP
FMC
tMCH
POWER
TEMPERATURE RANGE
PACKAGE CHARACTERISTICSSOIC θJA (Thermal Resistance [Junction-to-Ambient])
SSOP θJA (Thermal Resistance [Junction-to-Ambient])
AD1859
AD1859
ABSOLUTE MAXIMUM RATINGS*AVDD to AGND
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
DIGITAL FILTER CHARACTERISTICS44.1 kHz FS
32 kHz FS
Other FS
ANALOG FILTER CHARACTERISTICSNOTEStopband nominally repeats itself at multiples of 128 × FS, where FS is the input word rate. Thus the digital filter will attenuate to 62 dB across the frequency
spectrum except for a range ±0.55 × FS wide at multiples of 128 × FS.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
ORDERING GUIDE
PIN CONNECTIONS
Serial Control Port Interface
Digital Audio Serial Input Interface
Gain ErrorWith a near full-scale input, the ratio of actual output to ex-
pected output, expressed as a percentage.
Interchannel Gain MismatchWith identical near full-scale inputs, the ratio of outputs of the
two stereo channels, expressed in decibels.
Gain DriftChange in response to a near full-scale input with a change in
temperature, expressed as parts-per-million (ppm) per °C.
Crosstalk (EIAJ method)Ratio of response on one channel with a zero input to a full-scale
1 kHz sine-wave input on the other channel, expressed in decibels.
Interchannel Phase DeviationDifference in output sampling times between stereo channels,
expressed as a phase difference in degrees between 1 kHz inputs.
Power Supply RejectionWith zero input, signal present at the output when a 300 mV
p-p signal is applied to power supply pins, expressed in decibels
of full scale.
Group DelayIntuitively, the time interval required for an input pulse to ap-
pear at the converter’s output, expressed in seconds (s). More
precisely, the derivative of radian phase with respect to radian
frequency at a given frequency.
Group Delay VariationThe difference in group delays at different input frequencies.
Specified as the difference between the largest and the smallest
group delays in the passband, expressed in microseconds (μs).
DEFINITIONS
Dynamic RangeThe ratio of a full-scale output signal to the integrated output
noise in the passband (0 to 20 kHz), expressed in decibels (dB).
Dynamic range is measured with a –60 dB input signal and is
equal to (S/[THD+N]) + 60 dB. Note that spurious harmonics
are below the noise with a –60 dB input, so the noise level es-
tablishes the dynamic range. This measurement technique is
consistent with the recommendations of the Audio Engineering
Society (AES17-1991) and the Electronics Industries Association
of Japan (EIAJ CP-307).
Total Harmonic Distortion + Noise (THD+N)The ratio of the root-mean-square (rms) value of a full-scale
fundamental input signal to the rms sum of all other spectral
components in the passband, expressed in decibels (dB) and
percentage.
PassbandThe region of the frequency spectrum unaffected by the attenu-
ation of the digital interpolation filter.
Passband RippleThe peak-to-peak variation in amplitude response from equal-
amplitude input signal frequencies within the passband, ex-
pressed in decibels.
StopbandThe region of the frequency spectrum attenuated by the digi-
tal interpolation filter to the degree specified by “stopband
attenuation.”
PIN DESCRIPTIONS
AD1859
Analog Signals
Control and Clock Signals
Power Supply Connections and Miscellaneous
PIN DESCRIPTIONS
(continued from page 1)
The AD1859 has a simple but very flexible serial data input port
that allows for glueless interconnection to a variety of ADCs,
DSP chips, AES/EBU receivers and sample rate converters.
The serial data input port can be configured in left-justified,2S-justified, right-justified and DSP serial port compatible
modes. The AD1859 accepts 16- or 18-bit serial audio data in
MSB-first, twos-complement format. A power-down mode is
offered to minimize power consumption when the device is inac-
tive. The AD1859 operates from a single +5 V power supply. It
is fabricated on a single monolithic integrated circuit using a
0.6 μM CMOS double polysilicon, double metal process, and is
housed in 28-pin SOIC and SSOP packages for operation over
the temperature range –40°C to +105°C.
THEORY OF OPERATIONThe AD1859 offers the advantages of sigma-delta conversion
architectures (no component trims, low cost CMOS process
technology, superb low level linearity performance) with the
advantages of conventional multibit R-2R resistive ladder audio
DACs (no requirement for any high frequency synchronous master
clocks [e.g., 256 or 384 × FS] continuously variable sample rate
support, jitter tolerance, low output noise, etc.).
The use of a multibit sigma-delta modulator means that the
AD1859 generates dramatically lower amounts of out-of-band
noise energy, which greatly reduces the requirement on post
DAC filtering. The required post-filtering is integrated on the
AD1859. The AD1859’s multibit sigma-delta modulator is also
highly immune to digital substrate noise.
The digital phase locked loop feature gives the AD1859 an un-
precedented jitter rejection feature. The bandwidth of the first
order loop filter is 15 Hz; jitter components on the input
left/right clock are attenuated by 6 dB per octave above and be-
low 15 Hz. Jitter on the crystal time base or MCLK input is re-
jected as well (by virtue of the on-chip switched capacitor filter),
but this clock should be low jitter because it is used by the DAC
to convert the audio from the discrete time (sampled) domain to
the continuous time (analog) domain. The AD1859 includes an
on-chip oscillator, so that the user need only provide an inexpen-
sive quartz crystal or ceramic resonator as an external time base.
Serial Audio Data InterfaceThe serial audio data interface uses the bit clock (BCLK) simply
to clock the data into the AD1859. The bit clock may, there-
fore, be asynchronous to the L/R clock. The left/right clock
(LRCLK) is both a framing signal, and the sample frequency input
to the digital phase locked loop. The left/right clock (LRCLK) is
the signal that the AD1859 actually uses to determine the input
sample rate, and it is the jitter on LRCLK that is rejected by the
digital phase locked loop. The SDATA input carries the serial
stereo digital audio in MSB first, twos-complement format.
Digital Interpolation FilterThe purpose of the interpolator is to “oversample” the input
data, i.e., to increase the sample rate so that the attenuation re-
quirements on the analog reconstruction filter are relaxed. The
AD1859 interpolator increases the input data sample rate by a
variable factor depending on the sample frequency of the incom-
the fourth stage is a second-order comb filter. The FIR filter
implementation is multiplier-free, i.e., the multiplies are per-
formed using shift-and-add operations.
Multibit Sigma-Delta ModulatorThe AD1859 employs a four-bit sigma-delta modulator. Whereas a
traditional single bit sigma-delta modulator has two levels of quan-
tization, the AD1859’s has 17 levels of quantization. Traditional
single bit sigma-delta modulators sample the input signal at 64
times the input sample rate; the AD1859 samples the input sig-
nal at nominally 128 times the input sample rate. The addi-
tional quantization levels combined with the higher oversampling
ratio means that the AD1859 DAC output spectrum contains
dramatically lower levels of out-of-band noise energy, which is a
major stumbling block with more traditional single bit sigma-
delta architectures. This means that the post-DAC analog re-
construction filter has reduced transition band steepness and
attenuation requirements, which equates directly to lower phase
distortion. Since the analog filtering generally establishes the
noise and distortion characteristic of the DAC, the reduced
requirements translate into better audio performance.
Multibit sigma-delta modulators bring an additional benefit:
they are essentially free of stability (and therefore potential loop
oscillation) problems. They are able to use a wider range of the
voltage reference, which can increase the overall dynamic range
of the converter.
The conventional problem which limits the performance of
multibit sigma delta converters is the nonlinearity of the passive
circuit elements used to sum the quantization levels. Analog
Devices has developed (and been granted patents on) a revolu-
tionary architecture which overcomes the component linearity
problem that otherwise limits the performance of multibit sigma
delta audio converters. This new architecture provides the
AD1859 with the same excellent differential nonlinearity and
linearity drift (over temperature and time) specifications as
single bit sigma-delta DACs.
The AD1859’s multibit modulator has another important ad-
vantage; it has a high immunity to substrate digital noise. Sub-
strate noise can be a significant problem in mixed-signal
designs, where it can produce intermodulation products that
fold down into the audio band. The AD1859 is approximately
eight times less sensitive to digital substrate noise (voltage refer-
ence noise injection) than equivalent single bit sigma-delta
modulator based DACs.
Dither GeneratorThe AD1859 includes an on-chip dither generator, which is in-
tended to further reduce the quantization noise introduced by
the multibit DAC. The dither has a triangular Probability Dis-
tribution Function (PDF) characteristic, which is generally con-
sidered to create the most favorable noise shaping of the residual
quantization noise. The AD1859 is among the first low cost, IC
audio DACs to include dithering.
Analog FilteringThe AD1859 includes a second-order switched capacitor dis-
crete time low-pass filter followed by a first-order analog con-
tinuous time low-pass filter. These filters eliminate the need for
any additional off-chip external reconstruction filtering. This
AD1859
Option for Analog De-emphasis ProcessingThe AD1859 includes three pins for implementing an external
analog 50/15 μs (or possibly the CCITT J. 17) de-emphasis fre-
quency response characteristic. A control pin DEEMP (Pin 2)
enables de-emphasis when it is asserted HI. Two analog out-
puts, EMPL (Pin 3) and EMPR (Pin 26) are used to switch the
required analog components into the output stage of the AD1859.
An analog implementation of de-emphasis is superior to a digital
implementation in several ways. It is generally lower noise, since
digital de-emphasis is usually created using recursive IIR filters,
which inject limit cycle noise. Also the digital de-emphasis is be-
ing applied in front of the primary analog noise generation source,
the DAC modulator, and its high frequency noise contributions
are not attenuated. An analog de-emphasis circuit is down-
stream from the relatively “noisy” DAC modulator and thus pro-
vides a more effective noise reduction role (which was the original
intent of the emphasis/de-emphasis scheme). A final key advan-
tage of analog de-emphasis is that it is sample rate invariant, so
that users can fully exploit the sample rate range of the AD1859
and simultaneously use de-emphasis. Digital implementations gen-
erally only support fixed, standard sample rates.
Digital Phase Locked LoopThe digital PLL is adaptive, and locks to the applied sample rate
(on the LRCLK Pin 13) in 100 ms to 200 ms. The digital PLL
is initially in “fast” mode, with a wide lock capture bandwidth.
The phase detector automatically switches the loop filter into
“slow” mode as phase lock is gradually obtained. The loop
bandwidth is 15 Hz in slow mode. Since the loop filter is first
order, the digital PLL will reject jitter on the left/right clock
above 15 Hz, with an attenuation of 6 dB per octave. The jitter
rejection frequency response is shown in Figure 1.
Figure 1.Digital PLL Jitter Rejection
OPERATING FEATURES
Serial Data Input PortThe AD1859 uses the frequency of the left/right input clock to
determine the input sample rate. LRCLK must run continu-
ously and transition twice per stereo sample period (except in
the left-justified DSP serial port style mode, when it transitions
four times per stereo sample period). The bit clock (BCLK) is
edge sensitive and may be used in a gated or burst mode (i.e., a
stream of pulses during data transmission followed by periods of
inactivity). The bit clock is only used to write the audio data
into the serial input port. It is important that the left/right clock
is “clean” with monotonic rising and falling edge transitions and
no excessive overshoot or undershoot which could cause false
clock triggering of the AD1859.
The AD1859’s flexible serial data input port accepts data in
twos-complement, MSB-first format. The left channel data
field always precedes the right channel data field. The input
data consists of either 16 or 18 bits, as established by the 18/16
input control (Pin 8). All digital inputs are specified to TTL
logic levels. The input data port is configured by control pins.
Serial Input Port ModesThe AD1859 uses two multiplexed input pins to control the
mode configuration of the input data port. IDPM0 and IDPM1
program the input data port mode as follows:
Figure 2 shows the right-justified mode. LRCLK is HI for the
rising edge of BCLK. The MSB is delayed 14-bit clock periods
(in 18-bit input mode) or 16-bit clock periods (in 16-bit input
mode) from an LRCLK transition, so that when there are 64
MSB-1MSB-2LSB+2LSB+1LSBMSBMSB-1MSB-2LSBLSB+2LSB+1LSB
LEFT CHANNELRIGHT CHANNEL
MSB
BCLK
INPUT
SDATA
INPUT
LRCLK
INPUT
