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AD1855JRS-AD1855JRSRL
Stereo, 96 kHz, Multibit DAC
REV. B
Stereo, 96 kHz, Multibit �� DAC
FUNCTIONAL BLOCK DIAGRAM
96/48FS
ANALOG
OUTPUTS2
ZERO
FLAG
ANALOG
SUPPLY
DE-EMPHASISMUTEPD/RSTSERIAL
MODE
16-/18-/20-/24-BIT
DIGITAL
DATA INPUT
384/256
X2MCLK
FEATURES
5 V Stereo Audio DAC System
Accepts 16-/18-/20-/24-Bit Data
Supports 24 Bits and 96 kHz Sample Rate
Multibit Sigma-Delta Modulator with “Perfect Differen-
tial Linearity Restoration” for Reduced Idle Tones
and Noise Floor
Data Directed Scrambling DAC—Least Sensitive to
Jitter
Differential Output for Optimum Performance
113 dB Signal-to-Noise and Dynamic Range at 48 kHz
Sample Rate
110 dB Signal-to-Noise and Dynamic Range at 96 kHz
Sample Rate
–97 dB THD+N
On-Chip Volume Control with 1024 Steps
Hardware and Software Controllable Clickless Mute
Zero Input Flag Outputs for Left and Right Channels
Digital De-Emphasis Processing
Supports 128, 256, 384, and 512 � FS Master Mode
Clock
Switchable Clock Doubler
Power-Down Mode Plus Soft Power-Down Mode
Flexible Serial Data Port with Right-Justified, Left-
Justified, I2S-Compatible and DSP Serial Port Modes
28-Lead SSOP Plastic Package
APPLICATIONS
DVD, CD, Set-Top Boxes, Home Theater Systems, Auto-
motive Audio Systems, Computer Multimedia Prod-
ucts, Sampling Musical Keyboards, Digital Mixing
Consoles, Digital Audio Effects Processors*Patents Pending.
PRODUCT OVERVIEWThe AD1855 is a high performance, single-chip stereo, audio
DAC delivering 113 dB Dynamic Range and SNR (A-weighted—
not muted) at 48 kHz sample rate. It is comprised of a multibit
sigma-delta modulator with dither, continuous time analog
filters and analog output drive circuitry. Other features include
an on-chip stereo attenuator and mute, programmed through an
SPI-compatible serial control port. The AD1855 is fully com-
patible with current DVD formats, including 96 kHz sample
frequency and 24 bits. It is also backwards compatible by sup-
porting 50 µs/15 µs digital de-emphasis intended for “redbook”
44.1 kHz sample frequency playback from compact discs.
The AD1855 has a very simple but very flexible serial data input
port that allows for glueless interconnection to a variety of ADCs,
DSP chips, AES/EBU receivers and sample rate converters.
The AD1855 can be configured in left-justified, I2S, right-
justified, or DSP serial port compatible modes. The AD1855
accepts 16-/18-/20-/24-bit serial audio data in MSB first, twos-
complement format. A power-down mode is offered to mini-
mize power consumption when the device is inactive. The
AD1855 operates from a single +5 V power supply. It is fabri-
cated on a single monolithic integrated circuit and housed in a
28-lead SSOP package for operation over the temperature range
0°C to +70°C.
AD1855–SPECIFICATIONS
TEST CONDITIONS UNLESS OTHERWISE NOTEDSupply Voltages (AVDD, DVDD)+5.0 V
Ambient Temperature+25°C
Input Clock24.576 MHz (512 × FS Mode)
Input Signal1.0013 kHz
–0.5 dB Full Scale
Input Sample Rate48 kHz
Measurement Bandwidth20 Hz to 20 kHz
Word Width20 Bits
Load Impedance6 kΩ
Input Voltage HI4.0 V
Input Voltage LO0.8 V
Performance of right and left channels are identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications).
ANALOG PERFORMANCEResolution
Dynamic Range (20 Hz to 20 kHz, –60 dB Input)
Total Harmonic Distortion + Noise
Analog Outputs
DIGITAL TIMING (Guaranteed over 0�C to +70�C, AVDD = DVDD = +5.0 V � 10%)tDMP
tDMP
tDMP
tDML
tDMH
tDBH
AD1855
DIGITAL I/O (0�C to +70�C)
POWER
TEMPERATURE RANGE
DIGITAL FILTER CHARACTERISTICSSpecifications subject to change without notice.
AD1855
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1855 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*AVDD to AGND
Digital Inputs
*Stresses greater than those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PACKAGE CHARACTERISTICS
ORDERING GUIDE
PIN CONFIGURATION
PIN FUNCTION DESCRIPTIONS11, 15
AD1855
OPERATING FEATURES
Serial Data Input PortThe AD1855’s flexible serial data input port accepts data in
twos-complement, MSB-first format. The left channel data field
always precedes the right channel data field. The input data
consists of either 16, 18, 20 or 24 bits, as established by the
mode select pins (IDPM0 Pin 21 and IDPM1 Pin 20) or the
mode select bits (Data 15 and 14) in the control register
through the SPI (Serial Peripheral Interface) control port. Nei-
ther the pins nor the SPI controls has preference; to ensure
proper control the selection not being used should be tied LO.
Therefore, when the SPI bits are used to control Serial Data
Input Format, Pins 20 and 21 should be tied LO. Similarly,
when the Pins are to be used to select the Data Format, the SPI
bits should be set to Zeros. When the SPI Control Port is not
being used, the SPI Pins (3, 4 and 5) should be tied LO.
Serial Data Input ModeThe AD1855 uses two multiplexed input pins to control the
mode configuration of the input data port mode as follows:
Table I.Serial Data Input ModesFigure 1 shows the right-justified mode. L/RCLK is HI for the
left channel, LO for the right channel. Data is valid on the
rising edge of BCLK. The MSB is delayed 16 bit clock periods
from an L/RCLK transition, so that when there are 64 BCLK
periods per L/RCLK period, the LSB of the data will be right
justified to the next L/RCLK transition. The right-justified
mode can only be used with 16-bit inputs.
Figure 2 shows the I2S-justified mode. L/RCLK is LO for the
left channel and HI for the right channel. Data is valid on the
rising edge of BCLK. The MSB is left justified to an L/RCLK
transition but with a single BCLK period delay. The I2S-justified
mode can be used with 16-/18-/20- or 24-bit inputs.
Figure 3 shows the left-justified mode. L/RCLK is HI for the
left channel, and LO for the right channel. Data is valid on the
rising edge of BLCK. The MSB is left justified to an L/RCLK
transition, with no MSB delay. The left-justified mode can be
used with 16-/18-/20- or 24-bit inputs.
Figure 4 shows the left-justified DSP serial port style mode.
L/RCLK must pulse HI for at least one bit clock period before
the MSB of the left channel is valid, and L/RCLK must pulse
HI again for at least one bit clock period before the MSB of the
right channel is valid. Data is valid on the falling edge of BCLK.
The left-justified DSP serial port style mode can be used with
16-/18-/20- or 24-bit inputs.
Note that in this mode, it is the responsibility of the DSP to
ensure that the left data is transmitted with the first L/RCLK
pulse, and that synchronism is maintained from that point
forward.
The AD1855 is capable of a 32 × FS BCLK frequency “packed
mode” where the MSB is left justified to an L/RCLK transition,
and the LSB is right justified to an L/RCLK transition. L/RCLK
is HI for the left channel and LO for the right channel. Data is
valid on the rising edge of BLCK. Packed mode can be used
when the AD1855 is programmed in right- or left-justified
mode. Packed mode is shown is Figure 5.
Table II.Frequency Mode Settings
Figure 1.Right-Justified Mode
Figure 2.I2S-Justified Mode
Figure 3.Left-Justified Mode
Figure 4.Left-Justified DSP Mode
Figure 5.32 × FS Packed Mode
AD1855
Serial Control PortThe AD1855 serial control port is SPI compatible. SPI (Serial
Peripheral Interface) is an industry standard serial port protocol.
The write-only serial control port gives the user access to: select
input mode, soft power-down control, soft de-emphasis, channel-
specific attenuation and mute (both channels at once). The
AD1855 serial control port consists of three signals, control
clock CCLK (Pin 4), control data CDATA (Pin 5), and control
latch CLATCH (Pin 3). The control data input must be valid
on the control clock rising edge, and the control clock must
make a LO to HI transition when there is valid data. The con-
trol latch must make a LO to HI transition after the LSB has
been clocked into the AD1855, while the control clock is inac-
tive. The timing relation between these signals is shown in Fig-
ure 6. The control bits are assigned as in Table III.
Digital Timing
Table III.Serial Control Bit DefinitionsFigure 6.Serial Control Port Timing
The serial control port is byte oriented. The data is MSB first,
and is unsigned. There is one control register for the left chan-
nel or the right channel, as distinguished by bit Data 10. For
power-up and reset, the default settings are: Data 11 the Mute
control bit, reset default state is LO, which is the normal
(nonmuted) setting. Data 10 is LO, the Volume 9 through Vol-
ume 0 control bits have a reset default value of 11 1111 1111,
which is an attenuation of 0.0 dB (i.e., full scale, no attenua-
tion). The intent with these reset defaults is to enable AD1855
applications without requiring the use of the serial control port.
For those users who do not use the serial control port, it is still
possible to mute the AD1855 output by using the MUTE (Pin
23) signal.
Note that the serial control port timing is asynchronous to the
serial data port timing. Changes made to the attenuator level
will be updated on the next edge of the L/RCLK after the
CLATCH write pulse as shown in Figure 7.
MuteThe AD1855 offers two methods of muting the analog output.
By asserting the MUTE (Pin 23) signal HI, both the left and
right channel are muted. As an alternative, the user can assert
the mute bit in the serial control register (Data 11) HI. The
AD1855 has been designed to minimize pops and clicks when
muting and unmuting the device.
