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AD1854JRSRL ,Stereo, 96 kHz, Multibit DACaStereo, 96 kHz, Multibit DACAD1854PRODUCT
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AD1854JRS-AD1854JRSRL-AD1854KRS-AD1854KRSRL
Stereo, 96 kHz, Multibit DAC
REV. A
Stereo, 96 kHz, Multibit �� DAC
FUNCTIONAL BLOCK DIAGRAMSERIAL
DATA
INTERFACE
8 � FS
INTERPOLATOR
MULTIBIT SIGMA-
DELTA MODULATOR
SERIAL CONTROL
INTERFACE
CLOCK
CIRCUIT
OUTPUT
BUFFER
OUTPUT
BUFFER
MULTIBIT SIGMA-
DELTA MODULATOR
VOLUME
MUTE
CONTROL DATA
INPUT2
DIGITAL
SUPPLY
CLOCK
96/48FS
CLOCK
ANALOG
OUTPUTS2
ZERO
FLAG
ANALOG
SUPPLY
DE-EMPHASISMUTEPD/RSTSERIAL
MODE
16-/18-/20-/24-BIT
DIGITAL
DATA INPUT
AD1854
8 � FS
INTERPOLATOR
FEATURES
5 V Stereo Audio DAC System
Accepts 16-/18-/20-/24-Bit Data
Supports 24 Bits and 96 kHz Sample Rate
Multibit Sigma-Delta Modulator with “Perfect Differential
Linearity Restoration” for Reduced Idle Tones and
Noise Floor
Data Directed Scrambling DAC—Least Sensitive to Jitter
Differential Output for Optimum Performance
113 dB Dynamic Range at 48 kHz Sample Rate
(AD1854KRS)
112 dB Signal-to-Noise at 48 kHz Sample Rate
(AD1854KRS)
–101 THD+N (AD1854KRS)
On-Chip Volume Control with 1024 Steps
Hardware and Software Controllable Clickless Mute
Zero Input Flag Outputs for Left and Right Channels
Digital De-Emphasis Processing
Supports 256 � FS or 384 � FS Master Mode Clock
Switchable Clock Doubler
Power-Down Mode Plus Soft Power-Down Mode
Flexible Serial Data Port with Right-Justified, Left-
Justified, and I2S-Compatible
28-Lead SSOP Plastic Package
APPLICATIONS
DVD, CD, Set-Top Boxes, Home Theater Systems,
Automotive Audio Systems, Sampling Musical
Keyboards, Digital Mixing Consoles, Digital Audio
Effects Processors
PRODUCT OVERVIEWThe AD1854 is a high performance, single-chip stereo, audio
DAC delivering 113 dB Dynamic Range and 112 dB SNR
(A-weighted—not muted) at 48 kHz sample rate. It is comprised
of a multibit sigma-delta modulator with dither, continuous
time analog filters and analog output drive circuitry. Other features
include an on-chip stereo attenuator and mute, programmed
through an SPI-compatible serial control port. The AD1854
is fully compatible with current DVD formats, including 96 kHz
sample frequency and 24 bits. It is also backwards compatible
by supporting 50 µs/15 µs digital de-emphasis intended for
“redbook” 44.1 kHz sample frequency playback from com-
pact discs.
The AD1854 has a very simple but very flexible serial data input
port that allows for glueless interconnection to a variety of ADCs,
DSP chips, AES/EBU receivers and sample rate converters.
The AD1854 can be configured in left-justified, I2S, and right-
justified. The AD1854 accepts serial audio data in MSB first,
twos-complement format. A power-down mode is offered to mini-
mize power consumption when the device is inactive. The AD1854
operates from a single 5 V power supply. It is fabricated on a single
monolithic integrated circuit and housed in a 28-lead SSOP
package for operation over the temperature range 0°C to 70°C.
AD1854–SPECIFICATIONS
TEST CONDITIONS UNLESS OTHERWISE NOTEDSupply Voltages (AVDD, DVDD)5.0 V
Ambient Temperature25°C
Input Clock12.288 MHz (256 × FS Mode)
Input Signal1.0013 kHz
–0.5 dB Full Scale
Input Sample Rate48 kHz
Measurement Bandwidth20 Hz to 20 kHz
Word Width20 Bits
Load Capacitance100 pF
Load Impedance47 kΩ
Input Voltage HI2.4 V
Input Voltage LO0.8 V
Performance of right and left channels are identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications).
ANALOG PERFORMANCEResolution
Signal-to-Noise Ratio (20 Hz to 20 kHz)
Dynamic Range (20 Hz to 20 kHz, –60 dB Input)
Total Harmonic Distortion + Noise (AD1854JRS) VO = 0 dB
Total Harmonic Distortion + Noise (AD1854JRS and
CMOUT
DC Accuracy
Interchannel Crosstalk (EIAJ Method)
Interchannel Phase Deviation
DIGITAL I/O (0�C to 70�C)Input Voltage HI (VIH)
Input Voltage LO (VIL)
Low Level Output Voltage (VOL) IOL = 1 mA
AD1854
POWER
TEMPERATURE RANGE
DIGITAL TIMING (Guaranteed over 0�C to 70�C, AVDD = DVDD = 5.0 V � 10%)
DIGITAL FILTER CHARACTERISTICSSpecifications subject to change without notice.
AD1854
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1854 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*AVDD to AGND
Digital Inputs
*Stresses greater than those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PACKAGE CHARACTERISTICS
ORDERING GUIDEAD1854JRSRL
AD1854KRS
PIN CONFIGURATION
PIN FUNCTION DESCRIPTIONS11, 15
AD1854
OPERATING FEATURES
Serial Data Input PortThe AD1854’s flexible serial data input port accepts data in
twos-complement, MSB-first format. The left channel data field
always precedes the right channel data field. The input data
consists of either 16, 18, 20, or 24 bits, as established by the
mode select pins (IDPM0 Pin 21 and IDPM1 Pin 20) or the
mode select bits (Bits 15 and 14) in the control register through
the SPI (Serial Peripheral Interface) control port. Neither the
pins nor the SPI controls has preference; to ensure proper control,
the selection not being used should be tied LO. Therefore,
when the SPI bits are used to control Serial Data Input Format,
Pins 20 and 21 should be tied LO. Similarly, when the pins are
to be used to select the Data Format, the SPI bits should be set
to zeros. When the SPI Control Port is not being used, the SPI
Pins (3, 4, and 5) should be tied LO.
Serial Data Input ModeThe AD1854 uses two multiplexed input pins to control the
mode configuration of the input data port mode as follows:
Table I.Serial Data Input ModesFigure 1 shows the right-justified mode (16-bit mode). L/RCLK
is HI for the left channel, LO for the right channel. Data is valid
on the rising edge of BCLK. The MSB is delayed 16-bit clock
periods from an L/RCLK transition, so that when there are 64
BCLK periods per L/RCLK period, the LSB of the data will be
right justified to the next L/RCLK transition. The right-justified
mode can also be used with 20-bit or 24-bit inputs as selected
in Table I.
Figure 2 shows the I2S-justified mode. L/RCLK is LO for the
left channel and HI for the right channel. Data is valid on the
rising edge of BCLK. The MSB is left justified to an L/RCLK
transition but with a single BCLK period delay. The I2S-justified
mode can be used with 16-/18-/20- or 24-bit inputs.
Figure 3 shows the left-justified mode. Note: Left-justified mode
is selected by pulsing IDPM1 (Pin 20) with bit clock, that is, tying
bit clock to IDPM1 while IDPM0 (Pin 21) is tied LO. Left-
justified can only be selected this way, it cannot be selected through
SPI Control Port.
L/RCLK is HI for the left channel, and LO for the right channel.
Data is valid on the rising edge of BCLK. The MSB is left-
justified to an L/RCLK transition, with no MSB delay. The
left-justified mode can be used with 16-/18-/20- or 24-bit inputs.
Note that the AD1854 is capable of a 32 × FS BCLK frequency
“packed mode” where the MSB is left-justified to an L/RCLK
transition, and the LSB is right-justified to an L/RCLK transi-
tion. L/RCLK is HI for the left channel, and LO for the right
channel. Data is valid on the rising edge of BCLK. Packed
mode can be used when the AD1854 is programmed in right-
justified mode. Packed mode is shown is Figure 4.
Table II.Frequency Mode SettingsFigure 1.Right-Justified Mode
