AD1853JRS Fast Delivery |IC PHOENIX CO.,LIMITED

AD1853JRS ,Stereo, 24-Bit, 192 kHz, Multibit DACfeatures include an on-chip clickless stereo at-117 dB Signal to Noise (Not Muted) at 48 kHz tenuat ..
AD1853JRSZ , Stereo, 24-Bit, 192 kHz, Multibit DAC
AD1854 ,Stereo, 96 kHz, Multibit Sigma-Delta DACspecifications).ANALOG PERFORMANCEMin Typ Max UnitResolution 20 BitsSignal-to-Noise Ratio (20 Hz to ..
AD1854JRS ,Stereo, 96 kHz, Multibit DACSpecifications Guaranteed 25 °CFunctionality Guaranteed 0 70 °CStorage –55 +125 °CDIGITAL TIMING (G ..
AD1854JRSRL ,Stereo, 96 kHz, Multibit DACSPECIFICATIONSTEST CONDITIONS UNLESS OTHERWISE NOTEDSupply Voltages (AV , DV ) 5.0 VDD DDAmbient Te ..
AD1854JRSRL ,Stereo, 96 kHz, Multibit DACaStereo, 96 kHz, Multibit DACAD1854PRODUCT
AD8313ARMZ-REEL7 , 0.1 GHz to 2.5 GHz 70 dB Logarithmic Detector/Controller
AD8314 ,0.1Applications section.2Mean and Standard Deviation speciﬁcations are available in Table I.3Increased ..
AD8314ACP-REEL ,0.1applications. A setpoint voltage is applied to VSET andment and control of RF signals in the freque ..
AD8314ACP-REEL ,0.1APPLICATIONSwhich averaging of the input waveform occurs.Cellular Handsets (TDMA, CDMA, GSM)RSSI an ..
AD8314ACP-REEL7 ,0.1Applications section.2Mean and Standard Deviation speciﬁcations are available in Table I.3Increased ..
AD8314ACP-REEL7 ,0.1100 MHz–2.7 GHz 45 dBaRF Detector/Controller*AD8314

AD1853JRS
Stereo, 24-Bit, 192 kHz, Multibit DAC
REV.A
Stereo, 24-Bit, 192 kHz, Multibit �� DAC
FEATURES
5 V Stereo Audio DAC System
Accepts 16-/18-/20-/24-Bit Data
Supports 24 Bits and 192 kHz Sample Rate
Accepts a Wide Range of Sample Rates Including:
32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz and 192 kHz
Multibit Sigma-Delta Modulator with “Perfect Differential
Linearity Restoration” for Reduced Idle Tones and
Noise Floor
Data Directed Scrambling DAC—Least Sensitive to Jitter
Differential Output for Optimum Performance
120 dB Signal to Noise (Not Muted) at 48 kHz
(A-Weighted Mono)
117 dB Signal to Noise (Not Muted) at 48 kHz
(A-Weighted Stereo)
119 dB Dynamic Range (Not Muted) at 48 kHz Sample
Rate (A-Weighted Mono)
116 dB Dynamic Range (Not Muted) at 48 kHz Sample
Rate (A-Weighted Stereo)
–107 dB THD+N (Mono Application Circuit, See Figure 30)
–104 dB THD+N (Stereo)
115 dB Stopband Attenuation (96 kHz)
On-Chip Clickless Volume Control
Hardware and Software Controllable Clickless Mute
Serial (SPI) Control for: Serial Mode, Number of Bits,
Interpolation Factor, Volume, Mute, De-Emphasis, Reset
Digital De-Emphasis Processing for 32, 44.1 and 48 kHz
Sample Rates
Clock Auto-Divide Circuit Supports Five Master-Clock
Frequencies
Flexible Serial Data Port with Right-Justified, Left-
Justified, I2S-Compatible and DSP Serial Port Modes
28-Lead SSOP Plastic Package
PRODUCT OVERVIEW
The AD1853 is a complete high performance single-chip stereo
digital audio playback system. It is comprised of a high per-
formance digital interpolation filter, a multibit sigma-delta
modulator, and a continuous-time current-out analog DAC
section. Other features include an on-chip clickless stereo at-
tenuator and mute capability, programmed through an SPI-
compatible serial control port. The AD1853 is fully compatible
with all known DVD formats and supports 48 kHz, 96 kHz and
192 kHz sample rates with up to 24 bits word lengths. It also
provides the “Redbook” standard 50 µs/15 µs digital de-emphasis
filters at sample rates of 32 kHz, 44.1 kHz and 48 kHz.
The AD1853 has a very flexible serial data input port that
allows for glueless interconnection to a variety of ADCs, DSP
chips, AES/EBU receivers and sample rate converters. The
AD1853 can be configured in left-justified, I2S, right-justified,
or DSP serial port compatible modes. The AD1853 accepts
serial audio data in MSB first, twos complement format.
The AD1853 operates from a single +5 V power supply. It is
fabricated on a single monolithic integrated circuit and is housed in
a 28-lead SSOP package for operation over the temperature
range 0°C to +70°C.
FUNCTIONAL BLOCK DIAGRAM
DIGITAL
CLOCK
ANALOG
OUTPUTS2
ZERO
FLAG
ANALOG
SUPPLY
DE-EMPHASISMUTERESETSERIAL
MODE
DIGITAL
DATA INPUT
APPLICATIONS
Hi End: DVD, CD, Home Theater Systems, Automotive
Audio Systems, Sampling Musical Keyboards, Digital
Mixing Consoles, Digital Audio Effects Processors
*Patents Pending.
AD1853–SPECIFICATIONS
TEST CONDITIONS UNLESS OTHERWISE NOTED
Supply Voltages (AVDD, DVDD)+5.0 V
Ambient Temperature+25°C
Input Clock24.576 MHz (512 × FS Mode)
Input Signal996.094 kHz
–0.5 dB Full Scale
Input Sample Rate48 kHz
Measurement Bandwidth20 Hz to 20 kHz
Word Width20 Bits
Input Voltage HI3.5 V
Input Voltage LO0.8 V
ANALOG PERFORMANCE (See Figures)
NOTES
Single-ended current output range: 1 mA ± 0.75 mA.
Performance of right and left channels are identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications).
Specifications subject to change without notice.
DIGITAL I/O (+25�C–AVDD, DVDD = +5.0 V � 10%)
Specifications subject to change without notice.
AD1853
POWER
Supplies
Dissipation
Power Supply Rejection Ratio
Specifications subject to change without notice.
TEMPERATURE RANGE
Specifications Guaranteed
Functionality Guaranteed
Specifications subject to change without notice.
DIGITAL FILTER CHARACTERISTICS
Specifications subject to change without notice.
GROUP DELAY
INT8x Mode
INT4x Mode
Specifications subject to change without notice.
DIGITAL TIMING (Guaranteed Over 0�C to +70�C, AVDD = DVDD = +5.0 V � 10%)
tDML
tDBL
tDBP
tDLS
tDLH
tDDS
AD1853
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1853 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*
AVDD to AGND
Digital Inputs
*Stresses greater than those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PACKAGE CHARACTERISTICS
ORDERING GUIDE
PIN CONFIGURATION
PIN FUNCTION DESCRIPTIONS
AD1853
Figure 1.Right-Justified Mode
Figure 2.I2S-Justified Mode
Figure 3.Left-Justified Mode
Figure 4.Left-Justified DSP Mode
Figure 5. 32 × FS Packed Mode
OPERATING FEATURES
Serial Data Input Port
The AD1853’s flexible serial data input port accepts data in
twos-complement, MSB-first format. The left channel data field
always precedes the right channel data field. The serial mode is
set by using either the external mode pins (IDPM0 Pin 21 and
IDPM1 Pin 20) or the mode select bits (Bits 4 and 5) in the SPI
control register. To control the serial mode using the external
mode pins, the SPI mode select bits should be set to zero
(default at power-up). To control the serial mode using the SPI
mode select bits, the external mode control pins should be
grounded.
In all modes except for the right-justified mode, the serial port
will accept an arbitrary number of bits up to a limit of 24 (extra
bits will not cause an error, but they will be truncated inter-
nally). In the right-justified mode, control register Bits 8 and 9
are used to set the word length to 16, 20, or 24 bits. The default
on power-up is 24-bit mode. When the SPI Control Port is not
being used, the SPI pins (3, 4 and 5) should be tied LO.
Serial Data Input Mode
The AD1853 uses two multiplexed input pins to control the
mode configuration of the input data port mode.
Table I.Serial Data Input Modes
Figure 1 shows the right-justified mode. LRCLK is HI for the
left channel, LO for the right channel. Data is valid on the rising
edge of BCLK.
In normal operation, there are 64-bit clocks per frame (or 32
per half-frame). When the SPI word length control bits (Bits 8
and 9 in the control register) are set to 24 bits (0:0), the serial
port will begin to accept data starting at the 8th bit clock pulse
after the L/RCLK transition. When the word length control bits
are set to 20-bit mode, data is accepted starting at the 12th bit
clock position. In 16-bit mode, data is accepted starting at the
16th-bit clock position. These delays are independent of the
number of bit clocks per frame, and therefore other data formats
are possible using the delay values described above. For detailed
timing, see Figure 6.
Figure 2 shows the I2S mode. L/RCLK is LO for the left chan-
nel, and HI for the right channel. Data is valid on the rising
edge of BCLK. The MSB is left-justified to an L/RCLK transi-
tion but with a single BCLK period delay. The I2S mode can be
used to accept any number of bits up to 24.
Figure 3 shows the left-justified mode. L/RCLK is HI for the
left channel, and LO for the right channel. Data is valid on the
rising edge of BCLK. The MSB is left-justified to an L/RCLK
transition, with no MSB delay. The left-justified mode can
accept any word length up to 24 bits.
Figure 4 shows the DSP serial port mode. L/RCLK must pulse
HI for at least one bit clock period before the MSB of the left
channel is valid, and L/RCLK must pulse HI again for at least
one bit clock period before the MSB of the right channel is
valid. Data is valid on the falling edge of BCLK. The DSP serial
port mode can be used with any word length up to 24 bits.
AD1853
In this mode, it is the responsibility of the DSP to ensure that
the left data is transmitted with the first LRCLK pulse, and that
synchronism is maintained from that point forward.
Note that the AD1853 is capable of a 32 × FS BCLK frequency
“packed mode” where the MSB is left-justified to an L/RCLK
transition, and the LSB is right-justified to the opposite L/RCLK
transition. L/RCLK is HI for the left channel, and LO for the
right channel. Data is valid on the rising edge of BCLK. Packed
mode can be used when the AD1853 is programmed in right-
justified or left-justified mode. Packed mode is shown is Figure 5.
Master Clock Auto-Divide Feature
The AD1853 has a circuit that autodetects the relationship
between master clock and the incoming serial data, and inter-
nally sets the correct divide ratio to run the interpolator and
modulator. The allowable frequencies for each mode are shown
above.
Serial Control Port
The AD1853 serial control port is SPI-compatible. SPI (Serial
Peripheral Interface) is an industry standard serial port protocol.
The write-only serial control port gives the user access to: select
input mode, soft reset, soft de-emphasis, channel specific at-
tenuation and mute (both channels at once). The SPI port is a
3-wire interface with serial data (CDATA), serial bit clock
(CCLK), and data latch (CLATCH). The data is clocked
into an internal shift register on the rising edge of CCLK.
The serial data should change on the falling edge of CCLK and
be stable on the rising edge of CCLK. The rising edge of
CLATCH is used internally to latch the parallel data from the
serial-to-parallel converter. This rising edge should be aligned
with the falling edge of the last CCLK pulse in the 16-bit frame.
The CCLK can run continuously between transactions.
The serial control data is 16-bit MSB first, and is unsigned. Bits
0 and 1 are used to select 1 of 3 registers (control, volume left,
and volume right). The remaining 14 bits (bits 15:2) are used to
carry the data for the selected register. If a volume register is
selected, then the upper 14 bits are used to multiply the digital
input signal by the control word, which is interpreted as an
unsigned number (for example, 11111111111111 is 0 dB, and
01111111111111 is –6 dB, etc.). The default volume control
words on power-up are all 1s (0 dB). The control register only
uses bits 11:2 to carry data; the upper bits (15:12) should al-
ways be written with zeroes, as several test modes are decoded
from these upper bits. The control register defaults on power-up
to 8× interpolation mode, 24-bit right-justified serial mode,
unmuted, and no de-emphasis filter. The intent with these reset
defaults is to enable AD1853 applications without requiring the
use of the serial control port. For those users that do not use the
serial control port, it is still possible to mute the AD1853 output
by using the MUTE pin (Pin 23) signal.
Note that the serial control port timing is asynchronous to the
serial data port timing. Changes made to the attenuator level
will be updated on the next edge of the LRCLK after CLATCH
write pulse as shown in Figure 6.
Table II.
Figure 7.Serial Control Port Timing

Partno	Mfg	Dc	Qty	Available	Descript
AD1853JRS	ADI	N/a	19	avai	Stereo, 24-Bit, 192 kHz, Multibit DAC