AD1849KP ,Serial-Port 16-Bit SoundPort Stereo CodecFEATURES speaker and stereo headphone drive circuits that require noSingle-Chip Integrated SD Digit ..
AD1849KPZ , Serial-Port 16-Bit SoundPort® Stereo Codec
AD1851 ,16-Bit/18-Bit, 16 3 FS PCM Audio DACsSPECIFICATIONSAMin Typ Max UnitsDIGITAL INPUTSV 2.0 +V VIH LV 0.8 VILI , V = V 1.0 μAIH IH LI , V = ..
AD1851N ,16-Bit/18-Bit, 16 X Fs PCM Audio DACsspecifications of THD+N and signal-to-noise ratioThe AD1851/AD1861 is a monolithic PCM audio DAC. T ..
AD1851N ,16-Bit/18-Bit, 16 X Fs PCM Audio DACsAPPLICATIONS LE 611High-End Compact Disc PlayersRDATA 710 FDigital Audio AmplifiersAD1851/ VNC 8 9O ..
AD1851N-J ,16-Bit/18-Bit, 16 X Fs PCM Audio DACsSpecifications subject to change without notice.16-BIT 16-BIT16-BIT 16-BIT –V +V–V +V 1 16S 1 16 S ..
AD830JR ,High Speed, Video Difference AmplifierCHARACTERISTICSOutput Voltage Swing R ≥ 150 Ω±3.2 ±3.5 ±3.2 ±3.5 VLR ≥ 150 Ω, ±4 V ±2.2 +2.7, –2.4 ..
AD830JR. ,High Speed, Video Difference AmplifierCHARACTERISTICSOutput Voltage Swing R ≥ 1 kΩ±12 +13.8, –13.8 ±12 +13.8, –13.8 VLR ≥ 1 kΩ, ±16.5 V ± ..
AD8310ARM ,Fast, Voltage-Out DC-440 MHz 95 dB Logarithmic AmplifierSPECIFICATIONS A SParameter Conditions Min Typ Max UnitINPUT STAGE (Inputs INHI, INLO)1Maximum Inpu ..
AD8310ARMZ ,Fast Response, DCGENERAL DESCRIPTION range. The AD8310 is a complete, dc–440 MHz demodulating The output voltage run ..
AD8310ARMZ-REEL7 ,Fast Response, DCCharacteristics Reordered ....... 6 Changes to Figures 41 and 42 . 20 7/03—Data Sheet Changed from ..
AD8310ARMZ-REEL7 ,Fast Response, DCOverview... 11 Cable-Driving ..... 19 Enable Interface .. 11 DC-Coupled Input ...... 19 Input Inter ..
AD1849KP
Serial-Port 16-Bit SoundPort Stereo Codec
REV.0
Serial-Port 16-Bit
SoundPort Stereo Codec
FEATURES
Single-Chip Integrated SD Digital Audio Stereo Codec
Multiple Channels of Stereo Input and Output
Digital Signal Mixing
On-Chip Speaker and Headphone Drive Capability
Programmable Gain and Attenuation
On-Chip Signal Filters
Digital Interpolation and Decimation
Analog Output Low-Pass
Sample Rates from 5.5 kHz to 48 kHz
44-Lead PLCC and TQFP Packages
Operation from +5 V and Mixed +5 V/+3.3 V Supplies
Serial Interface Compatible with ADSP-21xx Fixed-
Point DSmPs
Compatible with CS4215 (See Text)speaker and stereo headphone drive circuits that require no
additional external components. Dynamic range exceeds 80 dB
over the 20 kHz audio band. Sample rates from 5.5 kHz tokHz are supported from external crystals, from an external
clock, or from the serial interface bit clock.
The Codec includes a stereo pair of ΣΔ analog-to-digital
converters and a stereo pair of ΣΔ digital-to-analog converters.
Analog signals can be input at line levels or microphone levels.
A software controlled programmable gain stage allows
independent gain for each channel going into the ADC. The
ADCs’ output can be digitally mixed with the DACs’ input.
The left and right channel 16-bit outputs from the ADCs are
available over a single bidirectional serial interface that also sup-
ports 16-bit digital input to the DACs and control information.
The AD1849K can accept and generate 8-bit μ-law or A-law
companded digital data.
The ΣΔ DACs are preceded by a digital interpolation filter. An
attenuator provides independent user volume control over each
DAC channel. Nyquist images and shaped quantization noise
are removed from the DACs’ analog stereo output by on-chip
switched-capacitor and continuous-time filters. Two independent
stereo pairs of line-level (or one line-level and one headphone)
outputs are generated, as well as drive for a monaural (mono)
speaker.
(Continued on page 8)
FUNCTIONAL BLOCK DIAGRAM
ANALOG
CRYSTALSANALOG
DIGITALPOWER DOWN
LINE L
LINE R
MIC L
MIC R
2.25V
LINE 0 L
LINE 1 L
HEADPHONE RETURN
ANALOG
OUT
CHAINING
INPUT
CHAINING
OUTPUT
MONO SPEAKER
LINE 0 R
LINE 1 R
DATA/CONTROL
MODE
DATA/CONTROL
TRANSMIT
RESET
DATA/CONTROL
RECEIVE
PARALLEL I/O
BIT CLOCK
FRAME SYNC
DIGITAL
I/O
PRODUCT OVERVIEWThe Serial-Port AD1849K SoundPort® Stereo Codec integrates
the key audio data conversion and control functions into a single
integrated circuit. The AD1849K is intended to provide a com-
plete, single-chip audio solution for multimedia applications
requiring operation from a single +5 V supply. External signal
path circuit requirements are limited to three low tolerance
capacitors for line level applications; anti-imaging filters are
incorporated on-chip. The AD1849K includes on-chip monaural
SoundPort is a registered trademark of Analog Devices, Inc.
AD1849K–SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTEDTemperature25°CDAC Input Conditions
Digital Supply (VDD)5.0V0 dB Attenuation
Analog Supply (VCC)5.0VFull-Scale Digital Inputs
Clock (SCLK)256FS16-Bit Linear Mode
Master Mode256 Bits per FrameOLB = 1
Word Rate (FS)48kHzADC Input Conditions
Input Signal1kHz0 dB PGA Gain
Analog Output Passband20 Hz to 20 kHz–3.0 dB Relative to Full Scale
VIH2.4VLine Input
VIL0.8V16-Bit Linear Mode
External Load Impedance10kΩ
(Line 0)All tests are performed on all ADC and DAC channels.
External Load Impedance48Ω
(Line 1)
External Load Capacitance100pF
(Line 0, 1)
ANALOG INPUT*Accounts for Sum of Worst Case Reference Errors and Worst Case Gain Errors.
PROGRAMMABLE GAIN AMPLIFIER—ADC
DIGITAL DECIMATION AND INTERPOLATION FILTERS*
ANALOG-TO-DIGITAL CONVERTERS
DIGITAL-TO-ANALOG CONVERTERS
AD1849K
AD1849K
MONITOR MIX ATTENUATORStep Size (0.0 dB to –60 dB)*
Step Size (–61.5 dB to –94.5 dB)*
DAC ATTENUATORStep Size (0.0 dB to –60 dB)
Step Size (–61.5 dB to –94.5 dB)*
SYSTEM SPECIFICATIONSSystem Frequency Response*
ANALOG OUTPUTFull-Scale Output Voltage (Line 0 & 1)
Full-Scale Output Voltage (Line 0)
Full-Scale Output Voltage (Line 1)
Full-Scale Output Voltage (Mono Speaker)
Full-Scale Output Voltage (Mono Speaker)
CMOUT Voltage (No Load)
CMOUT Current Drive*
CMOUT Output Impedance
Mute Attenuation of 0 dB
STATIC DIGITAL SPECIFICATIONSLow Level Input Voltage (VIL)
High Level Output Voltage (VOH) at IOH = –2 mA
DIGITAL TIMING PARAMETERS (Guaranteed over +4.75 V to +5.25 V, 08C to +708C)
POWER SUPPLY
CLOCK SPECIFICATIONS**Guaranteed, not tested.
Specifications subject to change without notice.
AD1849K
AD1849K
ABSOLUTE MAXIMUM RATINGS*
WARNING: CMOS device. May be susceptible to high voltagetransient-induced latchup.
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
44-Lead Plastic Leaded Chip Carrier Pinout
0.656 (16.66)
0.650 (16.51)SQ
0.695 (17.65)
0.685 (17.40)SQ
0.048 (1.21)
0.042 (1.07)
TOP VIEW
PIN 1
IDENTIFIER
0.032 (0.81)
0.026 (0.66)
0.021 (0.53)
0.180 (4.57)
0.165 (4.19)
0.63 (16.00)
0.59 (14.99)
0.110 (2.79)
0.085 (2.16)
(1.27)
BSC
0.020 (0.50) R
PIN 1
IDENTIFIER
BOTTOM VIEW
44-Lead TQFP
VDD
PIO0
N/C
LOUT0R
LOUT0L
LOUT1L
LOUT1C
PIO1
LOUT1R
GNDD
COUT1
GNDD
COUT2
PDN
MINR
LINR
MINL
CIN2
VDD
CIN1CLKINV
GNDDSDRXSDTX
SCLK
FSYNCCLKOUT
TSOUTTSIN
LINL
REF
GNDA
CMOUT
GNDA
N/C
MOUT
MOUTR
N/C = NO CONNECT
RESET
D/C
PIN DESCRIPTION
Digital SignalsCIN1
COUT1
CIN2
COUT2
CLKIN
PDN
PIO1
Analog SignalsMINR
LOUT0L
LOUT0R
LOUT1L
LOUT1R
LOUT1C
MOUT
MOUTR
Power Supplies
AD1849K(Continued from page 1)
FUNCTIONAL DESCRIPTIONThis section overviews the functionality of the AD1849K and is
intended as a general introduction to the capabilities of the
device. As much as possible, detailed reference information has
been placed in “Control Registers” and other sections. The user
is not expected to refer repeatedly to this section.
Analog InputsThe AD1849K SoundPort Stereo Codec accepts stereo
line-level and mic-level inputs. These analog stereo signals are
multiplexed to the internal programmable gain amplifier (PGA)
stage. The mic inputs can be amplified by +20 dB prior to the
PGA to compensate for the voltage swing difference between
line levels and typical condenser microphones. The mic inputs
can bypass the +20 dB fixed gain block and go straight to the
input multiplexer, which often results in an improved system
signal-to-noise ratio.
The PGA following the input multiplexer allows independent
selectable gains for each channel from 0 to 22.5 dB in +1.5 dB
steps. The Codec can operate either in a global stereo mode or
in a global mono mode with left-channel inputs appearing at
both channel outputs.
Analog-to-Digital DatapathThe AD1849K ∑Δ ADCs incorporate a proprietary fourth-order
modulator. A single pole of passive filtering is all that is required
for anti-aliasing the analog input because of the ADC’s high 64
times oversampling ratio. The ADCs include linear-phase digital
decimation filters that low-pass filter the input to 0.45 × FS
(“FS” is the word rate or “sampling frequency”). ADC input
overrange conditions will cause a sticky bit to be set that can be
read.
Digital-to-Analog DatapathThe ∑Δ DACs are preceded by a programmable attenuator and
a low-pass digital interpolation filter. The attenuator allows
independent control of each DAC channel from 0 dB to –94.5dB
in 1.5 dB steps plus full digital mute. The anti-imaging inter-
polation filter oversamples by 64 and digitally filters the higher
frequency images. The DACs’ ∑Δ noise shapers also oversample
by 64 and convert the signal to a single-bit stream. The DAC
outputs are then filtered in the analog domain by a combination
of switched-capacitor and continuous-time filters. They remove
the very high frequency components of the DAC bitstream
output, including both images at the oversampling rate and
shaped quantization noise. No external components are required.
Phase linearity at the analog output is achieved by internally
compensating for the group delay variation of the analog output
filters.
Attenuation settings are specified by control bits in the data
stream. Changes in DAC output level take effect only on zero
crossings of the digital signal, thereby eliminating “zipper”
noise. Each channel has its own independent zero-crossing
detector and attenuator change control circuitry. A timer
guarantees that requested volume changes will occur even in the
absence of an input signal that changes sign. The time-out
period is 10.7 milliseconds at a 48 kHz sampling rate and 64
Monitor MixA monitor mix is supported that digitally mixes a portion of the
digitized analog input with the analog output (prior to digitiza-
tion). The digital output from the ADCs going out of the serial
data port is unaffected by the monitor mix. Along the monitor
mix datapath, the 16-bit linear output from the ADCs is
attenuated by an amount specified with control bits. Both
channels of the monitor data are attenuated by the same
amount. (Note that internally the AD1849K always works with
16-bit PCM linear data, digital mixing included; format
conversions take place at the input and output.)
Sixteen steps of –6 dB attenuation are supported to –94.5 dB. A
“0” implies no attenuation, while a “14” implies 84 dB of
attenuation. Specifying full scale “15” completely mutes the
monitor datapath, preventing any mixing of the analog input
with the digital input. Note that the level of the mixed output
signal is also a function of the input PGA settings since they
affect the ADCs’ output.
The attenuated monitor data is digitally summed with the DAC
input data prior to the DACs’ datapath attenuators. Because
both stereo signals are mixed before the output attenuators, mix
data is attenuated a second time by the DACs’ datapath
attenuators. The digital sum of digital mix data and DAC input
data is clipped at plus or minus full scale and does not wrap
around.
Analog OutputsOne stereo line-level output, one stereo headphone output, and
one monaural (mono) speaker output are available at external
pins. Each of these outputs can be independently muted.
Muting either the line-level stereo output or the headphone
stereo output mutes both left and right channels of that output.
When muted, the outputs will settle to a dc value near
CMOUT, the midscale reference voltage. The mono speaker
output is differential. The chip can operate either in a global
stereo mode or in a global mono mode with left channel inputs
appearing at both outputs.
Digital Data TypesThe AD1849K supports four global data types: 16-bit twos-
complement linear PCM, 8-bit unsigned linear PCM, 8-bit
companded μ-law, and 8-bit companded A-law, as specified by
control register bits. Data in all four formats is always trans-
ferred MSB first. Sixteen-bit linear data output from the ADCs
and input to the DACs is in twos-complement format. Eight-bit
data is always left-justified in 16-bit fields; in other words, the
MSBs of all data types are always aligned; in yet other words,
full-scale representations in all three formats correspond to
equivalent full-scale signals. The eight least-significant bit
positions of 8-bit linear and companded data in 16-bit fields are
ignored on input and zeroed on output.
The 16-bit PCM data format is capable of representing 96 dB of
dynamic range. Eight-bit PCM can represent 48 dB of dynamic
range. Companded μ-law and A-law data formats use nonlinear
coding with less precision for large-amplitude signals. The loss
of precision is compensated for by an increase in dynamic range
to 64 dB and 72 dB, respectively.
On input, 8-bit companded data is expanded to an internal
linear representation, according to whether μ-law or A-law was
specified in the Codec’s internal registers. Note that when μ-law
compressed data is expanded to a linear format, it requires 14
bits. A-law data expanded requires 13 bits, see Figure 1.
3/22/1000DAC INPUT
EXPANSION
COMPRESSED
INPUT DATA
3/22/1
8 7Figure 1. A-Law or μ-Law Expansion
When 8-bit companding is specified, the ADCs’ linear output is
compressed to the format specified prior to output. See Figure 2.
Note that all format conversions take place at input or output.
Internally, the AD1849K always uses 16-bit linear PCM
representations to maintain maximum precision.
3/22/1000
ADC OUTPUT
TRUNCATION
COMPRESSION
8 7Figure 2.A-Law or μ-Law Compression
Power Supplies and Voltage ReferenceThe AD1849K operates from +5 V power supplies.Independent
analog and digital supplies are recommended for optimal
performance, though excellent results can be obtained in single
supply systems. A voltage reference is included on the Codec
and its 2.25 V buffered output is available on an external pin
(CMOUT). The CMOUT output can be used for biasing op
amps used in dc coupling. The internal reference is externally
bypassed to analog ground at the VREF pin. Note that VREF
should only be connected to its bypass capacitors.
AutocalibrationThe AD1849K supports an autocalibration sequence to eliminate
DAC and ADC offsets. The autocalibration sequence is
initiated in the transition from Control Mode to Data Mode,
regardless of the state of the AC bit. The user should specify
that analog outputs be muted to prevent undesired outputs.
Monitor mix will be automatically disabled by the Codec.
During the autocalibration sequence, the serial data output from
the ADCs is meaningless and the ADI bit is asserted. Serial data
inputs to the DACs are ignored. Even if the user specified the
muting of all analog outputs, near the end of the autocalibration
sequence, dc analog outputs very close to CMOUT will be
produced at the line outputs and mono speaker output.
An autocalibration sequence is also performed when the
AD1849K leaves the reset state (i.e., RESET goes HI). The
RESET pin should be held LO for 50 ms after power up or after
leaving power-down mode to delay the onset of the autocalibration
sequence until after the voltage reference has settled.
LoopbackDigital and analog loopback modes are supported for device and
system testing. The monitor mix datapath is always available for
loopback test purposes. Additional loopback tests are enabled by
setting the ENL bit (Control Word Bit 33) to a “1.”
Analog loopback mode D-A-D is enabled by setting the ADL
bit (Control Word Bit 32) to a “1” when ENL is a “1.” In this
mode, the DACs’ analog outputs are re-input to the PGAs prior
to the ADCs, allowing digital inputs to be compared to digital
outputs. The monitor mix will be automatically disabled by the
Codec during D-A-D loopback. The analog outputs can be
individually attenuated, and the analog inputs are internally
disconnected. Note that muting the line 0 output mutes the
looped-back signal in this mode.
Digital loopback mode D-D is enabled by resetting the ADL bit
(Control Word Bit 32) to a “0” when ENL is a “1.” In this
mode, the control and data bit pattern presented on the SDRX
pin is echoed on the SDTX pin with a two frame delay, allowing
the host controller to verify the integrity of the serial interface
starting on the third frame after D-D loopback is enabled.
During digital loopback mode, the output DACs are
operational.
AD1849KThe loopback modes are shown graphically in Figure 3.
GAIN
MONITOR
DISABLE
AD1849K
LINE, MIC
INPUT
DISCONNECTED
FUNCTIONAL
SDTX
SDRX
LINE 0
LINE 1
OUTPUT
A/Dµ/A-LAW
ENCODE
DECODEAD1849K Analog Loopback D-A-D
LINE, MIC
INPUT
SDTX
SDRXLINE 0,
LINE 1
OUTPUT
FUNCTIONALAD1849K Digital Loopback D-D
Figure 3.AD1849K Loopback Modes
Clocks and Sample RatesThe AD1849K can operate from external crystals, from a 256 ×
FS input clock, from an input clock with a programmable divide
factor, or from the serial port’s bit clock (at 256 × FS), selected
under software control. Two crystal inputs are provided to
generate a wide range of sample rates. The oscillators for these
crystals are on the AD1849K, as is a multiplexer for selecting
between them. They can be overdriven with external clocks by
the user, if so desired. The recommended crystal frequencies are
16.9344 MHz and 24.576 MHz. From them the following sample
rates can be internally generated: 5.5125, 6.615, 8, 9.6, 11.025,
16, 18.9, 22.05, 27.42857, 32, 33.075, 37.8, 44.1, 48kHz.
Regardless of clock input source, a clock output of 256 × FS is
generated (with some skew). If an external input clock or the
serial port’s bit clocks are selected to drive the AD1849K’s
internal operation, they should be low jitter clocks. If no
external clock will be used, Analog Devices recommends tying
the clock input pin (CLKIN) to ground. If either external
crystal is not used, Analog Devices recommends tying its input
(CIN1 and/or CIN2) to ground.
CONTROL REGISTERSThe AD1849K SoundPort Stereo Codec accepts control information through its serial port when in Control Mode. Some control
information is also embedded in the data stream when in Data Mode. (See Figure 8.) Control bits can also be read back for system
verification. Operation of the AD1849K is determined by the state of these control bits. The 64-bit serial Control Mode and Data
Mode control registers have been arbitrarily broken down into bytes for ease of description. All control bits initialize to default states
after RESET or Power Down. Those control bits that cannot be changed in Control Mode are initialized to defaults on the transition
from Data Mode to Control Mode. See below for a definition of these defaults.
Control Mode Control Registers
Control Byte 1, Status Register
Data 7Data 6Data 5Data 4Data 3Data 2Data 1Data 062616059585756Mic bypass:Mic inputs applied to +20 dB fixed gain block.Mic inputs bypass +20 dB fixed gain block.
OLBOutput level bit:Full-scale line 0 output is 2.8 V p-p (1 V rms).
Full-scale line 1 output is 4.0 V p-p.
Full-scale mono speaker output is 8.0 V p-p.Full-scale line 0 output is 2.0 V p-p.
Full-scale line 1 output is 2.0 V p-p.
Full-scale mono speaker output is 4.0 V p-p.
DCBData/control bit. Used for handshaking in data/control transitions. See “DCB Handshake Protocol.”Autocalibration.
Autocalibration will always occur on the Control-to-Data mode transition. The AC bit is ignored. Autocalibration
requires an interval of 194 frames. Offsets for all channels of ADC and DAC are zeroed. The user should specify that
analog outputs are muted to prevent undesired outputs, i.e., OM0 = “0,” OM1 = “0,” and SM =“0.” Monitor mix will
be automatically disabled by the Codec.
AD1849K
Control Byte 2, Data Format Register
Data 7Data 6Data 5Data 4Data 3Data 2Data 1Data 054535251504948
DFR2:0Data conversion frequency (FS) select tin kHz):
DFRDivide FactorXTAL1 (24.576 MHz)XTAL2 (16.9344 MHz)307285.512515361611.02589627.4285718.97683222.05448N/A37.8384N/A44.15124833.07525609.66.615
Note that the AD1849K’s internal oscillators can be overdriven by external clock sources at the crystal input pins. If an
external clock source is used, it should be applied to the crystal input pin (CIN1 or CIN2), and the crystal output pin
(COUT1 or COUT2) should be left unconnected. The external clock source need not be at the recommended crystal
frequencies, and it will be divided down by the selected Divide Factor.Global stereo mode. Both converters are placed in the same mode.Mono mode. The left analog input appears at both ADC outputs. The left digital input appears at both DAC outputs.Stereo mode
DF1:0Codec data format selection:16-bit twos-complement PCM linear8-bit μ-law companded8-bit A-law companded8-bit unsigned PCM linear
Control Byte 3, Serial Port Control Register
Data 7Data 6Data 5Data 4Data 3Data 2Data 1Data 046454443424140
ITSImmediate three-state:FSYNC, SDTX and SCLK three-state within 3 SCLK cycles after D/C goes LOFSYNC, SDTX and SCLK three-state immediately after D/C goes LO
MCK2:0Clock source select for Codec internal operation:Serial bit clock (SCLK) is the master clock at 256 × FS24.576 MHz crystal (XTAL1) is the clock source16.9344 MHz crystal (XTAL2) is the clock sourceExternal clock (CLKIN) is the clock source at 256 × FSExternal clock (CLKIN) is the clock source, divided by the factor selected by DFR2:0
(External clock must be stable and valid within 2000 periods after it is selected.)
FSEL1:0Frame size select:64 bits per frame128 bits per frame256 bits per frameReserved
Note that FSEL is overridden in Data Mode when SCLK is the clock source (MCK = “0”). When SCLK is
providing the 256 × FS clock for internal Codec operation, 256 bits per frame is effectively selected, regardless of
FSEL’s contents.Master/slave mode for the serial interface:0Receive serial clock (SCLK) and TSIN from an external device (“slave mode”)1Transmit serial clock (SCLK) and frame sync (FSYNC) to external devices (“master mode”)
Note that MS is overridden when SCLK is the clock source (MCK = “0”). When SCLK is providing the clock for
Control Byte 4, Test Register
Data 7Data 6Data 5Data 4Data 3Data 2Data 1Data 038373635343332
ENLEnable loopback testing:DisabledEnabled
ADLLoopback mode:Digital loopback from Data/Control receive to Data/Control transmit (D-D)Analog loopback from DACs to ADCs (D-A-D)
Control Byte 5, Parallel Port Register
Data 7Data 6Data 5Data 4Data 3Data 2Data 1Data 030292827262524
PIO1:0Parallel I/O bits for system signaling. PIO bits do not affect Codec operation.
Control Byte 6, Reserved Register
Data 7Data 6Data 5Data 4Data 3Data 2Data 1Data 022212019181716
Reserved bits should be written as 0.
Control Byte 7, Revision Register
Data 7Data 6Data 5Data 4Data 3Data 2Data 1Data 0141312111098
REVID3:0Silicon revision identification. Reads greater than or equal to 0010 (i.e., 0010, 0011, etc.) for the AD1849K.
Control Byte 8, Reserved Register
Data 7Data 6Data 5Data 4Data 3Data 2Data 1Data 0Reserved bits should be written as 0.
AD1849K
Data Mode Data and Control Registers
Data Byte 1, Left Audio Data—Most Significant 8 Bits
Data 7Data 6Data 5Data 4Data 3Data 2Data 1Data 062616059585756
In 16-bit linear PCM mode, this byte contains the upper eight bits of the left audio data sample. In the 8-bit companded and linear
modes, this byte contains the left audio data sample. In mono mode, only the left audio data is used. MSB first format is used in all
modes, and twos-complement coding is used in 16-bit linear PCM mode.
Data Byte 2, Left Audio Data—Least Significant 8 Bits
Data 7Data 6Data 5Data 4Data 3Data 2Data 1Data 054535251`504948
In 16-bit linear PCM mode, this byte contains the lower eight bits of the left audio data sample. In the 8-bit companded and linear
modes, this byte is ignored on input, zeroed on output. In mono mode, only the left audio data is used. MSB first format is used in
all modes, and twos-complement coding is used in 16-bit linear PCM mode.
Data Byte 3, Right Audio Data—Most Significant 8 Bits
Data 7Data 6Data 5Data 4Data 3Data 2Data 1Data 046454443424140
In 16-bit linear PCM mode, this byte contains the upper eight bits of the right audio data sample. In the 8-bit companded and linear
modes, this byte contains the right audio data sample. In mono mode, this byte is ignored on input, zeroed on output. MSB first
format is used in all modes, and twos complement coding is used in 16-bit linear PCM mode.
Data Byte 4, Right Audio Data—Least Significant 8 Bits
Data 7Data 6Data 5Data 4Data 3Data 2Data 1Data 038373635343332
In 16-bit linear PCM mode, this byte contains the lower eight bits of the right audio data sample. In the 8-bit companded and linear
modes, this byte is not used. In mono mode, this byte is ignored on input, zeroed on output. MSB first format is used in all modes,
and twos-complement coding is used in 16-bit linear PCM mode.
Data Byte 5, Output Setting Register 1
Data 7Data 6Data 5Data 4Data 3Data 2Data 1Data 030292827262524
OM1Output Line 1 Analog Mute:Mute Line 1Line 1 on
OM0Output Line 0 Analog Mute:Mute Line 0Line 0 on
LO5:0Output attenuation setting for the left DAC channel; “0” represents no attenuation. Step size is 1.5 dB; “62” represents
