AD1847JP ,Serial-Port 16-Bit SoundPort Stereo CodecOVERVIEW® line #1, and post-mixed DAC output. A software-controlledThe AD1847 SoundPort Stereo Code ..
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AD1849KPZ , Serial-Port 16-Bit SoundPort® Stereo Codec
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AD1847JP-AD1847JST
Serial-Port 16-Bit SoundPort Stereo Codec
REV.B
Serial-Port 16-Bit
SoundPort Stereo Codec
FEATURES
Single-Chip Integrated SD Digital Audio Stereo Codec
Supports the Microsoft Windows Sound System*
Multiple Channels of Stereo Input
Analog and Digital Signal Mixing
Programmable Gain and Attenuation
On-Chip Signal Filters
Digital Interpolation and Decimation
Analog Output Low-Pass
Sample Rates from 5.5 kHz to 48 kHz
44-Lead PLCC and TQFP Packages
Operation from +5 V Supplies
Serial Digital Interface Compatible with ADSP-21xx
Fixed-Point DSPFigure 1.Example System Diagram
External circuit requirements are limited to a minimal number
of low cost support components. Anti-imaging DAC output
filters are incorporated on-chip. Dynamic range exceeds 70 dB
over the 20 kHz audio band. Sample rates from 5.5 kHz to
48 kHz are supported from external crystals.
The Codec includes a stereo pair of ∑Δ analog-to-digital con-
verters (ADCs) and a stereo pair of ∑Δ digital-to-analog con-
verters (DACs). Inputs to the ADC can be selected from four
stereo pairs of analog signals: line 1, line 2, auxiliary (“aux”)
line #1, and post-mixed DAC output. A software-controlled
programmable gain stage allows independent gain for each
channel going into the ADC. The ADCs’ output can be digitally
mixed with the DACs’ input.
The pair of 16-bit outputs from the ADCs is available over a se-
rial interface that also supports 16-bit digital input to the DACs
and control/status information. The AD1847 can accept and
generate 16-bit twos-complement PCM linear digital data, 8-bit
unsigned magnitude PCM linear data, and 8-bit μ-law or A-law
companded digital data.
(Continued on page 7)
FUNCTIONAL BLOCK DIAGRAM
PRODUCT OVERVIEWThe AD1847 SoundPort® Stereo Codec integrates key audio
data conversion and control functions into a single integrated
circuit. The AD1847 is intended to provide a complete, low
cost, single-chip solution for business, game audio and multi-
media applications requiring operation from a single +5 V sup-
ply. It provides a serial interface for implementation on a
computer motherboard, add-in or PCMCIA card. See Figure 1
for an example system diagram.
*Windows Sound System is a registered trademark of Microsoft Corp.
SoundPort is a registered trademark of Analog Devices, Inc.
STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTEDTemperature25°CDAC Output Conditions
Digital Supply (VDD)5.0V0 dB Attenuation
Analog Supply (VCC)5.0VFull-Scale Digital Inputs
Word Rate (FS )48kHz16-Bit Linear Mode
Input Signal1007HzNo Output Load
Analog Output Passband20Hz to 20 kHzMute Off
FFT Size4096ADC Input Conditions
VIH2.4V0 dB Gain
VIL0.8V–3.0 dB Relative to Full Scale
VOH2.4VLine Input
VOL0.4V16-Bit Linear Mode
ANALOG INPUT
PROGRAMMABLE GAIN AMPLIFIER—ADCStep Size (All Steps Tested, –30 dB Input)
AUXILIARY INPUT ANALOG AMPLIFIERS/ATTENUATORS
DIGITAL DECIMATION AND INTERPOLATION FILTERS†Passband
AD1847–SPECIFICATIONS
ANALOG-TO-DIGITAL CONVERTERS
DIGITAL-TO-ANALOG CONVERTERSResolution
Dynamic Range (–60 dB Input, THD+N Referenced to Full Scale, A-Weighted)
THD+N (Referenced to Full Scale)
Signal-to-Intermodulation Distortion†
Gain Error (Full-Scale Span Relative to VREFI)
Interchannel Gain Mismatch (Difference of Gain Errors)
DAC Crosstalk† (Input L, Zero R, Measure R_OUT; Input R, Zero L, Measure L_OUT)
Total Out-of-Band Energy† (Measured from 0.6 3 FS to 100 kHz)
DAC ATTENUATOR
DIGITAL MIX ATTENUATOR
ANALOG OUTPUTFull-Scale Line Output Voltage
VREF Current Drive
AD1847
AD1847
SYSTEM SPECIFICATIONSSystem Frequency Response†
Differential Nonlinearity†
STATIC DIGITAL SPECIFICATIONSHigh Level Output Voltage (VOH) IOH = 1 mA
TIMING PARAMETERS (Guaranteed Over Operating Temperature Range)Serial Frame Sync Period (t1)
Data Input Hold Time (tH)15
Clock to Output Data Valid (tDV)
Clock to Output Three-State [High-Z] (tHZ)20
POWER SUPPLY
CLOCK SPECIFICATIONS†Input Clock Frequency
Recommended Clock Duty Cycle
Initialization/Sample Rate Change Time
ABSOLUTE MAXIMUM RATINGS**Stresses greater than those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE*P = PLCC; ST = TQFP.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1847 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
44-Lead PLCC44-Lead TQFP
PINOUTS
AD1847
PIN DESCRIPTIONS
Parallel Interface
Analog Signals
MiscellaneousL_FILT
R_FILT
Power SuppliesGNDA
VDD
(Continued from page 1)
The ∑Δ DACs are preceded by a digital interpolation filter. An
attenuator provides independent user volume control over each
DAC channel. Nyquist images are removed from the DACs’
analog stereo output by on-chip switched-capacitor and
continuous-time filters. Two stereo pairs of auxiliary line-level
inputs can also be mixed in the analog domain with the DAC
output.
The AD1847 serial data interface uses a Time Division Multi-
plex (TDM) scheme that is compatible with DSP serial ports
configured in Multi-Channel Mode with 32 16-bit time slots
(i.e., SPORT0 on the ADSP-2101, ADSP-2115, etc.).
AUDIO FUNCTIONAL DESCRIPTIONThis section overviews the functionality of the AD1847 and is
intended as a general introduction to the capabilities of the de-
vice. As much as possible, detailed reference information has
been placed in “Control Registers” and other sections. The user
is not expected to refer repeatedly to this section.
Analog InputsThe AD1847 SoundPort Stereo Codec accepts stereo line-level
inputs. All inputs should be capacitively coupled (ac-coupled) to
the AD1847. LINE1, LINE2, and AUX1, and post-mixed DAC
output analog stereo signals are multiplexed to the internal pro-
grammable gain amplifier (PGA) stage.
The PGA following the input multiplexer allows independent
Analog MixingAUX1 and AUX2 analog stereo signals can be mixed in the ana-
log domain with the DAC output. Each channel of each auxil-
iary analog input can be independently gained/attenuated from
+12 dB to –34.5 dB in –1.5 dB steps or completely muted. The
post-mixed DAC output is available on L_OUT and R_OUT
externally and as an input to the ADCs.
Even if the AD1847 is not playing back data from its DACs, the
analog mix function can still be active.
Analog-to-Digital DatapathThe ∑Δ ADCs incorporate a proprietary fourth-order modula-
tor. A single pole of passive filtering is all that is required for
antialiasing the analog input because of the ADC’s high 64
times oversampling ratio. The ADCs include digital decimation
filters that low-pass filter the input to 0.4 3 FS. (“FS’’ is the
word rate or “sampling frequency.”) ADC input overrange con-
ditions will cause status bits to be set that can be read.
Digital-to-Analog DatapathThe ∑Δ DACs contain a programmable attenuator and a low-
pass digital interpolation filter. The anti-imaging interpolation
filter oversamples and digitally filters the higher frequency im-
ages. The attenuator allows independent control of each DAC
channel from 0 dB to –94.5 dB in 1.5 dB steps plus full mute.
The DACs’ ∑Δ noise shapers also oversample and convert the
signal to a single-bit stream. The DAC outputs are then filtered
in the analog domain by a combination of switched-capacitor
AD1847Changes in DAC output attenuation take effect only on zero
crossings of the digital signal, thereby eliminating “zipper” noise
on playback. Each channel has its own independent zero-crossing
detector and attenuator change control circuitry. A timer guar-
antees that requested volume changes will occur even in the ab-
sence of an input signal that changes sign. The time-out period
is 8 milliseconds at a 48 kHz sampling rate and 48 milliseconds
at an 8 kHz sampling rate. (Time-out [ms] ≈ 384/FS [kHz]).
Digital MixingStereo digital output from the ADCs can be mixed digitally with
the input to the DACs. Digital output from the ADCs going out
of the serial data port is unaffected by the digital mix. Along the
digital mix datapath, the 16-bit linear output from the ADCs is
attenuated by an amount specified with control bits. Both chan-
nels of the monitor data are attenuated by the same amount.
(Note that internally the AD1847 always works with 16-bit
PCM linear data, digital mixing included; format conversions
take place at the input and output.)
Sixty-four steps of –1.5 dB attenuation are supported to
–94.5 dB. The digital mix datapath can also be completely
muted, preventing any mixing of the digital input with the digi-
tal output. Note that the level of the mixed signal is also a func-
tion of the input PGA settings, since they affect the ADCs’
output.
The attenuated digital mix data is digitally summed with the
DAC input data prior to the DACs’ datapath attenuators. The
digital sum of digital mix data and DAC input data is clipped at
plus or minus full scale and does not wrap around. Because
both stereo signals are mixed before the output attenuators, mix
data is attenuated a second time by the DACs’ datapath
attenuators.
Analog OutputsA stereo line-level output is available at external pins. Other
output types such as headphone and speaker must be imple-
mented in external circuitry. The stereo line-level outputs
should be capacitively coupled (ac-coupled) to the external cir-
cuitry. Each channel of this output can be independently
muted. When muted, the outputs will settle to a dc value near
VREF, the midscale reference voltage.
Digital Data TypesThe AD1847 supports four global data types: 16-bit twos-
complement linear PCM, 8-bit unsigned linear PCM,
companded μ-law, and 8-bit companded A-law, as specified by
control register bits. Eight-bit data is always left-justified in 16-
bit fields; in other words, the MSBs of all data types are always
aligned; in yet other words, full-scale representations in all four
formats correspond to equivalent full-scale signals. The eight
least significant bit positions of 8-bit data in 16-bit fields are ig-
nored on digital input and zoned on digital output (i.e., truncated).
The 16-bit PCM data format is capable of representing 96 dB of
dynamic range. Eight-bit PCM can represent 48 dB of dynamic
range. Companded μ-law and A-law data formats use nonlinear
coding with less precision for large-amplitude signals. The loss
of precision is compensated for by an increase in dynamic range
to 64 dB and 72 dB, respectively.
specified in the Codec’s internal registers. Note that when μ-law
compressed data is expanded to a linear format, it requires 14
bits. A-law data expanded requires 13 bits.
When 8-bit companding is specified, the ADCs’ linear output is
compressed to the format specified.
Note that all format conversions take place at input or output.
Internally, the AD1847 always uses 16-bit linear PCM represen-
tations to maintain maximum precision.
Power Supplies and Voltage ReferenceThe AD1847 operates from +5 V power supplies. Independent
analog and digital supplies are recommended for optimal perfor-
mance though excellent results can be obtained in single-supply
systems. A voltage reference is included on the Codec and its
2.25 V buffered output is available on an external pin (VREF).
The reference output can be used for biasing op amps used in
dc coupling. The internal reference must be externally bypassed
to analog ground at the VREFI pin, and must not be used to bias
external circuitry.
Clocks and Sample RatesThe AD1847 operates from two external crystals, XTAL1 and
XTAL2. The two crystal inputs are provided to generate a wide
range of sample rates. The oscillators for these crystals are on
the AD1847, as is a multiplexer for selecting between them.
They can be overdriven with external clocks by the user, if so
desired. At a minimum, XTAL1 must be provided since it is se-
lected as the reset default. If XTAL2 is not used, the XTAL2
input pin should be connected to ground. The recommended
crystal frequencies are 16.9344 MHz and 24.576 MHz. From
them, the following sample rates can be selected: 5.5125, 6.615,
8, 9.6, 11.025, 16, 18.9, 22.05, 27.42857, 32, 33.075, 37.8,
44.1, 48 kHz.
CONTROL REGISTERS
Control Register MappingThe AD1847 has six 16-bit and thirteen 8-bit on-chip user-
accessible control registers. Control information is sent to the
AD1847 in the 16-bit Control Word. Status information is sent
from the AD1847 in the 16-bit Status Word. Playback Data and
Capture Data each have two 16-bit registers for the right and
left channels. Additional 8-bit Index Registers are accessed via
indirect addressing in the AD1847 Control Word. [Index Regis-
ters are reached with indirect addressing.] The contents of an
indirect addressed Index Register may be readback by the host
CPU or DSP (during the Status Word/Index Readback time
slot) by setting the Read Request (RREQ) bit in the Control
Word. Note that each 16-bit register is assigned its own time
slot, so that the AD1847 always consumes six 16-bit time slots.
Figure 4 shows the mapping of the Control Word, Status Word/
Index Readback and Data registers to time slots when TSSEL = 0.
TSSEL = 0 is used when the SDI and SDO pins are tied to-
gether (i.e., “1-wire” system). This configuration is efficient in
terms of component interconnect (one bidirectional wire for se-
rial data input and output), but inefficient in terms of time slot
usage (six slots consumed on single bidirectional Time Division
Multiplexed [TDM] serial bus). When TSSEL = 0, serial data
input to the AD1847 occurs sequentially with serial data output
from the AD1847 (i.e., Control Word, Left Playback and Right
Playback data is received on the SDI pin, then the Status Word/
lndex Readback, Left Capture and Right Capture data is trans-
mitted on the SDO pin).
Figure 4.Control Register Mapping with TSSEL = 0
Figure 5 shows the mapping of the Control Word, Status Word/
Index Readback and Data registers to time slots when TSSEL =
1. Note that the six 16-bit registers “share” three time slots.
TSSEL = 1 is used when the SDI and SDO pins are indepen-
dent inputs and output (i.e., “2-wire” system). This configura-
tion is inefficient in terms of component interconnect (two
unidirectional wires for serial data input and output), but effi-
cient in terms of time slot usage (three slots consumed on each
of two unidirectional TDM serial buses). When TSSEL = 1, se-
rial data input to the AD1847 occurs concurrently with serial
data output from the AD1847 (i.e., Control Word reception on
the SDI pin occurs simultaneously with Status Word/lndex
Readback transmission on the SDO pin).
Figure 5.Control Register Mapping with TSSEL = 1
An Index Register readback request to an invalid index address
(11, 14 and 15) will return the contents of the Status Word. At-
tempts to write to an invalid index address (11, 14 and 15) will
have no effect on the AD1847. As mentioned above, the RREQ
bit of the Control Word is used to request Status Word output
or Index Register readback output during either time slot 3
(TSSEL = 0) or time slot 0 (TSSEL = 1). RREQ is set for In-
dex Register readback output, and reset for Status Word output.
When Index Register readback is requested, the Index Readback
bit format is the same as the Control Word bit format. All status
bits are updated by the AD1847 before a new Control Word is
received (i.e., at frame boundaries). Thus, if TSSEL = 0 and
the Control Word written at slot 0 causes some status bits to
change, the change will show up in the Status Word transmitted
at slot 3 of the same sample.
AD1847
Control Word (16-Bit)
Data 15Data 14Data 13Data 12Data 11Data 10Data 9Data 8
Data 7Data 6Data 5Data 4Data 3Data 2Data 1Data 0DATA7:0Index Register Data. These bits are the data for the desired AD1847 Index Register referenced by the Index Address.
Written by the host CPU or DSP to the AD1847.
IA3:0Index Register Address. These bits define the indirect address of the desired AD1847 Index Register. Written by the host
CPU or DSP to the AD1847.
RREQRead Request. Setting this bit indicates that the current transfer is a request by the host CPU or DSP for readback of the
contents of the indirect addressed Index Register. When this bit is set (RREQ = HI), the AD1847 will not transmit its
Status Word in the following Status Word Index readback slot, but will instead transmit the data in the Index Register
specified by the Index Address. Although the Index Readback is transmitted in the following Status Word/Index
Readback time slot, the format of the Control Word is used (i.e., CLOR, MCE, RREQ and the Index Register Address
in the most significant byte, and the readback Index Register Data in the least significant byte). When this bit is reset
(RREQ = LO), the AD1847 will transmit its Status Word in the following Status Word Index Readback time slot.
A read request is serviced in the next available Index Readback time slot. If TSSEL = 0, the Index Register readback
data is transmitted in slot 3 of the same sample. If TSSEL = 1, Index Register readback data is transmitted in slot 0 of
the next sample. If TSSEL changes from 0 to 1, Index Register readback will occur twice, in slot 3 of the current sample,
and slot 0 of the next. If TSSEL changes from 1 to 0, the last read request is lost.
resReserved for future expansion. Write zeros (LO) to all reserved bits.
MCEMode Change Enable. This bit must be set (MCE = HI) whenever protected control register bits of the AD1847 are
changed. The Data Format register, the Miscellaneous Information register, and the ACAL bit of the Interface Configu-
ration register can NOT be changed unless this bit is set. The DAC outputs will be muted when MCE is set. The user
must mute the AUX1 and AUX2 channels when this bit is set (no audio activity should occur). Written by the host CPU
or DSP to the AD1847. This bit is HI after reset.
CLORClear Overrange. When this bit is set (CLOR = HI), the overrange bits in the Status Word are updated every sample.
When this bit is reset (CLOR = LO), the overrange bits in the Status Word will record the largest overrange value. The
largest overrange value is sticky until the CLOR bit is set. Written by the host CPU or DSP to the AD1847. Since there
can be up to 2 samples in the data pipeline, a change to CLOR may take up to 2 samples periods to take effect. This bit
is HI after reset.
Immediately after reset, the contents of this register is: 1100 0000 0000 0000 (C000h).
Left/Right Playback/Capture Data (16-Bit)The data formats for Left Playback, Right Playback, Left Capture and Right Capture are all identical.
Data 15Data 14Data 13Data 12Data 11Data 10Data 9Data 8
Data 7Data 6Data 5Data 4Data 3Data 2Data 1Data 0DATA15:0Data Bits. These registers contain the 16-bit, MSB first data for capture and playback. The host CPU or DSP reads the
capture data from the AD1847. The host CPU or DSP writes the playback data to the AD1847. For 8-bit linear or 8-bit
companded modes, only DATA15:8 contain valid data; DATA7:0 are ignored during capture, and are zeroed during
playback. Mono mode plays back the same audio sample on both left and right channels. Mono capture only captures
data from the left audio channel. See “Serial Data Format” Timing Diagram.
Immediately after reset, the content of these registers is: 0000 0000 0000 0000 (0000h).
Status Word (16-Bit)
Data 15Data 14Data 13Data 12Data 11Data 10Data 9Data 8
Data 7Data 6Data 5Data 4Data 3Data 2Data 1Data 0INITInitialization. This bit is an indication to the host that frame syncs will stop and the serial bus will be shut down. INIT is
set HI on the last valid frame. It is reset LO for all other frames. Read by the host CPU or DSP from the AD1847.
The INIT bit is set HI on the last sample before the serial interface is inactivated. The only condition under which the
INIT bit is set is when a different sample rate is programmed. If FRS = 0 (32 slots per frame, two samples per frame)
and the sample rate is changed in the first sample of the 32 slot frame (i.e., during slots 0 through 15), the INIT bit will
be set on the second sample of that frame (i.e., during slots 16 through 31). If FRS = 0 and the sample rate is changed in
the second sample of the 32 slot frame, the INIT bit will be set on the second sample of the following frame.
ACIAutocalibrate In-Progress. This bit indicates that autocalibration is in progress or the Mode Change Enable (MCE) state
has been recently exited. When exiting the MCE state with the ACAL bit set, the ACI bit will be set HI for 384 sample
periods. When exiting the MCE state with the ACAL bit reset, the ACAL bit will be set HI for 128 sample periods, indi-
cating that offset and filter values are being restored. Read by the host CPU or DSP from the AD1847.Autocalibration not in progressAutocalibration is in progress
ACI clear (i.e., reset or LO) should be recognized by first polling for a HI on the sample after the MCE bit is reset, and
then polling for a LO. Note that it is important not to start polling until one sample after MCE is reset, because if MCE
is set while ACI is HI, an ACI LO on the following sample will suggest a false clear of ACI.
ORL1:0Overrange Left Detect. These bits indicate the overrange on the left input channel. Read by the host CPU or DSP from
the AD1847.Greater than –1.0 dB underrangeBetween –1.0 dB and 0 dB underrangeBetween 0 dB and 1.0 dB overrangeGreater than 1.0 dB overrange
ORR1:0Overrange Right Detect. These bits indicate the overrange on the right input channel. Read by the host CPU or DSP
from the AD1847.Greater than –1.0 dB underrangeBetween –1.0 dB and 0 dB underrangeBetween 0 dB and 1.0 dB overrangeGreater than 1.0 dB overrange
ID3:0AD1847 Revision ID. These four bits define the revision level of the AD1847. The first version of the AD1847 is desig-
nated ID = 0001. Read by the host CPU or DSP from the AD1847.
RREQThis bit is reset LO for the Status Word, echoing the RREQ state written by the host CPU or DSP in the previous Con-
trol Word. Read by the host CPU or DSP from the AD1847.
resReserved for future expansion. All reserved bits read zero (LO).
Immediately after reset, the contents of this register is: 0000 0001 0000 0000 (0100h).
AD1847
Index Readback (16-Bit)
Data 15Data 14Data 13Data 12Data 11Data 10Data 9Data 8
Data 7Data 6Data 5Data 4Data 3Data 2Data 1Data 0DATA7:0Index Register Data. These bits are the readback data from the desired AD1847 Index Register referenced by the Index
Address from the previous Control Word (with the RREQ bit set). Read by the host CPU or DSP from the AD1847.
IA3:0Index Register Address. These bits echo the indirect address (written during the previous Control Word (with the RREQ
bit set) of the desired AD1847 Index Register to be readback. Read by the host CPU or DSP from the AD1847.
RREQRead Request. This bit is set HI for Index Readback, echoing the RREQ state written by the host CPU or DSP in the
previous Control Word. Read by the host CPU or DSP from the AD1847.
resReserved for future expansion. All reserved bits read zero (LO).
MCEMode Change Enable. This bit echoes the MCE state written by the host CPU or DSP during the previous* Control
Word (with the RREQ bit set). Read by the host CPU or DSP from the AD1847.
CLORClear Overrange. This bit echoes the CLOR state written by the host CPU or DSP during the previous Control Word
(with the RREQ bit set). Read by the host CPU or DSP from the AD1847.
Immediately after reset, the contents of this register is: 1110 0000 0000 0000 (E000h).
Indirect Mapped RegistersFollowing in Figure 6 is a table defining the mapping of AD1847 8-bit Index Registers to Index Address. These registers are accessed
by writing the appropriate 4-bit Index Address in the Control Word.
Figure 6. Index Register Mapping
A detailed description of each of the Index Registers is given below.
Left Input Control Register (Index Address 0)
IA3:0Data 7Data 6Data 5Data 4Data 3Data 2Data 1 Data 0LIG3:0Left Input Gain Select. The least significant bit of this 16-level gain select represents +1.5 dB. Maximum gain is
+22.5 dB.
resReserved for future expansion. Write zeros (LO) to all reserved bits.
LSS1:0Left Input Source Select. These bits select the input source for the left gain stage preceding the left ADC.Left Line 1 Source SelectedLeft Auxiliary 1 Source SelectedLeft Line 2 Source SelectedLeft Line 1 Post-Mixed Output Loopback Source Selected
This register’s initial state after reset is: 0000 0000 (00h).
Right Input Control Register (Index Address 1)
IA3:0Data 7Data 6Data 5Data 4Data 3Data 2Data 1Data 0RIG3:0Right Input Gain Select. The least significant bit of this 16-level gain select represents +1.5 dB. Maximum gain is
+22.5 dB.
resReserved for future expansion. Write zeros (LO) to all reserved bits.
RSS1:0Right Input Source Select. These bits select the input source for the right gain stage preceding the right ADC.Right Line 1 Source SelectedRight Auxiliary 1 Source SelectedRight Line 2 Source SelectedRight Line 1 Post-Mixed Output Loopback Source Selected
This register’s initial state after reset is: 0000 0000 (00h).
Left Auxiliary #1 Input Control Register (Index Address 2)
IA3:0Data 7Data 6Data 5Data 4Data 3Data 2Data 1Data 0LX1G4:0Left Auxiliary Input #1 Gain Select. The least significant bit of this 32-level gain/attenuate select represents –1.5 dB.
LX1G4:0 = 0 produces a +12 dB gain. LX1G4:0 = “01000” (8 decimal) produces 0 dB gain. Maximum attenuation is
–34.5 dB. Gains referred to 2.0 V p-p full-scale output level.
resReserved for future expansion. Write zeros (LO) to all reserved bits.
LMX1Left Auxiliary #1 Mute. This bit, when set HI, will mute the left channel of the Auxiliary #1 input source. This bit is set
HI after reset.
This register’s initial state after reset is: 1000 0000 (80h).
Right Auxiliary #1 Input Control Register (Index Address 3)
IA3:0Data 7Data 6Data 5Data 4Data 3Data 2Data 1Data 0RX1G4:0Right Auxiliary Input #1 Gain Select. The least significant bit of this 32-level gain/attenuate select represents –1.5 dB.
RX1G4:0 = 0 produces a +12 dB gain. RX1G4:0 = “01000” (8 decimal) produces 0 dB gain. Maximum attenuation is
–34.5 dB. Gains referred to 2.0 V p-p full-scale output level.
resReserved for future expansion. Write zeros (LO) to all reserved bits.
AD1847
Left Auxiliary #2 Input Control Register (Index Address 4)
IA3:0Data 7Data 6Data 5Data 4Data 3Data 2Data 1Data 0LX2G4:0Left Auxiliary #2 Gain Select. The least significant bit of this 32-level gain/attenuate select represents –1.5 dB.
LX2G4:0 = 0 produces a +12 dB gain. LX2G4:0 = “01000” (8 decimal) produces 0 dB gain. Maximum attenuation is
–34.5 dB. Gains referred to 2.0 V p-p full-scale output level.
resReserved for future expansion. Write zeros (LO) to all reserved bits.
LMX2Left Auxiliary #2 Mute. This bit, when set HI, will mute the left channel of the Auxiliary #2 input source. This bit is HI
after reset.
This register’s initial state after reset is: 1000 0000 (80h).
Right Auxiliary #2 Input Control Register (Index Address 5)
IA3:0Data 7Data 6Data 5Data 4Data 3Data 2Data 1Data 0RX2G4:0Right Auxiliary #2 Gain Select. The least significant bit of this 32-level gain/attenuate select represents –1.5 dB.
RX2G4:0 = 0 produces a +12 dB gain. RX2G4:0 = “01000” (8 decimal) produces 0 dB gain. Maximum attenuation is
–34.5 dB. Gains referred to 2.0 V p-p full-scale output level.
resReserved for future expansion. Write zeros (LO) to all reserved bits.
RMX2Right Auxiliary #2 Mute. This bit, when set HI, will mute the right channel of the Auxiliary #2 input source. This bit is
HI after reset.
This register’s initial state after reset is: 1000 0000 (80h).
Left DAC Control Register (Index Address 6)
IA3:0Data 7Data 6Data 5Data 4Data 3Data 2Data 1Data 0LDA5:0Left DAC Attenuate Select. The least significant bit of this 64-level attenuate select represents –1.5 dB. LDA5:0 = 0 pro-
duces a 0 dB attenuation. Maximum attenuation is –94.5 dB.
resReserved for future expansion. Write zeros (LO) to all reserved bits.
LDMLeft DAC Mute. This bit, when set HI, will mute the left channel output. Auxiliary inputs are muted independently with
the Left Auxiliary Input Control Registers. This bit is HI after reset.
This register’s initial state after reset is: 1000 0000 (80h).
Right DAC Control Register (Index Address 7)
IA3:0Data 7Data 6Data 5Data 4Data 3Data 2Data 1Data 0RDA5:0Right DAC Attenuate Select. The least significant bit of this 64-level attenuate select represents –1.5 dB. RDA5:0 = 0
produces a 0 dB attenuation. Maximum attenuation must be at least –94.5 dB.
resReserved for future expansion. Write zeros (LO) to all reserved bits.
RDMRight DAC Mute. This bit, when set HI, will mute the right DAC output. Auxiliary inputs are muted independently with
the Right Auxiliary Input Control Registers. This bit is HI after reset.
This register’s initial state after reset is: 1000 0000 (80h).
