AD1846JP ,Low Cost Parallel-Port 16-Bit SoundPort Stereo CodecSPECIFICATIONSSTANDARD TEST CONDITIONS UNLESS OTHERWISE NOTEDDAC Output ConditionsPost-Autocalibrat ..
AD1847JP ,Serial-Port 16-Bit SoundPort Stereo CodecOVERVIEW® line #1, and post-mixed DAC output. A software-controlledThe AD1847 SoundPort Stereo Code ..
AD1847JST ,Serial-Port 16-Bit SoundPort Stereo CodecSerial-Port 16-BitaSoundPort Stereo CodecAD1847
AD1848KP ,Parallel-Port 16-Bit SoundPort Stereo CodecSPECIFICATIONSSTANDARD TEST CONDITIONS UNLESS DAC Input ConditionsOTHERWISE NOTED Post-Autocalibrat ..
AD1849KP ,Serial-Port 16-Bit SoundPort Stereo CodecFEATURES speaker and stereo headphone drive circuits that require noSingle-Chip Integrated SD Digit ..
AD1849KPZ , Serial-Port 16-Bit SoundPort® Stereo Codec
AD8307AR ,Low Cost DC-500 MHz, 92 dB Logarithmic AmplifierSpecifications subject to change without notice.–2– REV. AAD8307*Stresses above those listed under ..
AD8307AR-REEL ,Low Cost DC-500 MHz, 92 dB Logarithmic AmplifierAPPLICATIONSCOMMON COM COMConversion of Signal Level to Decibel FormOFSINPUT-OFFSETOFS. ADJ.COMPENS ..
AD8307AR-REEL7 ,Low Cost DC-500 MHz, 92 dB Logarithmic Amplifierapplications requiring the reduction of aEach of the cascaded amplifier/limiter cells has a small-s ..
AD8307ARZ-RL7 , Low Cost DC-500 MHz, 92 dB Logarithmic Amplifier
AD8309 ,5APPLICATIONSReceivers for Frequency and Phase ModulationVery Wide Range IF and RF Power Measurement ..
AD8309ARU ,5 MHz.500 MHz 100 dB Demodulating Logarithmic Amplifier with Limiter OutputSpecifications subject to change without notice.–2– REV. BAD8309ABSOLUTE MAXIMUM RATINGS*Operating ..
AD1846JP
Low Cost Parallel-Port 16-Bit SoundPort Stereo Codec
REV.
Low Cost Parallel-Port 16-Bit
SoundPort Stereo Codec
FEATURES
Low Cost, Pin- and Register-Compatible Alternative to
AD1848
Single-Chip Integrated ∑Δ Digital Audio Stereo Codec
Supports the Microsoft Windows Sound System*
Multiple Channels of Stereo Input and Output
Analog and Digital Signal Mixing
Programmable Gain and Attenuation
On-Chip Signal Filters
Digital Interpolation and Decimation
Analog Output Low-Pass
Sample Rates from 5.5 kHz to 48 kHz
68-Lead PLCC Package
Operation from +5 V Supply
Byte-Wide Parallel Interface to ISA and EISA Buses
Supports One or Two DMA Channels and
Programmed I/OIt provides a direct, byte-wide interface to both ISA (“AT”) and
EISA computer buses for simplified implementation on a com-
puter motherboard or add-in card. The AD1846 generates en-
able and direction controls for IC buffers such as the 74_245.
The AD1846 SoundPort Stereo Codec supports a DMA re-
quest/grant architecture for transferring data with the host com-
puter bus. One or two DMA channels can be supported.
Programmed I/O (PIO) mode is also supported for control reg-
ister accesses and for applications lacking DMA control. Two
input control lines support mixed direct and indirect addressing
of twenty-one internal control registers over this asynchronous
interface.
External circuit requirements are limited to a minimal number
of low cost support components. Anti-imaging DAC output
filters are incorporated on-chip. DAC dynamic range exceeds
80 dB over the 20 kHz audio band. Sample rates from 5.5 kHz
to 48 kHz are supported from external crystals.
The Codec includes a stereo pair of ∑Δ analog-to-digital con-
verters and a stereo pair of ∑Δ digital-to-analog converters. In-
puts to the ADC can be selected from four stereo pairs of analog
signals: line, microphone (“mic”), auxiliary (“aux”) line #1, and
post-mixed DAC output. A software-controlled programmable
gain stage allows independent gain for each channel going into
the ADC. The ADCs’ output can be digitally mixed with the
DACs’ input.
(Continued on page 9)
PRODUCT OVERVIEWThe Parallel-Port AD1846 SoundPort® Stereo Codec integrates
key audio data conversion and control functions into a single in-
tegrated circuit. The AD1846 is intended to provide a complete,
single-chip audio solution for business audio and multimedia
applications requiring operation from a single +5 V supply.
*Windows Sound System is a trademark of Microsoft Corp.
SoundPort is a registered trademark of Analog Devices, Inc.
FUNCTIONAL BLOCK DIAGRAM
AD1846–SPECIFICATIONS
STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTEDDAC Output Conditions
Post-Autocalibrated
Temperature25°C0 dB Attenuation
Digital Supply (VDD)5.0VFull Scale (0 dB)
Analog Supply (VCC)5.0V16-Bit Linear Mode
Word Rate (FS )48kHzNo Output Load
Input Signal1007HzMute Off
Analog Output Passband20 Hz to 20 kHzADC Input Conditions
FFT Size4096Post-Autocalibrated
VIH2.4V0 dB Gain
VIL0.8V–1.0 dB Relative to Full Scale
VOH2.4VLine Input
VOL0.4V16-Bit Linear Mode
Inputs Driven with Low Impedance (≈ 50 Ω) Source
ANALOG INPUT
PROGRAMMABLE GAIN AMPLIFIER—ADC
AUXILIARY INPUT ANALOG AMPLIFIERS/ATTENUATORS
DIGITAL DECIMATION AND INTERPOLATION FILTERS*Passband
ANALOG-TO-DIGITAL CONVERTERS
DIGITAL-TO-ANALOG CONVERTERS*Guaranteed Not Tested.
Specifications subject to change without notice.
AD1846
AD1846
DAC ATTENUATORStep Size (0 dB to –60 dB)
Step Size (–60 dB to –94.5 dB)*
ANALOG OUTPUTFull-Scale Output Voltage
Output Impedance*
External Load Impedance
Output Capacitance*
External Load Capacitance
VREF
VREF Current Drive
SYSTEM SPECIFICATIONSPeak-to-Peak Frequency Response Ripple*
Differential Nonlinearity*
STATIC DIGITAL SPECIFICATIONSLow Level Input Voltage (VIL)
High Level Output Voltage (VOH) at IOH = –2 mA
DIGITAL MIX ATTENUATORStep Size (0 dB to –94 dB)
TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE RANGE)Write Data Setup to WR Rising (tWDSU)10
Data Hold from RD Rising (tDHD1)0
POWER SUPPLYPower Dissipation – Power Down
Power Supply Rejection (100 mV p-p Signal @ 1 kHz)*
CLOCK SPECIFICATIONS*Input Clock Frequency
Recommended Clock Duty Cycle Tolerance
Initialization Time
*Guaranteed, not tested.
Specifications subject to change without notice.
AD1846
AD1846
ORDERING GUIDE
ABSOLUTE MAXIMUM RATINGS*
MinMaxUnitsPower Supplies
Digital (VDD)–0.36.0V
Analog (VCC)–0.36.0V
Input Current
(Except Supply Pins)±10.0mA
Analog Input Voltage (Signal Pins)–0.3(VCC) + 0.3V
Digital Input Voltage (Signal Pins)–0.3(VDD) + 0.3V
Ambient Temperature (Operating)0+70°C
Storage Temperature–65+150°C
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1846 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
68-Lead Plastic Leaded Chip Carrier Pinout
XCTL1
INT
XCTL0
VDD
GNDD
VDD
GNDD
ADR1
DATA0DATA1DATA2DATA3GNDD
DBDIRGNDDDATA4DATA5DATA6DATA7GNDDWRDBEN
ADR0
CDRQ
PDRQ
VDD
GNDD
XTAL1I
XTAL1O
GNDD
R_FILT
VDD
GNDD
XTAL2I
XTAL2O
VDD
PWRDWN
PDAK
CDAK
R_LINE
L_MIC
L_LINE
L_FILT
REF
(2.25V)
REF
_F (BYPASS)
GNDA
R_AUX1
R_MIC
GNDA
L_AUX2L_AUX1
L_OUT
R_AUX2
R_OUT
NC = NO CONNECT
PIN DESCRIPTION
Parallel InterfaceDBDIR
AD1846
Analog Signals
Miscellaneous
Power Supplies
(Continued from page 1)
Figure 1.Interface to ISA Bus
The pair of 16-bit outputs from the ADCs is available over a
byte-wide bidirectional interface that also supports 16-bit digital
input to the DACs and control information. The AD1846 can
accept and generate 16-bit twos-complement PCM linear digital
data, 8-bit unsigned magnitude PCM linear data, and 8-bit
μ-law or A-law companded digital data.
The ∑Δ DACs are preceded by a digital interpolation filter. An
attenuator provides independent user volume control over each
DAC channel. Nyquist images and shaped quantization noise
are removed from the DACs’ analog stereo output by on-chip
switched-capacitor and continuous-time filters. Two stereo pairs
of auxiliary line-level inputs can also be mixed in the analog do-
main with the DAC output.
AUDIO FUNCTIONAL DESCRIPTIONThis section overviews the functionality of the AD1846 and is
intended as a general introduction to the capabilities of the de-
vice. As much as possible, detailed reference information has
been placed in “Control Registers” and other sections. The user
is not expected to refer repeatedly to this section.
Analog InputsThe AD1846 SoundPort Stereo Codec accepts stereo line-level
and mic-level inputs. LINE, MIC, and AUX1 inputs and post-
mixed DAC output analog stereo signals are multiplexed to the
internal programmable gain amplifier (PGA) stage.
The PGA following the input multiplexer allows independent
selectable gains for each channel from 0 to 22.5 dB in +1.5 dB
steps. The Codec can operate either in a global stereo mode or
in a global mono mode with left channel inputs appearing at
both channel outputs.
Analog MixingAUX1 and AUX2 analog stereo signals can be mixed in the ana-
log domain with the DAC output. Each channel of each auxil-
iary analog input can be independently gained/attenuated from
+12 dB to –34.5 dB in –1.5 dB steps or completely muted. The
post mixed DAC output is available on OUT externally and as
an input to the ADCs.
Even if the AD1846 is not playing back data from its DACs, the
analog mix function can still be active.
Analog-to-Digital DatapathThe AD1846 ∑Δ ADCs incorporate a fourth order modulator.
A single pole of passive filtering is all that is required for anti-
aliasing the analog input because of the ADC’s high 64 times
oversampling ratio. The ADCs include linear phase digital deci-
mation filters that low-pass filter the input to 0.4 3 FS. (“FS’’ is
the word rate or “sampling frequency”). ADC input overrange
conditions will cause bits to be set that can be read.
Each channel of the mic inputs can be amplified digitally by
+18 dB to compensate for the voltage swing differences between
line levels and typical condenser microphone levels. This +18
dB digital gain is enabled with the same control bits (LMGE
and RMGE) as the +20 dB analog gain in the AD1848.
Digital-to-Analog DatapathThe ∑Δ DACs contain a programmable attenuator and a low-
pass digital interpolation filter. The anti-imaging interpolation
filter oversamples by 64 and digitally filters the higher frequency
images. The attenuator allows independent control of each
DAC channel from 0 dB to –94.5 dB in 1.5 dB steps plus full
mute. The DACs’ ∑Δ noise shapers also oversample by 64 and
convert the signal to a single bit stream. The DAC outputs are
then filtered in the analog domain by a combination of switched-
capacitor and continuous-time filters. They remove the very
high frequency components of the DAC bitstream output. No
external components are required. Phase linearity at the analog
output is achieved by internally compensating for the group
delay variation of the analog output filters.
Changes in DAC output attenuation take effect only on zero
crossings, thereby eliminating “zipper” noise. Each channel has
its own independent zero-crossing detector and attenuator
change control circuitry. A timer guarantees that requested vol-
ume changes will occur even in the absence of an input signal
that changes sign. The time-out period is 8 milliseconds at a
48 kHz sampling rate and 48 milliseconds at an 8 kHz sampling
rate. (Time out [ms] ≈ 384/FS [kHz].)
Digital MixingStereo digital output from the ADCs can be mixed digitally with
the input to the DACs. Digital output from the ADCs going out
of the data port is unaffected by the digital mix. Along the digi-
tal mix datapath, the 16-bit linear output from the ADCs is
attenuated by an amount specified with control bits. Both chan-
nels of the monitor data are attenuated by the same amount.
(Note that internally the AD1846 always works with 16-bit
PCM linear data, digital mixing included; format conversions
take place at the input and output.)
AD1846Sixty-four steps of –1.5 dB attenuation are supported to
–94.5 dB. The digital mix datapath can also be completely
muted, preventing any mixing of the analog input with the digi-
tal input. Note that the level of the mixed signal is also a func-
tion of the input PGA settings, since they affect the ADCs’
output.
The attenuated digital mix data is digitally summed with the
DAC input data prior to the DACs’ datapath attenuators. The
digital sum of digital mix data and DAC input data is clipped at
plus or minus full scale and does not wrap around. Because
both stereo signals are mixed before the output attenuators, mix
data is attenuated a second time by the DACs’ datapath
attenuators.
In case the AD1846 is capturing data but ADC output data is
not removed in time (“ADC overrun”), then the last sample
captured before overrun will be used for the digital mix. In case
the AD1846 is playing back data hut input digital DAC data
fails to arrive in time (“DAC underrun”), then a midscale zero
will be added to the digital mix data.
Analog OutputsA stereo line level output is available at external pins. Each
channel of this output can be independently muted. When
muted, the outputs will settle to a dc value near VREF, the
midscale reference voltage.
Digital Data TypesThe AD1846 supports four data types: 16-bit twos-complement
linear PCM, eight-bit unsigned linear PCM, companded μ-law,
and 8-bit companded A-law, as specified by control register bits.
Data in all four formats is always transferred MSB first. Stereo
data is always transferred in the left-right order. All data formats
that are less than 16 bits are properly aligned to insure the utili-
zation of full system resolution.
The 16-bit PCM data format is capable of representing 96 dB of
dynamic range. Eight-bit PCM can represent 48 dB of dynamic
range. Companded μ-law and A-law data formats use nonlinear
coding with less precision for large amplitude signals. The loss
of precision is compensated for by an increase in dynamic range
to 64 dB and 72 dB, respectively.
On input, 8-bit companded data is expanded to an internal lin-
ear representation, according to whether μ-law or A-law was
specified in the Codec’s internal registers. Note that when μ-law
compressed data is expanded to a linear format, it requires 14
bits. A-law data expanded requires 13 bits.
Figure 2.A-Law or μ-Law Expansion
When 8-bit companding is specified, the ADCs’ linear output is
compressed to the format specified.
Figure 3.A-Law or μ-Law Compression
Note that all format conversions take place at input or output.
Internally, the AD1846 always uses 16-bit linear PCM represen-
tations to maintain maximum precision.
Power Supplies and Voltage ReferenceThe AD1846 operates from +5 V power supplies. Independent
analog and digital supplies are recommended for optimal perfor-
mance though excellent results can be obtained in single supply
systems. A voltage reference is included on the Codec and its
2.25 V buffered output is available on an external pin (VREF).
The reference output can be used for biasing op amps used in
dc coupling. The internal reference must be externally bypassed
to analog ground at the VREF_F pin.
Clocks and Sample RatesThe AD1846 operates from external crystals. Two crystal inputs
are provided to generate a wide range of sample rates. The oscil-
lators for these crystals are on the AD1846, as is a multiplexer
for selecting between them. They can be overdriven with exter-
nal clocks by the user, if so desired. The recommended crystal
frequencies are 16.9344 MHz and 24.576 MHz. From them the
following sample rates are divided down: 5.5125, 6.615, 8, 9.6,
11.025, 16, 18.9, 22.05, 27.42857, 32, 33.075, 37.8, 44.1,
48 kHz.
IndexRegister Name
CONTROL REGISTERS
Control Register ArchitectureThe AD1846 SoundPort Stereo Codec accepts both data and
control information through its byte-wide parallel port. Indirect
addressing minimizes the number of external pins required to
access all 21 of its byte-wide internal registers. Only two exter-
nal address pins, ADR1:0, are required to accomplish all data
and control transfers. These pins select one of five direct regis-
ters. (ADR1:0 = 3 addresses two registers, depending on
whether the transfer is a playback or a capture.)
ADR1:0Register NameFigure 4.Direct Register Map
A write to or a read from the Indexed Data Register will access
the indirect register which is indexed by the value most recently
written to the Index Address Register. The Status Register and
the PIO Data Register are always accessible directly, without in-
dexing. The 16 indirect registers are indexed in Figure 5.
Direct Registers:
ADR1:0Data 7Data 6Data 5Data 4Data 3Data 2Data 1Data 0
Indirect Registers:
IXA3:0Data 7Data 6Data 5Data 4Data 3Data 2Data 1Data 0Figure 6.Register Summary
Note that the only sticky bit in any of the AD1846 control registers is the interrupt (INT) bit. All other bits change with every
sample period.
Figure 5.Indirect Register Map
A detailed map of all direct and indirect register contents is
summarized for reference as follows:
AD1846
Direct Control Register Definitions
Index Register (ADR1:0 = 0)
ADR1:0Data 7Data 6Data 5Data 4Data 3Data 2Data 1Data 0IXA3:0Index Address. These bits define the address of the AD1846 register accessed by the Indexed Data Register. These bits
are read/write.
resReserved for future expansion. Always write a zero to this bit.
TRDTransfer Request Disable. This bit, when set, causes all data transfers to cease when the Interrupt Status (INT) bit of the
Status Register is set.Transfers Enabled During Interrupt. PDRQ and CDRQ pin outputs are generated uninhibited by interrupts.
DMA Current Counter Register decrements with every sample period when either PEN or CEN are enabled.Transfers Disabled By Interrupt. PDRQ and CDRQ pin outputs are generated only if INT bit is 0 (when either
PEN or CEN, respectively, are enabled). Any pending playback or capture requests are allowed to complete at the
time when TRD is set. After pending requests complete, midscale inputs will be internally generated for the
DACs, and the ADC output buffer will contain the last valid output. Clearing the sticky INT bit (or the TRD bit)
will cause the resumption of playback and/or capture requests (presuming PEN and/or CEN are enabled). The
DMA Current Counter Register will not decrement while both the TRD bit is set and the INT bit is a one.
MCEMode Change Enable. This bit must be set whenever the current functional mode of the AD1846 is changed. Specifically,
the Clock and Data Format and Interface Configuration registers cannot be changed unless this bit is set. The exceptions
are CEN and PEN in the Interface Configuration which can be changed “on-the-fly.” MCE should be cleared at the com-
pletion of the desired register changes. The DAC outputs are automatically muted when the MCE bit is set. After MCE is
cleared, the DAC outputs will be restored to the state specified by the LDM and RDM mute bits.
Both ADCs and DACs are automatically muted for approximately 128 sample cycles after exiting the MCE state to allow
the reference and all filters to settle. The ADCs will produce midscale values; the DACs’ analog output will be muted. All
converters are internally operating during these ≈128 sample cycles, and the AD1846 will expect playback data and will
generate (midscale) capture data. Note that the autocalibrate-in-process (ACI) bit will be set on exit from the MCE state
regardless of whether or not ACAL was set. ACI will remain HI for these ≈128 sample cycles; system software should poll
this bit rather than count cycles.
Special sequences must be followed if autocalibrate (ACAL) is set or sample rates are changed (CFS2:0 and or CSS)
during mode change enable. See the “Autocalibration” and “Changing Sample Rates” sections below.
INITAD1846 Initialization. This bit is set when the AD1846 is in a state which cannot respond to parallel bus cycles. This bit
is read only.
Immediately after reset and once the AD1846 has left the INIT state, the initial value of this register will be “0100 0000 (40h).”
During AD1846 initialization, this register cannot be written to and will always read “100x 0000 (80h).”
Indexed Data Register (ADR1:0 = 1)
ADR1:0Data 7Data 6Data 5Data 4Data 3Data 2Data 1Data 0IXD7:0Indexed Register Data. These bits contain the contents of the AD1846 register referenced by the Indexed Data Register.
During AD1846 initialization, this register cannot be written to and will always read as “1000 0000 (80h).”
Status Register (ADR1:0 = 2)
ADR1:0Data 7Data 6Data 5Data 4Data 3Data 2Data 1Data 0INTInterrupt Status. This sticky bit (the only one) indicates the status of the interrupt logic of the AD1846. This bit is cleared
by any host write of any value to this register. The IEN bit of the Pin Control Register determines whether the state of this
bit is reflected on the INT pin of the AD1846. The only interrupt condition supported by the AD1846 is generated by the
underflow of the DMA Current Count Register.Interrupt pin inactiveInterrupt pin active
PRDYPlayback Data Register Ready. The PIO Playback Data Register is ready for more data. This bit should only be used when
direct programmed I/O data transfers are desired. This bit is read only.DAC data is still valid. Do not overwrite.DAC data is stale. Ready for next host data write value.
PL/RPlayback Left/Right Sample. This bit indicates whether the PIO playback data needed is for the right channel DAC or left
channel DAC. This bit is read only.Right channel neededLeft channel or mono
PU/LPlayback Upper/Lower Byte. This bit indicates whether the PIO playback data needed is for the upper or lower byte of the
channel. This bit is read only.Lower byte neededUpper byte needed or any 8-bit mode
SOURSample Over/Underrun. This bit indicates that the most recent sample was not serviced in time and therefore either a cap-
ture overrun (COR) or playback underrun (PUR) has occurred. The bit indicates an overrun for ADC capture and an
underrun for DAC playback. If both capture and playback are enabled, the source which set this bit can be determined by
reading COR and PUR. This bit changes on a sample-by-sample basis. This bit is read only.
CRDYCapture Data Ready. The PIO Capture Data Register contains data ready for reading by the host. This bit should only be
used when direct programmed I/O data transfers are desired. This bit is read only.ADC data is stale. Do not reread the information.ADC data is fresh. Ready for next host data read.
CL/RCapture Left/Right Sample. This bit indicates whether the PIO capture data waiting is for the right channel ADC or left
channel ADC. This bit is read only.Right channelLeft channel or mono
CU/LCapture Upper/Lower Byte. This bit indicates whether the PIO capture data ready is for the upper or lower byte of the
channel. This bit is read only.Lower byte readyUpper byte ready or any 8-bit mode
The PRDY, CRDY, and INT bits of this status register can change asynchronously to host accesses. The host may access this regis-
ter while the bits are transitioning. The host read may return a zero value just as these bits are changing, for example. A “1” value
would not be read until the next host access.
This registers’s initial state after reset is “1100 1100.”
AD1846
PIO Data Registers (ADR1:0 = 3)
ADR1:0Data 7Data 6Data 5Data 4Data 3Data 2Data 1Data 0The PIO Data Registers are two registers mapped to the same address. Writes send data to the PIO Playback Data Register (PD7:0).
Reads will receive data from the PIO Capture Data Register (CD7:0).
During AD1846 initialization, the PIO Playback Data Register cannot be written and the Capture Data Register is always read
“1000 0000 (80h).”
CD7:0PIO Capture Data Register. This is the control register where capture data is read during programmed I/O data transfers.
The reading of this register will increment the state machine so that the following read will be from the next appropriate
byte in the sample. The exact byte which is next to be read can be determined by reading the Status Register. Once all rel-
evant bytes have been read, the state machine will stay pointed to the last byte of the sample until a new sample is received
from the ADCs. Once this has occurred, the state machine and status register will point to the first byte of the sample.
Until a new sample is received, reads from this register will return the most significant byte of the sample.
PD7:0PIO Playback Data Register. This is the control register where playback data is written during programmed I/O data
transfers.
Writing data to this register will increment the playback byte tracking state machine so that the following write will be to
the correct byte of the sample. Once all bytes of a sample have been written, subsequent byte writes to this port are ig-
nored. The state machine is reset when the current sample is sent to the DACs.
Indirect Control Register DefinitionsThe following control registers are accessed by writing index values to IXA3:0 in the Index Address Register (ADR1:0 = 0) followed
by a read/write to the Indexed Data Register (ADR1:0 = 1).
Left Input Control (IXA3:0 = 0)
IXA3:0Data 7Data 6Data 5Data 4Data 3Data 2Data 1Data 0LIG3:0Left input gain select. The least significant bit of this gain select represents +1.5 dB. Maximum gain is +22.5 dB.
resReserved for future expansion. Always write a zero to this bit.
LMGELeft Input Microphone Gain Enable. Setting this bit will enable the +18 dB digital gain of the left mic input signal.
LSS1:0Left Input Source Select. These bits select the input source for the left gain stage preceding the left ADC.Left Line Source SelectedLeft Auxiliary 1 Source SelectedLeft Microphone Source SelectedLeft Line Post-Mixed DAC Output Source Selected
This register’s initial state after reset is “000x 0000.”
