AD1845JP ,Parallel-Port 16-Bit SoundPort Stereo CodecFEATURESplete on-chip filtering, MPC Level-2 compliant analog mixing,Single-Chip Integrated ∑Δ Digi ..
AD1845JP-REEL ,Parallel-Port 16-Bit SoundPort Stereo CodecParallel-Port 16-Bit®aSoundPort Stereo CodecAD1845
AD1845JST ,Parallel-Port 16-Bit SoundPort Stereo Codecapplications. The codec includes stereo audio converters, com-FUNCTIONAL BLOCK DIAGRAMANALOG ANALO ..
AD1845JST ,Parallel-Port 16-Bit SoundPort Stereo Codecapplications lacking DMA control.68-Lead PLCC, 100-Lead TQFP PackagesTwo input control lines suppor ..
AD1845JST ,Parallel-Port 16-Bit SoundPort Stereo CodecOVERVIEW FIFOs buffer data transfers and allow for relaxed timing inThe Parallel Port AD1845 SoundP ..
AD1846JP ,Low Cost Parallel-Port 16-Bit SoundPort Stereo CodecSPECIFICATIONSSTANDARD TEST CONDITIONS UNLESS OTHERWISE NOTEDDAC Output ConditionsPost-Autocalibrat ..
AD8304ARUZ , 160 dB Range (100 pA -10 mA) Logarithmic Converter
AD8305ACP ,100 dB Range (10 nA to 1 mA) Logarithmic ConverterSPECIFICATIONSotherwise noted.)Parameter Conditions Min Typ Max UnitINPUT INTERFACE Pin 4, INPT, Pi ..
AD8306AR ,5 MHz-400 MHz 100 dB High Precision Limiting-Logarithmic AmplifierSPECIFICATIONSS A1 1Parameter Conditions Min Typ Max UnitsINPUT STAGE (Inputs INHI, INLO)2Maximum I ..
AD8307 ,Low Cost, DCAPPLICATIONSCOMMON COM COMConversion of Signal Level to Decibel FormOFSINPUT-OFFSETOFS. ADJ.COMPENS ..
AD8307AN ,Low Cost DC-500 MHz, 92 dB Logarithmic AmplifierSPECIFICATIONSS A L Parameter Conditions Min Typ Max UnitsGENERAL
AD8307AR ,Low Cost DC-500 MHz, 92 dB Logarithmic AmplifierSpecifications subject to change without notice.–2– REV. AAD8307*Stresses above those listed under ..
AD1845JP-AD1845JP-REEL-AD1845JST
Parallel-Port 16-Bit SoundPort Stereo Codec
Parallel-Port 16-BitSoundPort® Stereo Codec
FEATURES
Single-Chip Integrated ∑Δ Digital Audio Stereo Codec
Microsoft® and Windows® Sound System Compatible
MPC Level-2+ Compliant Mixing
16 mA Bus Drive Capability
Supports Two DMA Channels for Full Duplex Operation
On-Chip Capture and Playback FIFOs
Advanced Power-Down Modes
Programmable Gain and Attenuation
Sample Rates from 4.0 kHz to 50 kHz Derived from a
Single Clock or Crystal Input
68-Lead PLCC, 100-Lead TQFP Packages
Operation from +5 V Supplies
Byte-Wide Parallel Interface to ISA and EISA Buses
Pin Compatible with AD1848, AD1846, CS4248, CS4231REV.C
PRODUCT OVERVIEWThe Parallel Port AD1845 SoundPort Stereo Codec integrates
key audio data conversion and control functions into a single
integrated circuit. The AD1845 provides a complete, single chip
computer audio solution for business audio and multimedia
applications. The codec includes stereo audio converters, com-
(Continued on Page 9)
SoundPort is a registered trademark of Analog Devices, Inc.
Microsoft and Windows are registered trademarks of Microsoft Corporation.
plete on-chip filtering, MPC Level-2 compliant analog mixing,
programmable gain, attenuation and mute, a variable sample
frequency generator, FIFOs, and supports advanced power-
down modes. It provides a direct, byte-wide interface to both
ISA (“AT”) and EISA computer buses for simplified implemen-
tation on a computer motherboard or add-in card.
The AD1845 SoundPort Stereo Codec supports a DMA re-
quest/grant architecture for transferring data with the host com-
puter bus. One or two DMA channels can be supported.
Programmed I/O (PIO) mode is also supported for control
register accesses and for applications lacking DMA control.
Two input control lines support mixed direct and indirect ad-
dressing of thirty-seven internal control registers over this asyn-
chronous interface. The AD1845 includes dual DMA count
registers for full duplex operation enabling the AD1845 to cap-
ture data on one DMA channel and play back data on a separate
channel. The FIFOs on the AD1845 reduce the risk of losing
data when making DMA transfers over the ISA/EISA bus. The
FIFOs buffer data transfers and allow for relaxed timing in
acknowledging requests for capture and playback data.
FUNCTIONAL BLOCK DIAGRAM
M_IN
L_AUX2
R_AUX2
L_MIC
R_MIC
ANALOG SUPPLY
HOST DMA
INTERRUPT
L_OUT
M_OUT
R_OUT
L_LINE
R_LINE
L_AUX1
R_AUX1
DIGITAL SUPPLYCLOCK SOURCEPOWER DOWNRESETDIGITALANALOG
BUS DRIVER
CONTROL
EXTERNAL
CONTROL
VREFVREF_F
PLAYBACK ACK
CAPTURE ACK
PLAYBACK REQ
CAPTURE REQ
ADR1:0
DATA7:0
AD1845–SPECIFICATIONS
STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTEDTemperature25°C
Digital Supply (VDD)5.0V
Analog Supply (VCC)5.0V
Word Rate (FS)48kHz
Input Signal1008Hz
Analog Output Passband20 Hz to 20 kHz
ADC FFT Size2048
DAC FFT Size8192
VIH5V
VIL0V
ANALOG INPUT
PROGRAMMABLE GAIN AMPLIFIER–ADC
AUXILIARY LINE, MONO, AND MICROPHONE INPUT ANALOG GAIN/AMPLIFIERS/ATTENUATORS
DIGITAL DECIMATION AND INTERPOLATION FILTERS**Guaranteed, not tested.
DAC Test Conditions
Calibrated
0 dB Relative to Full Scale
16-Bit Linear Mode
10 kΩ Output Load
Mute Off, OL = 0
ADC Test Conditions
Calibrated
0 dB Gain
–1.0 dB Relative to Full Scale
Line Input
16-Bit Linear Mode
ANALOG-TO-DIGITAL CONVERTERS
DIGITAL-TO-ANALOG CONVERTERS
DAC ATTENUATOR
ANALOG OUTPUT*Guaranteed, not tested.
AD1845
AD1845
SYSTEM SPECIFICATIONSSystem Frequency Response Ripple (Line In to Line Out)*
Differential Nonlinearity*
STATIC DIGITAL SPECIFICATIONSHigh Level Input Voltage (VIH)
High Level Output Voltage (VOH) IOH = –2 mA
Low Level Output Voltage (VOL) IOL = 2 mA
TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE RANGE, VDD = VCC = 5.0 V)Write Data Setup to WR Rising
Data Hold from WR Rising
DRQ Hold from WR/RD Falling
*Guaranteed, not tested.
POWER SUPPLYPower Supply Range–Digital and Analog
Power Supply Current
Analog Supply Current
Digital Supply Current
Power Dissipation
Power-Down Supply Current
Reset Supply Current
Total Power-Down Supply Current
Standby Supply Current
Mixer Power-Down Supply Current
Mixer Only Supply Current
ADC Power-Down Supply Current
DAC Power-Down Supply Current
Power Supply Rejection (100 mV p-p Signal @ 1 kHz)*
CLOCK SPECIFICATIONS*Input Clock Frequency
Recommended Clock Duty Cycle
*Guaranteed, not tested.
Specifications subject to change without notice.
AD1845
ORDERING GUIDENOTESP = Plastic Leaded Chip Carrier; ST = Thin Quad Flatpack.13" Reel, multiples of 250 pcs.
ENVIRONMENTAL CONDITIONSAmbient Temperature Rating:
TAMB = TCASE – (PD × θCA)
TCASE = Case Temperature in °C
PD = Power Dissipation in W
θCA = Thermal Resistance (Case-to-Ambient)
θJA = Thermal Resistance (Junction-to-Ambient)
θJC = Thermal Resistance (Junction-to-Case)
ABSOLUTE MAXIMUM RATINGS**Stresses greater than those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
AD1845
PIN DESIGNATIONS
XCTL1
INT
XCTL0
VDD
GNDD
M_OUT
M_IN
VDD
GNDD272829303132333435363738394041424344454647484950
ADR0
CDAK
CDRQ
PDAK
PDRQ
VDD
GNDD
XTAL1I
XTAL1O
VDD
GNDD
XTAL2I
XTAL2O
PWRDWN
RESET
GNDD
R_FILT
ADR1GNDDVNCNCNCDATA0DATA1DATA2DATA3GNDDV
DATA4DATA5DATA6DATA7NCNCNCNCGNDDDBENDBDIRWR
XCTL1
INT
XCTL0
VDD
GNDD
M_OUT
M_IN
VDD
GNDD28293031323334353637383940414243
NC = NO CONNECT
ADR0
CDAK
CDRQ
PDAK
PDRQ
VDD
GNDD
XTAL1I
XTAL1O
VDD
GNDD
XTAL2I
XTAL2O
PWRDWN
RESET
GNDD
R_FILT
ADR1GNDDV
DATA0DATA1DATA2DATA3GNDDV
DATA4DATA5DATA6DATA7GNDDDBENDBDIRWR
R_LINE
R_MIC
L_MIC
L_LINE
L_FILT
REF
REF_F
GNDA
GNDA
L_AUX2L_AUX1
L_OUT
R_OUT
R_AUX1R_AUX2
100-Lead TQFP
68-Lead PLCC
PIN FUNCTION DESCRIPTIONS
Parallel Interface
AD1845
Analog Signals
MiscellaneousVREF_F
L_FILT
R_FILT
Power Supplies(Continued from page 1)
unsigned magnitude PCM linear data, and 8-bit μ-law or A-law
companded digital data.
The ∑Δ DACs are preceded by a digital interpolation filter. An
attenuator provides independent user volume control over each
DAC channel. Nyquist images and shaped quantized noise are
removed from the DACs’ analog stereo output by on-chip
switched-capacitor and continuous-time filters.
The AD1845 supports multiple low power and power-down
modes to support notebook and portable computing multimedia
applications. The ADC, DAC, and mixer paths can be sus-
pended independently allowing the AD1845 to be used for
capture-only or playback-only, lessening power consumption
and extending battery life.
The AD1845 includes a variable sample frequency generator,
that allows the codec to instantaneously change sample rates
with a resolution of 1 Hz without “clicks” and “pops.” Addi-
tionally, ∑Δ quantization noise is kept out of the 20 kHz audio
band regardless of the chosen sample rate. The codec uses the
variable sample frequency generator to derive all internal clocks
from a single external crystal or clock source.
Expanded Mode (MODE2)MODE1 is the initial state of the AD1845. In this state the
AD1845 appears as an AD1848 compatible device. To access
the expanded modes of operation on the AD1845, the MODE2
bit should be set in the Miscellaneous Information Control
Register. When this bit is set to one, 16 additional indirect
registers can be addressed allowing the user to access the
AD1845’s expanded features. The AD1845 can return to
MODE1 operation by clearing the MODE2 bit. In both
MODE1 and MODE2, the capture and playback FIFOs are
active to prevent data loss.
The additional MODE2 functions are:Full-Duplex DMA support.MIC input mixer, mute and volume control.Mono output with mute control.Mono input with mixer volume control.Software controlled advanced power-down modes.
Figure 1.Interface to ISA Bus
External circuit requirements are limited to a minimal number
of low cost support components. Anti-imaging DAC output
filters are incorporated on-chip. Dynamic range exceeds 80dB
over the 20 kHz audio band. Sample rates from 4 kHz to 50kHz
are supported from a single external crystal or clock source.
The AD1845 has built-in 8/16mA (user selectable) bus drivers.
If 24mA drive capability is required, the AD1845 generates
enable and direction controls for IC bus buffers such as the
74 245.
The codec includes a stereo pair of ∑Δ analog-to-digital con-
verters and a stereo pair of ∑Δ digital-to-analog converters. The
AD1845 mixer surpasses MPC Level-2 recommendations.
Inputs to the ADC can be selected from four stereo pairs of
analog signals: line (LINE), microphone (MIC), auxiliary line
#1 (AUX1), and post-mixed DAC output. A software-con-
trolled programmable gain stage allows independent gain for
each channel going into the ADC. In addition, the analog mixer
allows the mono input (M_IN), MIC, AUX1, LINE and auxil-
iary line #2 (AUX2) signals to be mixed with the DACs’ output.
The ADCs’ output can be digitally mixed with the DACs’ input.
The pair of 16-bit outputs from the ADCs is available over a
byte-wide bidirectional interface that also supports 16-bit digital
input to the DACs and control information. The AD1845 can
AD1845
Digital MixingStereo digital output from the ADCs can be digitally mixed with
the input to the DACs. Digital output from the ADCs going out
of the data port is unaffected by the digital mix. Along the
digital mix datapath, the 16-bit linear output from the ADCs
is attenuated by an amount specified with control bits. Both
channels of the digital mix datapath are attenuated by the same
amount. (Note that internally the AD1845 always works with
16-bit PCM linear data, digital mixing included; format conver-
sions take place at the input and output.)
Sixty-four steps of –1.5 dB attenuation are supported to –94.5dB.
The digital mix datapath can also be completely muted. Note
that the level of the mixed signal is also a function of the input
PGA settings, since they affect the ADCs’ output.
The attenuated digital mix data is digitally summed with the
DAC input data prior to the DACs’ datapath attenuators. The
digital sum of digital mix data and DAC input data is clipped at
plus or minus full scale and does not wrap around. Because both
stereo signals are mixed before the output attenuators, mix data is
attenuated a second time by the DACs’ datapath attenuators.
In case the AD1845 is capturing data, but ADC output data is
not removed in time (“ADC overrun”), the last sample captured
before overrun will be used for the digital mix. In case the
AD1845 is playing back data, but input digital DAC data fails
to arrive in time (“DAC underrun”), a midscale zero will be
added to the digital mix data when the DACZ control bit is set
to 0; otherwise, the DAC will output the previous valid sample
in an underrun condition.
Analog OutputsStereo and mono line-level outputs are available at external
pins. Each channel of this output can be independently muted.
When muted, the outputs will settle to a dc value near VREF, the
midscale reference voltage. The output is selectable for 2.0 V
peak-to-peak or 2.8 V peak-to-peak. When selecting the LINE
output as an input to the ADC, the ADC automatically com-
pensates for the output level selection.
Digital Data TypesThe AD1845 supports five global data types: 16-bit twos comple-
ment linear PCM (little endian and big endian byte ordering),
8-bit unsigned linear PCM, companded μ-law, and 8-bit com-
panded A-law, as specified by control register bits. Data in all
formats is always transferred MSB first. All data formats that are
less than 16 bits are MSB-aligned to ensure the use of full
system resolution.
The 16-bit PCM data format is capable of representing 96 dB
of dynamic range. Eight-bit PCM can represent 48 dB of dy-
namic range. Companded μ-law and A-law data formats use
nonlinear coding with less precision for large amplitude signals.
The loss of precision is compensated for by an increase in dy-
namic range to 64 dB and 72 dB, respectively.
On input, 8-bit companded data is expanded to an internal
linear representation, according to whether μ-law or A-law was
specified in the codec’s internal registers. Note that when μ-law
compressed data is expanded to a linear format, it requires
14 bits. A-law data expanded requires 13 bits.
FUNCTIONAL DESCRIPTIONThis section overviews the functionality of the AD1845 and is
intended as a general introduction to the capabilities of the
device. As much as possible, detailed reference information has
been placed in “Control Registers” and other sections. The
user is not expected to refer repeatedly to this section.
Analog InputsThe AD1845 SoundPort Stereo Codec accepts stereo line-level
and microphone-level inputs. The LINE, MIC, AUX1, and
post-mixed DAC output are available to the ADC multiplexer.
The DAC output can be mixed with LINE, MIC, AUX1,
AUX2 and M_IN. Each channel of the MIC inputs can be
amplified by +20 dB to compensate for the difference between
line levels and typical condenser microphone levels.
Analog MixingThe M_IN mono input signal, MIC, LINE, AUX1 and AUX2
analog stereo signals can be mixed in the analog domain with
the DAC output. Each channel of each AUX, LINE and MIC
analog input can be independently gained/attenuated from
+12dB to –34.5dB in 1.5dB steps or completely muted.
M_IN can be attenuated from 0 dB to –45 dB in 3 dB steps or
muted. The post-mixed DAC outputs are available on L_OUT
and R_OUT and also to the ADC input multiplexer.
Even if the AD1845 is not playing back data from its DACs, the
analog mix function can still be active.
Analog-to-Digital DatapathThe PGA following the input multiplexer allows independent
selectable gains for each channel from 0dB to 22.5dB in
+1.5dB steps. The codec can operate either in a global stereo
mode or in a global mono mode with left-channel inputs
appearing at both channel outputs.
The AD1845 ∑Δ ADCs incorporate a fourth-order modulator.
A single pole of passive filtering is all that is required for anti-
aliasing the analog input because of the ADC’s high over sam-
pling ratio. The ADCs include linear-phase digital decimation
filters that low-pass filter the input to 0.4 × FS. (“FS” is the
word rate or “sampling frequency.”) ADC input over range
conditions are reported on status bits in the Test and Initializa-
tion Register.
Digital-to-Analog DatapathThe ∑Δ DACs are preceded by a programmable attenuator and
a low-pass digital interpolation filter. The anti-imaging interpo-
lation filter over samples and digitally filters the higher fre-
quency images. The attenuator allows independent control of
each DAC channel from 0dB to –94.5dB in –1.5dB steps plus
full mute. The DACs’ ∑Δ noise shapers also over sample and
convert the signal to a single-bit stream. The DAC outputs are
then filtered in the analog domain by a combination of switched-
capacitor and continuous-time filters. They remove the very
high frequency components of the DAC bit stream output. No
external components are required.
Changes in DAC output attenuation take effect only on zero
crossings, eliminating “zipper” noise on playback. Each chan-
nel has its own independent zero-crossing detector and attenua-
tor change control circuitry. A timer guarantees that requested
COMPRESSEDINPUT DATA
8 7015
3/2 2/1015
EXPANSION
3/2 2/1015
DAC INPUTFigure 2. μ-Law or A-Law Expansion
When 8-bit companding is specified, the ADCs’ linear output is
compressed to the format specified.
15
3/2 2/1015
8 7015
ADC OUTPUT
TRUNCATION
COMPRESSIONFigure 3.μ-Law or A-Law Compression
Note that all format conversions take place at input or output.
Internally, the AD1845 always uses 16-bit linear PCM represen-
tations to maintain maximum precision.
Timer RegistersThe timer registers are provided for system level synchroniza-
tion, and for periodic interrupt generation. The 16-bit timer
time base is determined by the frequency of the connected input
clock source.
The timer is enabled by setting the Timer Enable bit, TE, in the
Alternate Feature Enable register. To set the timer, load the
Upper and Lower Timer Bits Registers. The timer value will
then be loaded into an internal count register with a value of
approximately 10μs (the exact timer value is listed in the regis-
ter descriptions). The internal count register will decrement
until it reaches zero, then the Timer Interrupt bit, TI, is set and
an interrupt will be sent to the host. The next timer clock will
load the internal count register with the value of the Timer
Register, and the timer will be reinitialized. To clear the inter-
rupt, write to the Status Register or write a “0” to TI.
InterruptsThe AD1845 supports interrupt conditions generated by DMA
playback count expiration, DMA capture count expiration, or
timer expiration. The INT bit will remain set, HI, until a write
has been completed to the Status Register or by clearing the TI,
CI, or PI bit (depending on the existing condition) in the Cap-
ture Playback Timer Register. The IEN bit of the Pin Control
Register determines whether the interrupt pin responds to an
interrupt condition and reflects the interrupt state on the
INT status bit.
Power Supplies and Voltage ReferenceThe AD1845 operates from a +5V power supply. Independent
analog and digital supplies are recommended for optimal perfor-
mance though excellent results can be obtained in single-supply
systems. A voltage reference is included on the codec and its
2.25V buffered output is available on an external pin (VREF).
The reference output can be used for biasing op amps used in
dc coupling. The internal reference is externally bypassed to
analog ground at the VREF_F pin.
Clocks and Sample RatesThe AD1845 operates from a single external crystal or clock
source. From a single input, a wide range of sample rates can be
generated. The AD1845 default frequency source is a
24.576MHz input. The AD1845 can also be driven from a
14.31818 MHz (OSC), 24 MHz, 25 MHz or 33 MHz input
frequency source. In MODE1, the input drives the internal
variable sample frequency generator to derive the following
AD1848 compatible sample rates: 5.5125, 6.615, 8, 9.6,
11.025, 16, 18.9, 22.05, 27.42857, 32, 33.075, 37.8, 44.1,kHz. In MODE2, the AD1845 can be programmed to gen-
erate any sample frequency between 4kHz and 50kHz withHz resolution. Note that it is no longer required to enter
Mode Change Enable (MCE) to change the sample rate. This
feature allows the user to change the AD1845’s sample rate “on
the fly.”
CONTROL REGISTERS
Control Register ArchitectureThe AD1845 SoundPort Stereo Codec accepts both data and
control information through its byte-wide parallel port. Indirect
addressing minimizes the number of external pins required to
access all 37 of its byte-wide internal registers. Only two exter-
nal address pins, ADR1:0, are required to accomplish all data
and control transfers. These pins select one of five direct regis-
ters. (ADR1:0 = 3 addresses two registers, depending on
whether the transfer is for a playback or capture.)
Figure 4.Direct Register Map
AD1845A write to or a read from the Indexed Data Register will access the Indirect Register which is indexed by the value most recently
written to the Index Address Register. The Status Register and the PIO Data Register are always accessible directly, without
indexing. The 32 Indirect Register indexes are shown in Figure 5:
“x” indicates reserved bit, always write “0s” to these bits.
Figure 5.Indirect Register Map and Reset/Default States
A detailed map of all direct and indirect register contents is summarized for reference as follows:
AD1845IXA4:0Index Address. These bits define the address of the AD1845 register accessed by the Indexed Data Register.
These bits are read/write. IXA4 is not active in MODE1. Always write 0 to this bit when using the AD1845 in
MODE1.
TRDTransfer Request Disable. This bit, when set, causes PIO and DMA transfers to cease when the Interrupt Status
(INT) bit of the Status Register is set.Transfers Enabled During Interrupt. PDRQ and CDRQ pin outputs are generated uninhibited by interrupts.
DMA Current Counter Register decrements with every sample transferred when either PEN or CEN are enabled.Transfers Disabled By Interrupt.PDRQ and CDRQ pin outputs are generated only if INT bit is 0 (when
either PEN or CEN, respectively are enabled). Any pending playback or capture requests are allowed to
complete at the time when INT is set. After pending requests complete, the data in the FIFO will be con-
sumed at the sample rate. Subsequently, the midscale inputs will be internally generated for the DACs if
the DACZ bit is set, otherwise, the previous valid sample will be repeated, and the ADC output buffer will
contain the last valid output. Clearing the sticky INT bit (or the TRD bit) will cause the resumption of
playback and/or capture requests (presuming PEN and/or CEN are enabled). The DMA Current Counter
Register will not decrement while both the TRD bit is set and the INT bit is a one. No over run or under
run error will be reported when transfers are disabled by INT.
MCEMode Change Enable. This bit must be set whenever the current functional mode of the AD1845 is changed
where noted in the Indirect Control Registers 8, 9, 28 and 29. MCE must be cleared at the completion of the
desired register changes.
The DAC outputs are automatically muted when the MCE bit is set. After MCE is cleared, the DAC outputs will
be restored to the state specified by the LDM and RDM mute bits.
Both ADCs and DACs are automatically muted for 32 sample cycles after exiting the MCE state to allow the refer-
ence and all filters to settle. The ADCs will produce midscale values; the DACs’ analog output will be muted. All
converters are internally operating during these 32 sample cycles, and the AD1845 will expect playback data and
will generate (midscale) capture data. Note that the autocalibrate-in-progress (ACI) bit will be set on exiting from
the MCE state only when ACAL is set. If ACAL bit is set, ACI will remain HI for these 384 sample cycles, allow-
ing system software to poll this bit rather than count cycles.
Special sequences must be followed if autocalibrate (ACAL) is set during mode change enable. See the
“Autocalibration” section.
INITAD1845 Initialization. This bit is set when the AD1845 cannot respond to parallel bus cycles. This bit is
read-only.
Immediately after reset and once the AD1845 has left the INIT state, the initial value of this register will be “0100 0000 (40h).”
During AD1845 initialization, this register cannot be written and always reads “1000 0000 (80h).”
IXD7:0Indexed Register Data. These bits contain the contents of the AD1845 register referenced by the Indexed Data
Register.
During AD1845 initialization, this register cannot be written and always reads as “1000 0000 (80h).”
INTInterrupt Status. This sticky bit (the only one) indicates the status of the interrupt logic of the AD1845. This bit
is cleared by any host write of any value to this register.The IEN bit of the Pin Control Register determines
whether the state of this bit is reflected on the INT pin of the AD1845. The only interrupt conditions supported
by the AD1845 are generated by the underflow of the DMA Current Count Register or the Timer Registers. The
Timer Register operates at a 10 μs resolution. Clearing INT requires a 10 μs wait. If an immediate clearing of a TI
condition is desired, clear the TE bit to remove the timer interrupt.Interrupt pin inactiveInterrupt pin active
PRDYPlayback Data Register Ready. The PIO or DMA Playback Data Register is ready for more data. This bit is intended
to be used when direct programmed I/O data transfers are desired; however, it is also valid for DMA transfers.
This bit is read-only.DAC data is still valid. Do not overwrite.DAC data is stale. Ready for next host data write value.
PL/RPlayback Left/Right Sample. This bit indicates whether the PIO or DMA playback data needed is for the right
channel DAC or left channel DAC. This bit is read-only.Right channel neededLeft channel or mono
PU/LPlayback Upper/Lower Byte. This bit indicates whether the PIO or DMA playback data needed is for the upper or
lower byte of the channel. This bit is read-only.Lower byte neededUpper byte needed or any 8-bit mode
SOURSample Over/Underrun. This bit indicates that the most recent sample was not serviced in time and therefore
either a capture overrun (COR) or playback underrun (PUR) has occurred. The bit indicates an overrun for ADC
capture and an underrun for DAC playback. If both capture and playback are enabled, the source that set this bit
can be determined by reading COR and PUR. This bit changes on a sample by sample basis. This bit is read-only.
CRDYCapture Data Ready. The PIO Capture Data Register contains data ready for reading by the host. This bit
should only be used when direct programmed I/O data transfers are desired. This bit is read-only.ADC data is stale. Do not reread the information.ADC data is fresh. Ready for next host data read.
CL/RCapture Left/Right Sample. This bit indicates whether the PIO capture data waiting is for the right channel ADC
or left channel ADC. This bit is read-only.Right channelLeft channel or mono
CU/LCapture Upper/Lower Byte. This bit indicates whether the PIO capture data ready is for the upper or lower byte
of the channel. This bit is read-only.Lower byte readyUpper byte ready or any 8-bit mode
The PRDY, CRDY, and INT bits of this status register can change asynchronously to host accesses. The host may access this regis-
ter while the bits are transitioning. The host read may return a zero value just as these bits are changing, for example. A one value
would not be read until the next host access.
While the FIFOs have multiple samples available for transfer, the CRDY and PRDY status bits for consecutive samples are approxi-
mately 320 ns–600 ns apart.
This register’s initial state after reset is “1100 1100.”
The PIO Data Registers are two registers mapped to the same address. Writes send data to the PIO Playback Data Register
(PD7:0). Reads will receive data from the PIO Capture Data Register (CD7:0).
During AD1845 initialization, the PIO Playback Data Register cannot be written to and the Capture Data Register is always read
as “1000 0000 (80h).”
CD7:0PIO Capture Data Register. This is the control register where capture data is read during programmed I/O data
transfers.
The reading of this register will increment the capture byte state machine so that the following read will be from
the next appropriate byte in the sample. The exact byte which is next to be read can be determined by reading the
Status Register. Once all relevant bytes have been read, the state machine will stay pointed to the last byte of the
sample until a new sample is received from the ADCs. Once this has occurred, the state machine and Status
Register will point to the first byte of the sample.
PD7:0PIO Playback Data Register. This is the control register where playback data is written during programmed I/O
data transfers.
Writing data to this register will increment the playback byte tracking state machine so that the following write will
be to the correct byte of the sample. Once all bytes of a sample have been written, subsequent byte writes to this
port are ignored. The state machine is reset when the current sample is sent to the DACs.
INDIRECT CONTROL REGISTER DEFINITIONSThe following control registers are accessed by writing index values to IXA3:0 in the Index Address Register (ADR1:0 = 0) followed
LIG3:0Left input gain select. The least significant bit of this gain select represents +1.5dB. Maximum gain is +22.5dB.
resReserved for future expansion. Always write a zero to this bit.
LMGELeft Input Microphone Gain Enable. This bit will enable the +20dB gain of the left MIC input signal.
LSS1:0Left Input Source Select. These bits select the input source for the left gain stage preceding the left ADC.
LSS1LSS0Left Input Source0Left Line Source Selected1Left Auxiliary 1 Source Selected0Left Microphone Source Selected1Left Line Post-Mixed DAC Output Source Selected
This register’s initial state after reset is “000x 0000.”
RIG3:0Right Input Gain Select. The least significant bit of this gain select represents +1.5 dB. Maximum gain is +22.5 dB.
resReserved for future expansion. Always write a zero to this bit.
RSS1RSS0Right Input Source0Right Line Source Selected1Right Auxiliary 1 Source Selected0Right Microphone Source Selected1Right Post-Mixed DAC Output Source Selected
LX1A4:0Left Auxiliary Input #1 Attenuate Select. The least significant bit of this gain/attenuate select represents1.5 dB.
LX1A4:0 = 0 produces a +12 dB gain. LX1A4:0 = “01000” (8 decimal) produces 0 dB gain. Maximum attenua-
tion is –34.5 dB. See Figure 10.
resReserved for future expansion. Always write zeros to these bits.
LMX1Left Auxiliary #1 Mute. This bit, when set, will mute the left channel of the Auxiliary #1 input source. This bit
powers up set.
RX1A4:0Right Auxiliary Input #1 Attenuate Select. The least significant bit of this gain/attenuate select represents
1.5 dB. RX1A4:0 = 0 produces a +12 dB gain. RX1A4:0 = “01000” (8 decimal) produces 0 dB gain. Maximum
attenuation is –34.5 dB. See Figure 10.
resReserved for future expansion. Always write zeros to these bits.
RMX1Right Auxiliary #1 Mute. This bit, when set, will mute the right channel of the Auxiliary #1 input source. This
bit powers up set.
LX2A4:0Left Auxiliary Input #2 Attenuate Select. The least significant bit of this gain/attenuate select represents 1.5 dB.
LX2A4:0 = 0 produces a +12 dB gain. LX2A4:0 = “01000” (8 decimal) produces 0 dB gain. Maximum attenua-
tion is –34.5 dB. See Figure 10.
resReserved for future expansion. Always write zeros to these bits.
LMX2Left Auxiliary #2 Mute. This bit, when set to 1, will mute the left channel of the Auxiliary #2 input source. This
bit powers up set.
This register’s initial state after reset is “1xx0 1000.”
AD1845RX2A4:0Right Auxiliary Input #2 Attenuate Select. The least significant bit of this gain/attenuate select represents
1.5 dB. RX2A4:0 = 0 produces a +12 dB gain. RX2A4:0 = “01000” (8 decimal) produces 0 dB gain.
Maximum attenuation is –34.5 dB. See Figure 10.
resReserved for future expansion. Always write zeros to these bits.
RMX2Right Auxiliary #2 Mute. This bit, when set, will mute the right channel of the Auxiliary #2 input source. This bit
powers up set.
LDA5:0Left DAC Attenuate Select. The least significant bit of this gain/attenuate select represents 1.5 dB. Maximum
attenuation is –94.5 dB. See Figure 7.
resReserved for future expansion. Always write a zero to this bit.
LDMLeft DAC Mute. This bit, when set to 1, will mute the left DAC output. This bit powers up active.
This register’s initial state after reset is “1x00 0000.”
RDA5:0Right DAC Attenuate Select. The least significant bit of this gain/attenuate select represents 1.5 dB. Maximum
attenuation is –94.5 dB. See Figure 7.
resReserved for future expansion. Always write a zero to this bit.
RDMRight DAC Mute. This bit, when set to 1, will mute the right DAC output. This bit powers up active.
This register’s initial state after reset is “1x00 0000.”
A4A3A2A1A0 Mix Gain
NOTE:Placing the AD1845 in the Mode Change Enable (MCE) state is not required when changing the sample rate. However,
changes to FMT[1:0], C/L, and S/M require MCE or setting PEN = 0.
CSSClock Source Select. This bit in conjunction with CFS2:0 selects the audio sample rate frequency. See Figure 8
below. Note: MODE2 allows a wider range of sample rate frequencies to be selected by using the Frequency
Select Register (refer to Registers 22 and 23).
CFS2:0Clock Frequency Divide Select. These bits in conjunction with CSS select the audio sample frequency.
CFS2CFS1CFS0CSSSample Rate
Figure 8.MODE1 Audio Sample Frequency Select
S/MStereo/Mono Select. This bit determines how the audio data streams are formatted. Selecting stereo will result
with alternating samples representing left and right audio channels. Mono playback plays the same audio sample
on both channels. Mono capture only captures data from the left audio channel.MonoStereo
C/LCompanded/Linear Select. This bit selects between a linear digital representation of the audio signal or a nonlinear,
companded format for all input and output data. The type of linear PCM or the type of companded format is
defined by the FMT bits.Linear PCMCompanded
FMT[1:0]Format Select. The bits define the format for all digital audio input and outputs based on the state of the C/L bit.
See Figure 9 for FMT and C/L bit settings that determine the audio data type format.
resReserved for future expansion. Always write a zero to this bit.
This register’s initial state after reset is “0000 0000.”
FMT1FMT0C/LAudio Data Type
NOTE: Placing the AD1845 in the Mode Change Enable (MCE) state is not required when changing the CEN and PEN bits in this
register.
PENPlayback Enable. This bit will enable the playback of data in the format selected. The AD1845 will generate
PDRQ and respond to PDAK signals when this bit is enabled and PPIO = 0. If PPIO = 1, this bit enables Pro-
grammed I/O (PIO) playback mode.Playback disabled (PDRQ and PIO Playback Data Register inactive)Playback enabled
CENCapture Enable. This bit will enable the capture of data in the format selected. The AD1845 will generate
CDRQ and respond to CDAK signals when this bit is enabled and CPIO = 0. If CPIO = 1, this bit enables PIO
capture mode.Capture disable (CDRQ and PIO Capture Data Register inactive)Capture enable
SDCSingle DMA Channel. This bit will force both capture and playback DMA requests to occur on the Playback
DMA channel. The Capture DMA CDRQ pin will be LO. This bit will allow the AD1845 to be used with only
one DMA channel. Simultaneous capture and playback cannot occur in this mode. Should both capture and
playback be enabled (CEN=PEN=1) in the mode, only playback will occur. See “Data and Control Transfers” for
further explanation.Dual DMA channel modeSingle DMA channel mode
ACALAutocalibrate Enable. This bit determines whether the AD1845 performs an autocalibration whenever the Mode
Change Enable (MCE) bit changes from HI to LO. See “Autocalibration” for a description of a complete
autocalibration sequence. Note that an autocalibration is forced whenever the RESET or PWRDWN pin is
asserted LO then transitions HI regardless of the state of the ACAL bit.No autocalibrationAutocalibration after mode change
resReserved for future expansion. Always write zeros to these bits.
PPIOPlayback PIO Enable. This bit determines whether the playback data is transferred via DMA or PIO.DMA transfers onlyPIO transfers only
CPIOCapture PIO Enable. This bit determines whether the capture data is transferred via DMA or PIO.DMA transfers onlyPIO transfers only
This register’s initial state after reset is “00xx 1000.”
INITDDisable setting the INIT bit after changing the sample rate in MODE1. Otherwise the INIT bit is set HI for
approximately 200 μs after changing the sample rate.INIT bit is enabledINIT bit is disabled
IENInterrupt Enable. This bit enables the interrupt pin. The Interrupt Pin will go active HI when the number of
samples programmed in the Base Count Register is reached.
