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AD1839AAS
2 ADC, 6 DAC 96 kHz, 24-Bit Sigma Delta Codec
2 ADC, 6 DAC,
96 kHz, 24-Bit Sigma-Delta Codec
Rev. B
FEATURES
5 V stereo audio system with 3.3 V tolerant digital interface
Supports up to 96 kHz sample rates
192 kHz sample rate available on 1 DAC
Supports 16-/20-/24-bit word lengths
Multibit Σ-∆ modulators with perfect differential linearity
restoration for reduced idle tones and noise floor
Data-directed scrambling DACs—least sensitive to jitter
Single-ended output
ADCs: −95 dB THD + N, 105 dB SNR and dynamic range
DACs: −92 dB THD + N, 108 dB SNR and dynamic range
On-chip volume controls per channel with 1024-step linear
scale
DAC and ADC software controllable clickless mutes
Digital de-emphasis processing
Supports 256 × fS, 512 × fS, and 768 × fS master mode clocks
Power-down mode and soft power-down mode
Flexible serial data port with right-justified, left-justified, 2S compatible, and DSP serial modes
TDM interface mode supports 8-in/8-out operation using a
single SHARC® SPORT
52-lead MQFP plastic package
APPLICATIONS
DVD video and audio players
Home theater systems
Automotive audio systems
Audio/visual receivers
Digital audio effects process
GENERAL DESCRIPTION The AD1839A is a high performance single-chip codec that
features three stereo DACs and one stereo ADC. Each DAC
comprises a high performance digital interpolation filter, a
multibit Σ-∆ modulator featuring Analog Devices’ patented
technology, and a continuous-time voltage-out analog section.
Each DAC has independent volume control and clickless mute
functions. The ADC comprises two 24-bit conversion channels
with multibit Σ-∆ modulators and decimation filters.
The AD1839A also contains an on-chip reference with a
nominal value of 2.25 V.
The AD1839A contains a flexible serial interface that allows
glueless connection to a variety of DSP chips, AES/EBU
receivers, and sample rate converters. The AD1839A can be
configured in left-justified, right-justified, I2S, or DSP compati-
ble serial modes. Control of the AD1839A is achieved by means
of an SPI® compatible serial port. While the AD1839A can be
operated from a single 5 V supply, it also features a separate
supply pin for its digital interface that allows the device to be
interfaced to other devices using 3.3 V power supplies. The
AD1839A is available in a 52-lead MQFP package and is
specified for the −40°C to +85°C industrial temperature range.
FUNCTIONAL BLOCK DIAGRAM
OUTL1
FILTD
FILTR
ADCLP
ADCLN
ADCRP
ADCRN
DLRCLK
DBCLK
DSDATA1
DSDATA2
DSDATA3
DAUXDATA
MCLKODVDDDVDDAVDDAVDDDVDD
AGNDDGND
CINCLATCHCCLKCOUT
M/S
OUTR1
OUTL2OUTR2
OUTL3OUTR3
AAUXDATA3
ASDATAABCLKALRCLK
AGNDAGNDAGNDDGND03627-B
PD/RST
Figure 1.
TABLE OF CONTENTS
Specifications.....................................................................................3
Test Conditions.............................................................................3
Timing Specifications.......................................................................5
Absolute Maximum Ratings............................................................7
Temperature Range......................................................................7
ESD Caution..................................................................................7
Pin Configuration and Function Descriptions.............................8
Typical Performance Characteristics.............................................9
Terminology....................................................................................11
Functional Overview......................................................................12
ADCs............................................................................................12
DACs............................................................................................12
DAC and ADC Coding..............................................................12
AD1839A Clocking Scheme.....................................................12
RESET and Power-Down..........................................................13
Power Supply and Voltage Reference.......................................13
Serial Control Port.....................................................................13
Serial Data Ports—Data Format...............................................14
Packed Modes.............................................................................14
Auxiliary Time Division Multiplexing (TDM) Mode...........14
Control/Status Registers............................................................19
Cascade Mode.............................................................................22
Outline Dimensions.......................................................................24
Ordering Guide..........................................................................24
REVISION HISTORY
5/04—Data Sheet Changed from Rev. A to Rev. B
Updated Format Universal
Changes to Data Sheet Title1
2/04—Data Sheet Changed from Rev. 0 to Rev. A
Changes to Ordering Guide.............................................................6
Deleted Clock Signals Section.......................................................11
Added AD1835A Clocking Scheme Section................................11
Added Table II and Table III and renumbered following tables11
Changes to Auxiliary (TDM Mode) Section................................13
Changes to Figure 5.........................................................................14
Changes to Figure 6.........................................................................14
Added Figures 7a and 8a.................................................................15
Renamed Figure 7 and Figure 8 to Figure 7b and Figure 8b.....15
Changes to Figure 9.........................................................................15
Changes to Table VIII.....................................................................21
Updated Outline Dimensions........................................................24
SPECIFICATIONS
TEST CONDITIONS
Supply Voltages 5.0 V (AVDD, DVDD)
Ambient Temperature 25°C
Input Clock 12.288 MHz (256 × fS mode)
DAC Input Signal 1.0078125 kHz, 0 dBFS
ADC Input Signal 1.0078125 kHz, −1 dBFS
Input Sample Rate (fS) 48 kHz
Measurement Bandwidth 0 Hz to 20 kHz
Word Width 24 bits
Load Capacitance 100 pF
Load Impedance 47 kΩ
Performance of all channels is identical (except for the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications).
Table 1.
Common-Mode Output Voltage 2.25 V
TIMING SPECIFICATIONS
Table 2.
MCLK
PD/RST
ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted.
Table 3.
TEMPERATURE RANGE
Table 4. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 03627-B
DGND
CCLK
COUT
DATA
ODVDD
MCLK
ALRCLK
ABCLK
AAUX
DATA3
DATA3
DATA2
DATA1
DGNDDBCLKDLRCLKDAUXDATANCAGNDM/SDVDDNCNCAGNDOUTR3NCAVDDCLATCHCINPD/RSTOUTL1NCAGNDDVDDNCOUTR1AGNDNCOUTL2AVDD
NC = NO CONNECT
OUTR2
AGND
FILTD
FILTR
ADCLN
ADCLP
ADCRN
ADCRP
AGND
OUTL3
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
TYPICAL PERFORMANCE CHARACTERISTICS 03627-B
FREQUENCY (Normalized tofS)51015
MAGNITUDE
(dB)
–150
Figure 4. ADC Composite Filter Response
03627-B
FREQUENCY (Hz)
MAGNITUDE
(dB)
–10
Figure 5. ADC High-Pass Filter Response, fS = 48 kHz
03627-B
FREQUENCY(Normalized tofS)2.00.51.01.5
MAGNITUDE
(dB
–50
Figure 6. ADC Composite Filter Response (Pass-Band Section)
03627-B
FREQUENCY (Hz)51015
MAGNITUDE
–10
Figure 7. ADC High-Pass Filter Response, fS = 96 kHz
03627-B
FREQUENCY (kHz)
MAGNITUDE
(dB)
–100
Figure 8. DAC Composite Filter Response, fS = 48 kHz
03627-B
FREQUENCY (kHz)
MAGNITUDE
(dB)
–100100150
Figure 9. DAC Composite Filter Response, fS = 96 kHz
03627-B
FREQUENCY (kHz)
MAGNITUDE
(dB)
–150
Figure 10. DAC Composite Filter Response, fS = 192 kHz
03627-B
FREQUENCY (kHz)0
MAGNITUDE
(dB)
51015
Figure 11. DAC Composite Filter Response, fS = 48 kHz (Pass-Band Section)
03627-B
FREQUENCY (kHz)010203040
MAGNITUDE
(dB)
–0.1
Figure 12. DAC Composite Filter Response, fS = 96 kHz (Pass-Band Section)
03627-B
FREQUENCY (kHz)
MAGNITUDE
(dB)
–0.05406080
Figure 13. DAC Composite Filter Response, fS = 192 kHz (Pass-Band Section)
TERMINOLOGY
Dynamic Range The ratio of a full-scale input signal to the integrated input
noise in the pass band (20 Hz to 20 kHz), expressed in decibels.
Dynamic range is measured with a −60 dB input signal and is
equal to (S/[THD + N]) + 60 dB. Note that spurious harmonics
are below the noise with a −60 dB input, so the noise level
establishes the dynamic range. The dynamic range is specified
with and without an A-weight filter applied.
Signal-to-(Total Harmonic Distortion + Noise)
[S/(THD + N)] The ratio of the root-mean-square (rms) value of the
fundamental input signal to the rms sum of all other spectral
components in the pass band, expressed in decibels.
Pass Band The region of the frequency spectrum unaffected by the
attenuation of the digital decimator’s filter.
Pass-Band Ripple The peak-to-peak variation in amplitude response from equal-
amplitude input signal frequencies within the pass band,
expressed in decibels.
Stop Band The region of the frequency spectrum attenuated by the digital
decimator’s filter to the degree specified by stop-band
attenuation.
Gain Error With identical near full-scale inputs, the ratio of actual output
to expected output, expressed as a percentage.
Interchannel Gain Mismatch With identical near full-scale inputs, the ratio of outputs of the
two stereo channels, expressed in decibels.
Gain Drift Change in response to a near full-scale input with a change in
temperature, expressed as parts-per-million (ppm) per °C.
Crosstalk (EIAJ Method) Ratio of response on one channel with a grounded input to a
full-scale 1 kHz sine wave input on the other channel, expressed
in decibels.
Power Supply Rejection With no analog input, signal present at the output when a
300 mV p-p signal is applied to the power supply pins,
expressed in decibels of full scale.
Group Delay Intuitively, the time interval required for an input pulse to
appear at the converter’s output, expressed in microseconds.
More precisely, the derivative of radian phase with respect to
the radian frequency at a given frequency.
Group Delay Variation The difference in group delays at different input frequencies.
Specified as the difference between the largest and the smallest
group delays in the pass band, expressed in microseconds.
Acronyms
ADC—Analog-to-digital converter.
DAC—Digital-to-analog converter.
DSP—Digital signal processor.
IMCLK—Internal master clock signal used to clock the ADC and DAC engines.
MCLK—External master clock signal applied to the AD1839A. FUNCTIONAL OVERVIEW
ADCS There are two ADC channels in the AD1839A, configured as a
stereo pair. Each ADC has fully differential inputs. The ADC
section can operate at a sample rate of up to 96 kHz. The ADCs
include on-board digital decimation filters with 120 dB stop-
band attenuation and linear phase response, operating at an
oversampling ratio of 128 (for 48 kHz operation) or 64 (for
96 kHz operation).
The peak level information for each ADC may be read from the
ADC Peak 0 and ADC Peak 1 registers. The data is supplied as a
6-bit word with a maximum range of 0 dB to −63 dB and a
resolution of 1 dB. The registers hold peak information until
read; after reading, the registers are reset so that new peak
information can be acquired. (Refer to the register description
in Table 10 for details of the format.) The two ADC channels
have a common serial bit clock and a left-right framing clock.
The clock signals are all synchronous with the sample rate.
The ADC digital pins, ABCLK and ALRCLK, can be set to
operate as inputs or outputs by connecting the M/S pin to
ODVDD or DGND, respectively. When the pins are set as
outputs, the AD1839A generates the timing signals. When the
pins are set as inputs, the timing must be generated by the
external audio controller.
DACS The AD1839A has six DAC channels arranged as three
independent stereo pairs, with six single-ended analog outputs.
Each channel has its own independently programmable
attenuator, adjustable in 1,024 linear steps. Digital inputs are
supplied through three serial data input pins (one for each
stereo pair) and a common frame (DLRCLK) and bit clock
(DBCLK). Alternatively, one of the packed data modes can be
used to access all six channels on a single TDM data pin. A
stereo replicate feature is included where the DAC data sent to
the first DAC pair is also sent to the other DACs in the part.
The AD1839A can accept DAC data at a sample rate of 192 kHz
on DAC 1 only. The stereo replicate feature can then be used to
copy the audio data to the other DACs.
Each of the output pins sits at a dc level of VREF and swings
±1.4 V for a 0 dB digital input signal. A single op amp, third-
order, external low-pass filter is recommended to remove high
frequency noise present on the output pins. Note that the use of
op amps with low slew rate or low bandwidth may cause high
frequency noise and tones to fold down into the audio band;
care should be exercised in selecting these components.
The FILTD pin should be connected to an external grounded
capacitor. This pin reduces the noise of the internal DAC bias
DAC AND ADC CODING The DAC and ADC output data stream is in a twos complement
encoded format. A 16-bit, 20-bit, or 24-bit word width can be
selected. The coding scheme is detailed in Table 6.
Table 6. Coding Scheme
AD1839A CLOCKING SCHEME By default, the AD1839A requires an MCLK signal that is
256 times the required sample frequency up to a maximum of
12.288 MHz. The AD1839A uses a clock scaler to double the
clock frequency for use internally. The default setting of the
clock scaler is Multiply by 2. The clock scaler can also be set to
Multiply by 1 (bypass) or Multiply by 2/3. The clock scaler is
controlled by programming the bits in the ADC Control 3
register. The internal MCLK signal, IMCLK, should not exceed
24.576 MHz to ensure correct operation.
The MCLK of the AD1839A should remain constant during
normal operation of the DAC and ADC. If it is required to
change the MCLK rate, the AD1838A should be reset. Also, if
MCLK scaler needs to be modified so that the IMCLK does not
exceed 24.576 MHz, this should be done during the internal
reset phase of the AD1839A by programming the bits in the
first 3,072 MCLK periods following the reset.
Selecting the DAC Sampling Rate The AD1839A DAC engine has a programmable interpolator
that allows the user to select different interpolation rates based
on the required sample rate and MCLK value available. Table 7
shows the settings required for sample rates based on a fixed
MCLK of 12.288 MHz.
Table 7. DAC Sample Rate Settings
Selecting an ADC Sample Rate The AD1839A ADC engine has a programmable decimator that
allows the user to select the sample rate based on the MCLK
value. By default, the output sample rate is IMCLK/512. To
achieve a sample rate of IMCLK/256, the sample rate bit in the
ADC Control 1 register should be set as shown in Table 8.
Table 8. ADC Sample Rate Settings
