AD1837AS Fast Delivery |IC PHOENIX CO.,LIMITED

AD1837AS ,2 ADC, 8 DAC, 96 kHz, 24-Bit Codecspecifications).Parameter Min Typ Max UnitANALOG-TO-DIGITAL CONVERTERSADC Resolution 24 BitsDynamic ..
AD1838AAS ,2 ADC, 6 DAC 96 kHz, 24-Bit Sigma Delta CodecSPECIFICATIONSAD1838ATEST CONDITIONSSupply Voltages (AVDD, DVDD) 5.0 VAmbient Temperature 25°CInput ..
AD1838AS ,Please see the AD1838A.specifications).Parameter Min Typ Max UnitANALOG-TO-DIGITAL CONVERTERSADC Resolution 24 BitsDynamic ..
AD1839AAS ,2 ADC, 6 DAC 96 kHz, 24-Bit Sigma Delta Codecfeatures three stereo DACs and one stereo ADC. Each DAC 192 kHz sample rate available on 1 DAC comp ..
AD1843JS ,Serial-Port 16-Bit SoundComm CodecSerial-Port 16-BitaSoundComm CodecAD1843
AD1845JP ,Parallel-Port 16-Bit SoundPort Stereo CodecFEATURESplete on-chip filtering, MPC Level-2 compliant analog mixing,Single-Chip Integrated ∑Δ Digi ..
AD8300ARZ-REEL ,+3 Volt, Serial Input Complete 12-Bit DACCHARACTERISTICSPower Supply Range V DNL < – 1 LSB 2.7 5.5 VDD RANGEPositive Supply Current I V = 3 ..
AD8302ARU ,LF.2.7 GHz RF/IF Gain and Phase DetectorSPECIFICATIONS A Sresistors connected to INPA and INPB, for Phase measurement P = P unless otherwis ..
AD8303AN ,+3 V, Dual, Serial Input Complete 12-Bit DACCHARACTERISTICSDNL < ±1 LSB 2.7 3.0 5.5 VPower Supply Range VDD RANGEShutdown Supply Current I SHDN ..
AD8303AR ,+3 V, Dual, Serial Input Complete 12-Bit DACCHARACTERISTICSPower Supply Range V DNL < ±1 LSB 2.7 5.5 VDD RANGEShutdown Current I SHDN = 0, No L ..
AD8304ARU ,160 dB Range (100 pA -10 mA) Logarithmic ConverterSPECIFICATIONS (V = 5 V, V = 0 V, T = 25C, unless otherwise noted.)P N A1 1Parameter Conditions Mi ..
AD8304ARUZ , 160 dB Range (100 pA -10 mA) Logarithmic Converter

AD1837AS
2 ADC, 8 DAC, 96 kHz, 24-Bit Codec
REV.B
2 ADC, 8 DAC,
96 kHz, 24-Bit �-� Codec
FEATURES
5 V Stereo Audio System with 3.3 V Tolerant
Digital Interface
Supports up to 96 kHz Sample Rates
192 kHz Sample Rate Available on One DAC
Supports 16-/20-/24-Bit Word Lengths
Multibit �-� Modulators with
Perfect Differential Linearity Restoration for
Reduced Idle Tones and Noise Floor
Data Directed Scrambling DACs—Least
Sensitive to Jitter
Single-Ended Outputs
ADCs: –95 dB THD + N, 105 dB SNR and
Dynamic Range
DACs: –92 dB THD + N, 108 dB SNR and
Dynamic Range
On-Chip Volume Controls per Channel with
1024-Step Linear Scale
DAC and ADC Software Controllable Clickless Mutes
Digital De-emphasis Processing
Supports 256 � fS, 512 � fS, and 768 � fS Master Mode
Clocks
Power-Down Mode Plus Soft Power-Down Mode
Flexible Serial Data Port with Right-Justified, Left-
Justified, I2S Compatible, and DSP Serial Port Modes
TDM Interface Mode Supports 8 In/8 Out Using a
Single SHARC® SPORT
52-Lead MQFP Plastic Package
FUNCTIONAL BLOCK DIAGRAM
OUTL1
FILTD
FILTR
ADCLP
ADCLN
ADCRP
ADCRN
DLRCLK
DBCLK
DSDATA1
DSDATA2
DSDATA3
DSDATA4
MCLKASDATAABCLKALRCLKODVDDDVDDAVDDAVDDDVDD
AGNDAGNDAGNDAGNDDGNDDGND
CINCLATCHCCLKCOUT
PD/RSTM/S
OUTR1
OUTL2
OUTR2
OUTL3
OUTR3
OUTL4
OUTR4
APPLICATIONS
DVD Video and Audio Players
Home Theater Systems
Automotive Audio Systems
Audio/Visual Receivers
Digital Audio Effects Processors
PRODUCT OVERVIEW
The AD1837 is a high performance single-chip codec featuring
four stereo DACs and one stereo ADC. Each DAC comprises a
high performance digital interpolation filter, a multibit �-�
modulator featuring Analog Devices’ patented technology, and
a continuous-time voltage out analog section. Each DAC has
independent volume control and clickless mute functions. The
ADC comprises two 24-bit conversion channels with multibit
�-� modulators and decimation filters.
The AD1837 also contains an on-chip reference with a nominal
value of 2.25 V.
The AD1837 contains a flexible serial interface that allows for
glueless connection to a variety of DSP chips, AES/EBU receiv-
ers, and sample rate converters. The AD1837 can be configured
in left-justified, right-justified, I2S, or DSP compatible serial
modes. Control of the AD1837 is achieved by means of an SPI
compatible serial port. While the AD1837 can be operated from
a single 5 V supply, it also features a separate supply pin for its
digital interface that allows the device to be interfaced to other
devices using 3.3 V power supplies.
The AD1837 is available in a 52-lead MQFP package and is
specified for the industrial temperature range of –40ºC to +85ºC.
AD1837–SPECIFICATIONS
TEST CONDITIONS
Supply Voltages (AVDD, DVDD)5.0 V
Ambient Temperature25∞C
Input Clock12.288 MHz, (256 ¥ fS Mode)
ADC Input Signal1.0078125 kHz, –1 dBFS (Full Scale)
DAC Input Signal1.0078125 kHz, 0 dBFS (Full Scale)
Input Sample Rate (fS)48 kHz
Measurement Bandwidth20 Hz to 20 kHz
Word Width24 Bits
Load Capacitance100 pF
Load Impedance47 kW
Performance of all channels is identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications).
ADC DECIMATION FILTER, 48 kHz*
AD1837
*Guaranteed by design.
Specifications subject to change without notice.
AD1837
TIMING SPECIFICATIONS
AD1837
Specifications subject to change without notice.
Figure 1.MCLK and PD/RST Timing
AD1837
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD1837 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*
(TA = 25∞C, unless otherwise noted.)
AVDD, DVDD, ODVDD to AGND, DGND . . . .–0.3 V to +6.0 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital I/O Voltage to DGND . . . . . –0.3 V to ODVDD + 0.3 V
Analog I/O Voltage to AGND . . . . . . –0.3 V to AVDD + 0.3 V
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . . –40∞C to +85∞C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
TEMPERATURE RANGE
Parameter
Specifications
Functionality
Storage
ORDERING GUIDE
PIN CONFIGURATION
AGND
AVDD
OUTR2
OUTL2
OUTR1
OUTL1
PD/RST
CIN
CLATCH
DVDD
OUTL3
OUTR3
OUTL4
OUTR4
AGND
DLRCLK
DBCLK
DGND
FILTDFILTR
AGND
M/S
AGND
AVDD
ADCLNADCLP
ADCRN
ADCRP
AGND
AGND
DGNDCCLKCOUTASDATAODVDDMCLKALRCLKABCLKDSDATA4DSDATA3DSDATA2DSDATA1
DVDD
AVDD
NC � NO CONNECT
PIN FUNCTION DESCRIPTIONS
40, 52
41–44
AD1837–Typical Performance Characteristics
TPC 1.ADC Composite Filter Response
TPC 2.ADC High-Pass Filter Response, fS = 48 kHz
TPC 3.ADC Composite Filter Response
(Pass-Band Section)
TPC 4.ADC High-Pass Filter Response, fS = 96 kHz
TPC 5.DAC Composite Filter Response, fS = 48 kHz
TPC 6.DAC Composite Filter Response, fS = 96 kHz
TPC 7.DAC Composite Filter Response, fS = 192 kHz
TPC 8.DAC Composite Filter Response, fS = 48 kHz
(Pass-Band Section)
TPC 9.DAC Composite Filter Response, fS = 96 kHz
(Pass-Band Section)
TPC 10.DAC Composite Filter Response, fS = 192 kHz
(Pass-Band Section)
AD1837
TERMINOLOGY
Dynamic Range
The ratio of a full-scale input signal to the integrated input noise
in the pass band (20 Hz to 20 kHz), expressed in decibels (dB).
Dynamic range is measured with a –60 dB input signal and is
equal to (S/[THD + N]) + 60 dB. Note that spurious harmon-
ics are below the noise with a –60 dB input, so the noise level
establishes the dynamic range. The dynamic range is specified
with and without an A-Weight filter applied.
Signal-to-(Total Harmonic Distortion + Noise)
[S/(THD + N)]
The ratio of the root-mean-square (rms) value of the fundamental
input signal to the rms sum of all other spectral components in
the pass band, expressed in decibels (dB).
Pass Band
The region of the frequency spectrum unaffected by the attenu-
ation of the digital decimator’s filter.
Pass-Band Ripple
The peak-to-peak variation in amplitude response from equal-
amplitude input signal frequencies within the pass band, expressed
in decibels.
Stop Band
The region of the frequency spectrum attenuated by the digital
decimator’s filter to the degree specified by stop-band attenuation.
Gain Error
With a near full-scale input, the ratio of actual output to expected
output, expressed as a percentage.
Interchannel Gain Mismatch
With identical near full-scale inputs, the ratio of outputs of the
two stereo channels, expressed in decibels.
Gain Drift
Change in response to a near full-scale input with a change in
temperature, expressed as parts-per-million (ppm) per ∞C.
Crosstalk (EIAJ Method)
Ratio of response on one channel with a grounded input to a
full-scale 1 kHz sine wave input on the other channel, expressed
in decibels.
Power Supply Rejection
With no analog input, signal present at the output when a
300 mV p-p signal is applied to power supply pins, expressed in
decibels of full scale.
Group Delay
Intuitively, the time interval required for an input pulse to
appear at the converter’s output, expressed in milliseconds (ms).
More precisely, the derivative of radian phase with respect to
radian frequency at a given frequency.
Group Delay Variation
The difference in group delays at different input frequencies.
Specified as the difference between the largest and the smallest
group delays in the pass band, expressed in microseconds (ms).
Acronyms
ADC—Analog-to-Digital Converter
DAC—Digital-to-Analog Converter
DSP—Digital Signal Processor
IMCLK—Internal Master Clock signal used to clock the ADC
and DAC engines
MCLK—External Master Clock signal applied to the AD1837
FUNCTIONAL OVERVIEW
ADCs
There are two ADC channels in the AD1837, configured as a
stereo pair. Each ADC has fully differential inputs. The ADC
section can operate at a sample rate of up to 96 kHz. The ADCs
include on-board digital decimation filters with 120 dB stop-band
attenuation and linear phase response, operating at an over-
sampling ratio of 128 (for 48 kHz operation) or 64 (for 96kHz
operation).
ADC peak level information for each ADC may be read from
the ADC Peak 0 and ADC Peak 1 registers. The data is supplied
as a 6-bit word with a maximum range of 0 dB to –63 dB and a
resolution of 1 dB. The registers will hold peak information until
read; after reading, the registers are reset so that new peak
information can be acquired. Refer to the register description
for details on the format. The two ADC channels have a common
serial bit clock and a left-right framing clock. The clock signals
are all synchronous with the sample rate.
The ADC digital pins, ABCLK and ALRCLK, can be set to
operate as inputs or outputs by connecting the M/S pin to
ODVDD or DGND, respectively. When the pins are set as
outputs, the AD1837 will generate the timing signals. When
the pins are set as inputs, the timing must be generated by the
external audio controller.
DACs
The AD1837 has eight DAC channels arranged as four inde-
pendent stereo pairs, with eight single-ended analog outputs for
improved noise and distortion performance. Each channel has
its own independently programmable attenuator, adjustable in
1024 linear steps. Digital inputs are supplied through four serial
data input pins (one for each stereo pair) and a common frame
(DLRCLK) and bit (DBLCK) clock. Alternatively, one of the
“packed data” modes may be used to access all eight channels
on a single TDM data pin. A stereo replicate feature is included
where the DAC data sent to the first DAC pair is also sent to the
other DACs in the part. The AD1837 can accept DAC data at a
sample rate of 192 kHz on DAC 1 only. The stereo replicate fea-
ture can then be used to copy the audio data to the other DACs.
Each of the output pins sits at a dc level of VREF and swings±1.4V for a 0 dB digital input signal. A single op amp third
order external low-pass filter is recommended to remove high
frequency noise present on the output pins. Note that the use of
op amps with low slew rate or low bandwidth may cause high
frequency noise and tones to fold down into the audio band;
care should be exercised in selecting these components.
The FILTD pin should be connected to an external grounded
capacitor. This pin is used to reduce the noise of the internal
DAC bias circuitry, thereby reducing the DAC output noise. In
some cases, this capacitor may be eliminated with little effect
on performance.
DAC and ADC Coding
The DAC and ADC output data stream is in a twos complement
encoded format. The word width can be selected from 16-bit,
20-bit, or 24-bit. The coding scheme is detailed in Table I.
Table I.Coding Scheme
Clock Signals
The DAC and ADC engines in the AD1837 are designed to
operate from a 24.576 MHz internal master clock (IMCLK).
This clock is used to generate 48 kHz and 96 kHz sampling on
the ADC and 48 kHz, 96 kHz, and 192 kHz on the DAC,
although the 192 kHz option is available only on one DAC pair.
The stereo replicate feature can be used to copy this DAC data
to the other DACs if required.
To facilitate the use of different MCLK values, the AD1837
provides a clock scaling feature. The MCLK scaler can be
programmed via the SPI port to scale the MCLK by a factor of
1 (pass through), 2 (doubling), or 2/3. The default setting of
the MCLK scaler is 2, which will generate 48 kHz sampling
from a 12.288 MHz MCLK. Additional sample rates can be
achieved by changing the MCLK value. For example, the CD
standard sampling frequency of 44.1 kHz can be achieved using
an 11.2896 kHz MCLK. Figure 2 shows the internal configura-
tion of the clock scaler and converter engines.
AD1837
To maintain the highest performance possible, it is recommended
that the clock jitter of the master clock signal be limited to less
than 300 ps rms, measured using the edge-to-edge technique.
Even at these levels, extra noise or tones may appear in the DAC
outputs if the jitter spectrum contains large spectral peaks. It is
highly recommended that the master clock be generated by an
independent crystal oscillator. In addition, it is especially important
that the clock signal should not be passed through an FPGA or
other large digital chip before being applied to the AD1837. In
most cases, this will induce clock jitter due to the fact that the
clock signal is sharing common power and ground connections
with other unrelated digital output signals.
RESET and Power-Down
PD/RST will power down the chip and set the control regis-
ters to their default settings. After PD/RST is deasserted, an
initialization routine will run inside the AD1837 to clear all
memories to zero. This initialization lasts for approximately
20 LRCLK intervals. During this time, it is recommended that
no SPI writes occur.
Power Supply and Voltage Reference
The AD1837 is designed for 5 V supplies. Separate power supply
pins are provided for the analog and digital sections. These pins
should be bypassed with 100 nF ceramic chip capacitors, as close
to the pins as possible, to minimize noise pickup. A bulk alumi-
num electrolytic capacitor of at least 22 mF should also be provided
on the same PC board as the codec. For critical applications,
improved performance will be obtained with separate supplies for
the analog and digital sections. If this is not possible, it is recom-
mended that the analog and digital supplies be isolated by means of
two ferrite beads in series with the bypass capacitor of each supply.is important that the analog supply be as clean as possible.
The internal voltage reference is brought out on the FILTR pin
and should be bypassed as close as possible to the chip, with a
parallel combination of 10 mF and 100 nF. The reference voltage
may be used to bias external op amps to the common-mode
voltage of the analog input and output signal pins. The current
drawn from the FILTR pin should be limited to less than 5 mA.
Serial Control Port
The AD1837 has an SPI® compatible control port to permit
programming the internal control registers for the ADCs and
DACs and for reading the ADC signal levels from the internal
peak detectors. The SPI control port is a 4-wire serial control
port. The format is similar to the Motorola SPI format except the
input data-word is 16 bits wide. The maximum serial bit clock
frequency is 12.5 MHz and may be completely asynchronous to
the sample rate of the ADCs and DACs. Figure 3 shows the
format of the SPI signal.
Serial Data Ports—Data Format
The ADC serial data output mode defaults to the popular I2S
format, where the data is delayed by 1 BCLK interval from the
edge of the LRCLK. By changing Bits 6 to 8 in ADC Control
Register 2, the serial mode can be changed to right-justified
(RJ), left-justified DSP (DSP), or left-justified (LJ). In the RJ
mode, it is necessary to set Bits 4 and 5 to define the width of
the data-word.
The DAC serial data input mode defaults to I2S. By changing
Bits 5, 6, and 7 in DAC Control Register 1, the mode can be
changed to RJ, DSP, LJ, Packed Mode 1, or Packed Mode 2.
The word width defaults to 24 bits but can be changed by
reprogramming Bits 3 and 4 in DAC Control Register 1.
Packed Modes
The AD1837 has a packed mode that allows a DSP or other
controller to write to all DACs and read all ADCs using one
input data pin and one output data pin. Packed Mode 256
refers to the number of BCLKs in each frame. The LRCLK is
low while data from a left channel DAC or ADC is on the data
pin and high while data from a right channel DAC or ADC is
on the data pin. DAC data is applied on the DSDATA1 pin and
ADC data is available on the ASDATA pin. Figures 7 to 10
show the timing for the packed mode. Packed mode is available
only for 48 kHz (based on MCLK = 12.288 MHz) and when
the ADC is set as a master (M/S=0).
Auxiliary (TDM) Mode
A special auxiliary mode is provided to allow three external
stereo ADCs to be interfaced to the AD1837 to provide 8-in/8-out
operation. In addition, this mode supports glueless interface to a
single SHARC DSP serial port, allowing a SHARC DSP to
access all eight channels of analog I/O. In this special mode,
many pins are redefined; see Table II for a list of redefined pins.
The auxiliary and the TDM interfaces are independently config-
urable to operate as masters or slaves. When the auxiliary interface
is set as a master, by programming the Aux Mode bit in ADC
Control Register 2, AUXLRCLK and AUXBCLK are generated
by the AD1837. When the auxiliary interface is set as a slave, the
AUXLRCLK and AUXBCLK need to be generated by an external
ADC as shown in Figure 13.
The TDM interface can be set to operate as a master or slave by
connecting the M/S pin to DGND or ODVDD, respectively. In
master mode, the FSTDM and BCLK signals are outputs and
are generated by the AD1837. In slave mode, the FSTDM and
BCLK are inputs and should be generated by the SHARC. Slave
mode operation is available for 48 kHz and 96 kHz operation
(based on a 12.288 MHz or 24.576 MHz MCLK), and master
mode operation is available for 48 kHz only.

Partno	Mfg	Dc	Qty	Available	Descript
AD1837AS	ADI	N/a	2400	avai	2 ADC, 8 DAC, 96 kHz, 24-Bit Codec