AD1837AAS-AD1837AASZ Fast Delivery |IC PHOENIX CO.,LIMITED

AD1837AAS ,2 ADC, 8 DAC, 96 kHz, 24-Bit Sigma Delta CODECGENERAL DESCRIPTIONPerfect Differential Linearity Restoration forThe AD1837A is a high performance ..
AD1837AASZ ,2 ADC, 8 DAC, 96 kHz, 24-Bit Sigma Delta CODECspecifications).Parameter Min Typ Max UnitANALOG-TO-DIGITAL CONVERTERSADC Resolution 24 BitsDynamic ..
AD1837AS ,2 ADC, 8 DAC, 96 kHz, 24-Bit Codecspecifications).Parameter Min Typ Max UnitANALOG-TO-DIGITAL CONVERTERSADC Resolution 24 BitsDynamic ..
AD1838AAS ,2 ADC, 6 DAC 96 kHz, 24-Bit Sigma Delta CodecSPECIFICATIONSAD1838ATEST CONDITIONSSupply Voltages (AVDD, DVDD) 5.0 VAmbient Temperature 25°CInput ..
AD1838AS ,Please see the AD1838A.specifications).Parameter Min Typ Max UnitANALOG-TO-DIGITAL CONVERTERSADC Resolution 24 BitsDynamic ..
AD1839AAS ,2 ADC, 6 DAC 96 kHz, 24-Bit Sigma Delta Codecfeatures three stereo DACs and one stereo ADC. Each DAC 192 kHz sample rate available on 1 DAC comp ..
AD8300ARZ ,+3 Volt, Serial Input Complete 12-Bit DACapplications.The AD8300 is specified over the extended industrial (–40

AD1837AAS-AD1837AASZ
2 ADC, 8 DAC, 96 kHz, 24-Bit Sigma Delta CODEC
REV.A
2 ADC, 8 DAC,
96 kHz, 24-Bit �-� Codec
FEATURES
5 V Stereo Audio System with 3.3 V Tolerant
Digital Interface
Supports up to 96 kHz Sample Rates
192 kHz Sample Rate Available on 1 DAC
Supports 16-, 20-, 24-Bit Word Lengths
Multibit �-� Modulators with
Perfect Differential Linearity Restoration for
Reduced Idle Tones and Noise Floor
Data Directed Scrambling DACs—Least
Sensitive to Jitter
Single-Ended Outputs
ADCs: –95 dB THD + N, 105 dB SNR and
Dynamic Range
DACs: –92 dB THD + N, 108 dB SNR and
Dynamic Range
On-Chip Volume Controls per Channel with
1024-Step Linear Scale
DAC and ADC Software Controllable Clickless Mutes
Digital De-emphasis Processing
Supports 256 � fS, 512 � fS, and 768 � fS Master
Mode Clocks
Power-Down Mode Plus Soft Power-Down Mode
Flexible Serial Data Port with Right-Justified, Left-
Justified, I2S Compatible, and DSP Serial Port
Modes
TDM Interface Mode Supports 8 In/8 Out Using a
Single SHARC® SPORT
52-Lead MQFP Plastic Package
APPLICATIONS
DVD Video and Audio Players
Home Theater Systems
Automotive Audio Systems
Audio/Visual Receivers
Digital Audio Effects Processors
FUNCTIONAL BLOCK DIAGRAM
OUTL1
FILTD
FILTR
ADCLP
ADCLN
ADCRP
ADCRN
DLRCLK
DBCLK
DSDATA1
DSDATA2
DSDATA3
DSDATA4
MCLKASDATAABCLKALRCLKODVDDDVDDAVDDAVDDDVDD
AGNDAGNDAGNDAGNDDGNDDGND
CINCLATCHCCLKCOUT
PD/RSTM/S
OUTR1
OUTL2
OUTR2
OUTL3
OUTR3
OUTL4
OUTR4
AD1837A
GENERAL DESCRIPTION
The AD1837A is a high performance single-chip codec featuring
four stereo DACs and one stereo ADC. Each DAC comprises a
high performance digital interpolation filter, a multibit �-�
modulator featuring Analog Devices’ patented technology, and a
continuous-time voltage out analog section. Each DAC has inde-
pendent volume control and clickless mute functions. The ADC
comprises two 24-bit conversion channels with multibit S-D
modulators and decimation filters.
The AD1837A also contains an on-chip reference with a nominal
value of 2.25 V.
The AD1837A contains a flexible serial interface that allows for
glueless connection to a variety of DSP chips, AES/EBU receivers,
and sample rate converters. The AD1837A can be configured in
left-justified, right-justified, I2S, or DSP compatible serial modes.
Control of the AD1837A is achieved by means of an SPI compat-
ible serial port. While the AD1837A can be operated from a single
5 V supply, it also features a separate supply pin for its digital inter-
face, which allows the device to be interfaced to other devices using
3.3 V power supplies.
The AD1837A is available in a 52-lead MQFP package and is speci-
fied for the industrial temperature range of –40ºC to +85ºC.
AD1837A–SPECIFICATIONS
Performance of all channels is identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation
specifications).
TEST CONDITIONS
Supply Voltages (AVDD, DVDD)5.0 V
Ambient Temperature25∞C
Input Clock12.288 MHz, (256 � fS Mode)
ADC Input Signal1.0078125 kHz, –1 dBFS (Full Scale)
DAC Input Signal1.0078125 kHz, 0 dBFS (Full Scale)
Input Sample Rate (fS)48 kHz
Measurement Bandwidth20 Hz to 20 kHz
Word Width24 Bits
Load Capacitance100 pF
Load Impedance47 kW
AD1837A
*Guaranteed by design.
Specifications subject to change without notice.
AD1837A
TIMING SPECIFICATIONS
AD1837A
Specifications subject to change without notice.
Figure 1.MCLK and PD/RST Timing
AD1837A
TEMPERATURE RANGE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD1837A features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*
(TA = 25∞C, unless otherwise noted.)
AVDD, DVDD, ODVDD to AGND, DGND
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +6 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital I/O Voltage to DGND . . . –0.3 V to ODVDD + 0.3 V
Analog I/O Voltage to AGND . . . . . –0.3 V to AVDD + 0.3 V
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . –40∞C to +85∞C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
*Z = Pb free part.
PIN CONFIGURATION
AGND
AVDD
OUTR2
OUTL2
OUTR1
OUTL1
PD/RST
CIN
CLATCH
DVDD
OUTL3
OUTR3
OUTL4
OUTR4
AGND
DLRCLK
DBCLK
DGND
FILTDFILTR
AGND
M/S
AGND
AVDD
ADCLNADCLP
ADCRN
ADCRP
AGND
AGND
DGNDCCLKCOUTASDATAODVDDMCLKALRCLKABCLKDSDATA4DSDATA3DSDATA2DSDATA1
DVDD
AVDD
NC = NO CONNECT
PIN FUNCTION DESCRIPTIONS
5, 10, 16, 24, 30, 35
6, 12, 25, 31
7, 13, 26, 32
8, 14, 27, 33
9, 15, 28, 34
11, 19, 29
AD1837A
TPC 1.ADC Composite Filter Response
TPC 2.ADC High-Pass Filter Response, fS = 48 kHz
TPC 3.ADC Composite Filter Response
(Pass-Band Section)
TPC 4.ADC High-Pass Filter Response, fS = 96 kHz
TPC 5.DAC Composite Filter Response, fS = 48 kHz
TPC 6.DAC Composite Filter Response, fS = 96 kHz
–Typical Performance Characteristics
TPC 7.DAC Composite Filter Response, fS = 192 kHz
TPC 8.DAC Composite Filter Response, fS = 48 kHz
(Pass-Band Section)
TPC 9.DAC Composite Filter Response, fS = 96 kHz
(Pass-Band Section)
TPC 10.DAC Composite Filter Response, fS = 192 kHz
(Pass-Band Section)
AD1837A
TERMINOLOGY
Dynamic Range
The ratio of a full-scale input signal to the integrated input noise
in the pass band (20 Hz to 20 kHz), expressed in decibels (dB).
Dynamic range is measured with a –60 dB input signal and is
equal to (S/[THD + N]) + 60 dB. Note that spurious harmonics
are below the noise with a –60 dB input, so the noise level
establishes the dynamic range. The dynamic range is specified
with and without an A-weight filter applied.
Signal-to-(Total Harmonic Distortion + Noise)
[S/(THD + N)]
The ratio of the root-mean-square (rms) value of the funda-
mental input signal to the rms sum of all other spectral compo-
nents in the pass band, expressed in decibels (dB).
Pass Band
The region of the frequency spectrum unaffected by the attenu-
ation of the digital decimator’s filter.
Pass-Band Ripple
The peak-to-peak variation in amplitude response from equal-
amplitude input signal frequencies within the pass band, expressed
in decibels.
Stop Band
The region of the frequency spectrum attenuated by the
digital decimator’s filter to the degree specified by stop-band
attenuation.
Gain Error
With a near full-scale input, the ratio of actual output to expected
output, expressed as a percentage.
Interchannel Gain Mismatch
With identical near full-scale inputs, the ratio of outputs of the
two stereo channels, expressed in decibels.
Gain Drift
Change in response to a near full-scale input with a change in
temperature, expressed as parts-per-million (ppm) per ∞C.
Crosstalk (EIAJ Method)
Ratio of response on one channel with a grounded input to a
full-scale 1 kHz sine wave input on the other channel, expressed
in decibels.
Power Supply Rejection
With no analog input, signal present at the output when a
300 mV p-p signal is applied to power supply pins, expressed
in decibels of full scale.
Group Delay
Intuitively, the time interval required for an input pulse to
appear at the converter’s output, expressed in microseconds
(ms). More precisely, the derivative of radian phase with
respect to radian frequency at a given frequency.
Group Delay Variation
The difference in group delays at different input frequencies.
Specified as the difference between largest and the smallest
group delays in the pass band, expressed in microseconds (ms).
ACRONYMS
ADC—Analog-to-Digital Converter.
DAC—Digital-to-Analog Converter.
DSP—Digital Signal Processor.
IMCLK—Internal Master Clock Signal used to clock the ADC
and DAC engines.
MCLK—External Master Clock Signal applied to the AD1837A.
FUNCTIONAL OVERVIEW
ADCs
There are two ADC channels in the AD1837A, configured as a
stereo pair. Each ADC has fully differential inputs. The ADC
section can operate at a sample rate of up to 96 kHz. The ADCs
include on-board digital decimation filters with 120 dB stop-band
attenuation and linear phase response, operating at an oversam-
pling ratio of 128 (for 48 kHz operation) or 64 (for 96kHz
operation).
ADC peak level information for each ADC may be read from the
ADC Peak 0 and ADC Peak 1 registers. The data is supplied as
a 6-bit word with a maximum range of 0 dB to –63 dB and a
resolution of 1 dB. The registers will hold peak information until
read; after reading, the registers are reset so that new peak
information can be acquired. Refer to the register description
for details on the format. The two ADC channels have a com-
mon serial bit clock and a left-right framing clock. The clock
signals are all synchronous with the sample rate.
The ADC digital pins, ABCLK and ALRCLK, can be set to
operate as inputs or outputs by connecting the M/S pin to
ODVDD or DGND, respectively. When the pins are set as
outputs, the AD1837A will generate the timing signals. When
the pins are set as inputs, the timing must be generated by
the external audio controller.
DACs
The AD1837A has eight DAC channels arranged as four inde-
pendent stereo pairs, with eight single-ended analog outputs for
improved noise and distortion performance. Each channel has
its own independently programmable attenuator, adjustable in
1024 linear steps. Digital inputs are supplied through four serial
data input pins (one for each stereo pair) and a common frame
(DLRCLK) and bit (DBLCK) clock. Alternatively, one of the
packed data modes may be used to access all eight channels on a
single TDM data pin. A stereo replicate feature is included where
the DAC data sent to the first DAC pair is also sent to the
other DACs in the part. The AD1837A can accept DAC data at
a sample rate of 192 kHz on DAC 1 only. The stereo repli-
cate feature can then be used to copy the audio data to the
other DACs.
Each of the output pins sits at a dc level of VREF and swings±1.4 V for a 0 dB digital input signal. A single op amp third-
order external low-pass filter is recommended to remove high
frequency noise present on the output pins. Note that the use of
op amps with low slew rate or low bandwidth may cause high
frequency noise and tones to fold down into the audio band;
care should be exercised in selecting these components.
The FILTD pin should be connected to an external grounded
capacitor. This pin is used to reduce the noise of the internal
DAC bias circuitry, thereby reducing the DAC output noise. In
some cases, this capacitor may be eliminated with little affect
on performance.
DAC and ADC Coding
The DAC and ADC output data stream is in a twos comple-
ment encoded format. The word width can be selected from
16 bit, 20 bit, or 24 bit. The coding scheme is detailed
in Table I.
Table I.Coding Scheme
AD1837A CLOCKING SCHEME
By default, the AD1837A requires an MCLK signal that is
256 times the required sample frequency up to a maximum of
12.288 MHz. The AD1837A uses a clock scaler to double the
clock frequency for internal use. The default setting of the clock
scaler is multiply by two. The clock scaler can also be set to
multiply by 1 (bypass) or multiply by 2/3. The internal MCLK
signal, IMCLK, should not exceed 24.576 MHz in order to
ensure correct operation.
The MCLK of the AD1837A should remain constant during
normal operation of the DAC and ADC. If it is required to
change the MCLK rate, the AD1837A should be reset. Addition-
ally, if MCLK scaler needs to be modified so that the IMCLK
does not exceed 24.576 MHz, this should be done during the
internal reset phase of the AD1837A by programming the bits in
the first 3072 MCLK periods following the reset.
Selecting DAC Sampling Rate
The AD1837A DAC engine has a programmable interpolator
that allows the user to select different interpolation rates
based on the required sample rate and MCLK value avail-
able. Table II shows the settings required for sample rates
based on a fixed MCLK of 12.288 MHz.
Table II. DAC Sample Rate Settings
Selecting an ADC Sample Rate
The AD1837A ADC engine has a programmable decimator
that allows the user to select the sample rate based on the
MCLK value. By default, the output sample rate is IMCLK/
512. To achieve a sample rate of IMCLK/256, the sample
rate bit in the ADC Control 1 register should be set as shown
in Table III.
Table III. ADC Sample Rate Settings
To maintain the highest performance possible, it is recommended
that the clock jitter of the master clock signal be limited to less
than 300 ps rms, measured using the edge-to-edge technique.
Even at these levels, extra noise or tones may appear in the
AD1837A
Figure 2.Modulator Clocking Scheme
Figure 3.Format of SPI Timing
DAC outputs if the jitter spectrum contains large spectral peaks.
It is highly recommended that the master clock be generated by
an independent crystal oscillator. In addition, it is especially
important that the clock signal not be passed through an FPGA
or other large digital chip before being applied to the AD1837A.
In most cases, this will induce clock jitter due to the fact that
the clock signal is sharing common power and ground connec-
tions with other unrelated digital output signals.
Power-Down and RESET
PD/RST powers down the chip and sets the control registers to
their default settings. After PD/RST is de-asserted, an initialization
routine runs inside the AD1837A to clear all memories to zero.
This initialization lasts for approximately 20 LRCLK intervals.
During this time, it is recommended that no SPI writes occur.
Power Supply and Voltage Reference
The AD1837A is designed for 5 V supplies. Separate power
supply pins are provided for the analog and digital sections.
These pins should be bypassed with 100 nF ceramic chip capaci-
tors, as close to the pins as possible, to minimize noise pickup. A
bulk aluminum electrolytic capacitor of at least 22 mF should also
means of two ferrite beads in series with the bypass capacitor of
each supply. Itis important that the analog supply be as clean
as possible.
The internal voltage reference is brought out on the FILTR pin
and should be bypassed as close as possible to the chip, with a
parallel combination of 10 mF and 100 nF. The reference voltage
may be used to bias external op amps to the common-mode
voltage of the analog input and output signal pins. The current
drawn from the VREF pin should be limited to less than 50 mA.
Serial Control Port
The AD1837A has an SPI compatible control port to permit
programming the internal control registers for the ADCs and
DACs and for reading the ADC signal levels from the internal
peak detectors. The SPI control port is a 4-wire serial control port.
The format is similar to the Motorola SPI format except the
input data-word is 16 bits wide. The maximum serial bit clock
frequency is 12.5 MHz and may be completely asynchronous to
the sample rate of the ADCs and DACs. Figure 3 shows the
format of the SPI signal.
Serial Data Ports—Data Format

Partno	Mfg	Dc	Qty	Available	Descript
AD1837AAS	AD	N/a	2	avai	2 ADC, 8 DAC, 96 kHz, 24-Bit Sigma Delta CODEC
AD1837AASZ	AD	N/a	2	avai	2 ADC, 8 DAC, 96 kHz, 24-Bit Sigma Delta CODEC