AD1836AS Fast Delivery |IC PHOENIX CO.,LIMITED

AD1836AS ,Multichannel 96 kHz CodecGENERAL DESCRIPTIONDACs: –95 dB THD + N, 108 dB SNR and Dynamic RangeThe AD1836 is a high-performan ..
AD1837AAS ,2 ADC, 8 DAC, 96 kHz, 24-Bit Sigma Delta CODECGENERAL DESCRIPTIONPerfect Differential Linearity Restoration forThe AD1837A is a high performance ..
AD1837AASZ ,2 ADC, 8 DAC, 96 kHz, 24-Bit Sigma Delta CODECspecifications).Parameter Min Typ Max UnitANALOG-TO-DIGITAL CONVERTERSADC Resolution 24 BitsDynamic ..
AD1837AS ,2 ADC, 8 DAC, 96 kHz, 24-Bit Codecspecifications).Parameter Min Typ Max UnitANALOG-TO-DIGITAL CONVERTERSADC Resolution 24 BitsDynamic ..
AD1838AAS ,2 ADC, 6 DAC 96 kHz, 24-Bit Sigma Delta CodecSPECIFICATIONSAD1838ATEST CONDITIONSSupply Voltages (AVDD, DVDD) 5.0 VAmbient Temperature 25°CInput ..
AD1838AS ,Please see the AD1838A.specifications).Parameter Min Typ Max UnitANALOG-TO-DIGITAL CONVERTERSADC Resolution 24 BitsDynamic ..
AD8300ARZ ,+3 Volt, Serial Input Complete 12-Bit DACapplications.The AD8300 is specified over the extended industrial (–40

AD1836AS
Multichannel 96 kHz Codec
PRELIMINARY TECHNICAL DATA
REV.PrC
Multichannel 96kHz Codec
FUNCTIONAL BLOCK DIAGRAM
AOUT1
AOUT2
MCLKCOUT
FILTD
CCLKCDATACLATCH
DLRCLK
DBCLK
DSDATA1
DSDATA2
DSDATA3
ALRCLK
ABCLK
ASDATA1
ASDATA2
AIN1L
CAPL1
AIN2L1
AIN2L2
CAPL2
CAPR1
CAPR2
AIN2R1
AIN2R2
PWRDWN/RESETAVDDAGNDDVDDDGND
AIN1R
AOUT3
AOUT4
AOUT5
AOUT6
FILTR
FEATURESV Multichannel Audio System
Accepts 16-/18-/20-/24-Bit Data
Supports 24 Bits and 96kHz Sample Rate
Multibit Sigma-Delta Modulators with Data Directed
Scrambling
Data-Directed Scrambling ADCs and DACs—Least
Sensitive to Jitter
Differential Output for Optimum Performance
ADCs: –92 dB THD + N, 105 dB SNR and Dynamic Range
DACs: –95 dB THD + N, 108 dB SNR and Dynamic Range
On-Chip Volume Control with “Autoramp” Function
Programmable Gain Amplifier for ADC Input
Hardware and Software Controllable Clickless Mute
Digital De-Emphasis Processing
Supports 256 � fS, 512 � fS, or 768 � fS Master Clock
Power-Down Mode Plus Soft Power-Down Mode
Flexible Serial Data Port with Right-Justified, Left-
Justified, I2S-Compatible and DSP Serial Port Modes
TDM Interface Mode Supports 8 In/8 Out Using a
Single SHARC® SPORT
52-Lead MQFP (PQFP) Plastic Package
GENERAL DESCRIPTION
The AD1836 is a high-performance, single-chip codec pro-
viding three stereo DACs and two stereo ADCs using ADI’s
patented multibit sigma-delta architecture. An SPI port is
included, allowing a microcontroller to adjust volume and
many other parameters. The AD1836 operates from a 5 V
supply, with provision for a separate output supply to interface
with low-voltage external circuitry. The AD1836 is available
in a 52-lead MQFP (PQFP) package.
APPLICATIONS
Home Theatre Systems
Automotive Audio Systems
DVD
Set-Top Boxes
Digital Audio Effects Processors
SHARC is a registered trademark of Analog Device, Inc.
PRELIMINARY TECHNICAL DATA
AD1836–SPECIFICATIONS
TEST CONDITIONS UNLESS OTHERWISE NOTED
Supply Voltages (AVDD, DVDD)5.0V
Ambient Temperature25°C
Master Clock12.288MHz, (48kHz fS, 256 × fS Mode)
Input Signal1.000kHz, 0dBFS (Full Scale)
Input Sample Rate48kHz
Measurement Bandwidth20Hz to 20kHz
Word Width20 Bits
Load Capacitance100pF
Load Impedance47kΩ
Input Voltage HI2.4V
Input Voltage LO0.8V
NOTE
Performance of all channels are identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications).
ANALOG PERFORMANCE
PRELIMINARY TECHNICAL DATA
AD1836
DIGITAL FILTERS at 44.1kHz
TIMING
PRELIMINARY TECHNICAL DATA
AD1836–SPECIFICATIONS
TIMING (continued)
PRELIMINARY TECHNICAL DATA
AD1836
TIMING (continued)
POWER SUPPLIES
TEMPERATURE RANGE
Functionality Guaranteed
Specifications subject to change without notice.
PRELIMINARY TECHNICAL DATA
AD1836
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD1836 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*
(Human Body Model, Method 3015.2, MIL-STD-883B)
*Stresses greater than those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ORDERING INFORMATION
PIN CONFIGURATION
52-Lead MQFP
AGND
AVDD
ADC1INLP
ADC1INLNADC1INRN
CAPL2CAPL1
ADC2INL1ADC2INL2ADC2INR2ADC2INR1
CAPR1
DGNDCCLKCLATCHCOUTASDATA2ASDATA1ODVDDMCLKALRCLKABCLKDSDATA3DSDATA2DVDD
DVDD
CDATA
PD/RST
OUTLP3
OUTLN3
OUTLP2
OUTLN2
OUTLP1
OUTLN1
AVDD
AGND
FILTD
FILTR
DGND
DSDATA1
DBCLK
DLRCLK
OUTRP3
OUTRN3
OUTRP2
OUTRN2
OUTRP1
OUTRN1
AGND
AGND
CAPR2
ADC1INRP
PRELIMINARY TECHNICAL DATA
PIN FUNCTION DESCRIPTIONS
PRELIMINARY TECHNICAL DATA
AD1836
FUNCTIONAL OVERVIEW
ADCs
There are four ADC channels in the AD1836, configured as two
independent stereo pairs. One stereo pair is the primary ADC and
has fully differential inputs. The second pair can be programmed
to operate in one of three possible input modes (programmed
via SPI ADC Control Register 3). The ADC section may also
operate at a sample rate of 96 kHz, with only the two primary
channels active. The ADCs include an on-board digital decima-
tion filter with 120 dB stopband attenuation and linear phase
response, operating at an oversampling ratio of 128 (for 4-channel
48 kHz operation) or 64 (for two-channel 96 kHz operation).
The primary ADC pair should be driven from a differential
signal source for best performance. The input pins of the pri-
mary ADC connect directly to internal switched capacitors. To
isolate the external driving op amp from the “glitches” caused
by the internal switched-capacitors, each input pin should be
isolated by using a series-connected external 100 Ω resistor
together with a 1 nF capacitor connected from each input to
ground. This capacitor must be of high quality; for example,
ceramic NPO or polypropylene film.
The secondary input pair can be operated in one of the follow-
ing three modes:Direct differential inputs (driven the same as the primary
ADC inputs described above).PGA mode with differential inputs (Figure 13). In this mode,
the PGA amplifier can be programmed using the SPI port to
give an input gain of 0 to 12 dB in 3 dB steps. External
capacitors are used after the PGA to supply filtering for the
switched-capacitor inputs.Single-ended MUX/PGA mode. In this mode, two single-
ADC peak level information for each ADC may be read from
the SPI port through Registers 12 through 15. The data is sup-
plied as a 10-bit word with a maximum range of 0 dB to –60 dB
and a resolution of 1 dB. The registers will hold peak informa-
tion until read; after reading, the registers are reset so that new
peak information can be acquired. Refer to the register descrip-
tion for details of the format.
The voltage at the VREF pin, FILTR (~2.25 V) can be used to
bias external op amps used to buffer the input signals. This
source can be connected directly to op amp inputs but should
be buffered if it is required to drive resistive networks.
DACs
The AD1836 has six DAC channels arranged as three indepen-
dent stereo pairs, with six fully differential analog outputs for
improved noise and distortion performance. Each channel has
its own independently programmable attenuator, adjustable in
1024 linear steps. Digital inputs are supplied through three
serial data input pins (one for each stereo pair) and a common
frame (DLRCLK) and bit (DBLCK) clock. Alternatively, one
of the “packed data” modes may be used to access all six chan-
nels on a single TDM data pin.
Each set of differential output pins sits at a dc level of VREF, and
swings ±1.4 V for a 0 dB digital input signal. A single op amp
third-order external low-pass filter is recommended to remove
high-frequency noise present on the output pins, as well as to
provide differential-to-single-ended conversion. A recommended
circuit is shown in Figure 2. Note that the use of op amps with
low slew rate or low bandwidth may cause high-frequency noise
and tones to fold down into the audio band; care should be
exercised in selecting these components.
The FILTD pin should be connected to an external grounded
Figure 1.
PRELIMINARY TECHNICAL DATA
Figure 2.Format of SPI Signal
Clock Signals
The master clock frequency can be selected for 256, 512, or
768 times the sample rate. The default at power-up is 256 fS.
For operation at 96 kHz, the master clock frequency should
stay at the same absolute frequency. For example, if the AD1836
is programmed in 256 × fS mode and operated in the normal
48 kHz 4-channel mode, the frequency of the master-clock
would be 256 × 48 kHz = 12.288 MHz. If the AD1836 is then
switched to 96 kHz operation (via writing to the SPI port), the
frequency of the master-clock should remain at 12.288 MHz
(which is now 128 × fS).
The internal clock used in the AD1836 is 512 × fS (48 kHz
mode) or 512 × fS (96 kHz mode). Clock doublers are used to
generate this internal master-clock from the external clocks.
Since clock-doublers have a limited range of operation, it is
recommended that the part be operated in 512 × fS mode if the
desired sampling rates are not at all close to the common audio
sampling rates for which the part was designed.
To maintain the highest performance possible, it is recommended
that the clock jitter of the master clock signal be limited to less
than 300 ps rms, measured using the edge-to-edge technique.
Even at these levels, extra noise or tones may appear in the
DAC outputs if the jitter spectrum contains large spectral peaks.
It is highly recommended that the master clock be generated by
an independent crystal oscillator. In addition, it is especially
important that the clock signal should not be passed through an
FPGA or other large digital chip before being applied to the
AD1836. In most cases this will induce clock jitter due to the
fact that the clock signal is sharing common power and ground
connections with other unrelated digital output signals.
The six DAC channels use a common serial bit clock to clock in
the serial data and a common left-right framing clock. The four
ADC channels output a common serial bit clock and a left-right
framing clock. The clock signals are all synchronous with the
sample rate.
RESET and Power-Down
RESET will power down the chip and set the control registers
to their default settings. After reset is deasserted, an initialization
routine will run inside the AD1836 to clear all memories to zero.
This initialization lasts for approximately 20 LRCLK intervals.
During this time it is recommended that no SPI writes occur.
Serial Control Port
The AD1836 has an SPI-compatible control port to permit
programming the internal control registers for the ADCs and
DACs and for reading the ADC signal level from the internal
peak detectors. The DAC output levels may be independently
programmed by means of an internal digital attenuator adjust-
able in 1024 linear steps.
The SPI control port is a 4-wire serial control port. The format is
similar to the Motorola SPI format except the input data word
is 16-bits wide. Max serial bit clock frequency is 8 MHz and
may be completely asynchronous to the sample rate of the ADCs
and DACs. The following figure shows the format of the SPI
signal. Note that the CCLK should be run continuously and not
stop between SPI transactions.
Power Supply and Voltage Reference
The AD1836 is designed for 5 V supplies. Separate power sup-
ply pins are provided for the analog and digital sections. These
pins should be bypassed with 100 nF ceramic chip capacitors, as
close to the pins as possible, to minimize noise pickup. A bulk
aluminum electrolytic capacitor of at least 22 µF should also be
provided on the same PC board as the codec. For critical appli-
cations, improved performance will be obtained with separate
supplies for the analog and digital sections. If this is not pos-
sible, it is recommended that the analog and digital supplies be
isolated by means of two ferrite beads in series with the bypass
capacitor of each supply. It is important that the analog supply
be as clean as possible.
The internal voltage reference is brought out on Pin 13 (FILTR)
and should be bypassed as close as possible to the chip, with a
parallel combination of 10 µF and 100 nF. The reference volt-
age may be used to bias external op amps to the common-mode
voltage of the analog input and output signal pins. The current
drawn from the VREF pin should be limited to less than 50 µA.
Serial Data Ports—Data Format
The ADC serial data output mode defaults to the popular I2S
format, where the data is delayed by 1 BCLK interval from the
edge of the LRCLK. By changing Bits 8 and 9 in ADC Control
Register 2, the serial mode can be changed to Right-Justified
(RJ), Left-Justified DSP (DSP) or Left-Justified (LJ). In the RJ
mode, it is necessary to set Bits 6 and 7 to define the width of
the data word.
The DAC serial data input mode defaults to I2S. By changing
Bits 5, 6, and 7 in DAC Control Register 1, the mode can be
changed to RJ, DSP, LJ, Packed Mode 1 or Packed Mode 2.

Partno	Mfg	Dc	Qty	Available	Descript
AD1836AS	AD	N/a	5020	avai	Multichannel 96 kHz Codec