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AD1835AASZ ,2 ADC, 8 DAC, 96 kHz, 24-Bit Sigma Delta Codecspecifications).Parameter Min Typ Max UnitANALOG-TO-DIGITAL CONVERTERSADC Resolution 24 BitsDynamic ..
AD1836ACSZ , Multichannel 96 kHz Codec
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AD1837AASZ ,2 ADC, 8 DAC, 96 kHz, 24-Bit Sigma Delta CODECspecifications).Parameter Min Typ Max UnitANALOG-TO-DIGITAL CONVERTERSADC Resolution 24 BitsDynamic ..
AD1837AS ,2 ADC, 8 DAC, 96 kHz, 24-Bit Codecspecifications).Parameter Min Typ Max UnitANALOG-TO-DIGITAL CONVERTERSADC Resolution 24 BitsDynamic ..
AD829SQ/883B ,High-Speed, Low-Noise Video Op AmpApplications–IN 2 7 +VS0.02% Differential Gain+IN 3 6 OUTPUT0.04 Differential PhaseTOP VIEWLow Noi ..
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AD8300AR ,+3 Volt, Serial Input Complete 12-Bit DACapplications.The AD8300 is specified over the extended industrial (–40

AD1835AASZ
2 ADC, 8 DAC, 96 kHz, 24-Bit Sigma Delta Codec
REV.A
2 ADC, 8 DAC,
96 kHz, 24-Bit �-� Codecs
FEATURES
5 V Stereo Audio System with 3.3 V Tolerant Digital
Interface
Supports up to 96 kHz Sample Rates
192 kHz Sample Rate Available on 1 DAC
Supports 16-/20-/24-Bit Word Lengths
Multibit �-� Modulators with
Perfect Differential Linearity Restoration for
Reduced Idle Tones and Noise Floor
Data Directed Scrambling DACs—Least
Sensitive to Jitter
Differential Output for Optimum Performance
ADCs: –95 dB THD + N, 105 dB SNR, and
Dynamic Range
DACs: –95 dB THD + N, 108 dB SNR, and
Dynamic Range
On-Chip Volume Controls per Channel with
1024-Step Linear Scale
DAC and ADC Software Controllable Clickless Mutes
Digital De-emphasis Processing
FUNCTIONAL BLOCK DIAGRAM
OUTLP1
OUTLN1
OUTRP1
OUTRN1
FILTD
FILTR
ADCLP
ADCLN
ADCRP
ADCRN
DLRCLK
DBCLK
DSDATA1
DSDATA2
DSDATA3
DSDATA4
MCLKASDATAABCLKALRCLKODVDDDVDDAVDDAVDDDVDD
AGNDAGNDAGNDAGNDDGNDDGND
CINCLATCHCCLKCOUT
PD/RSTM/S
OUTLP2
OUTLN2
OUTRP2
OUTRN2
OUTLP3
OUTLN3
OUTRP3
OUTRN3
OUTLP4
OUTLN4
OUTRP4
OUTRN4
PRODUCT OVERVIEW
The AD1835A is a high performance, single-chip codec fea-
turing four stereo DACs and one stereo ADC. Each DAC
comprises a high performance digital interpolation filter, a
multibit �-� modulator featuring Analog Devices’ patented
technology, and a continuous-time voltage out analog section.
(continued on page 11)
Supports 256 � fS, 512 � fS, and 768 � fS Master
Mode Clocks
Power-Down Mode Plus Soft Power-Down Mode
Flexible Serial Data Port with Right-Justified, Left-
Justified, I2S Compatible, and DSP Serial Port Modes
TDM Interface Mode Supports 8-In/8-Out Using a
Single SHARC® SPORT
52-Lead MQFP Plastic Package
APPLICATIONS
DVD Video and Audio Players
Home Theater Systems
Automotive Audio Systems
Audio/Visual Receivers
Digital Audio Effects Processors
AD1835A–SPECIFICATIONS
TEST CONDITIONS
Supply Voltages (AVDD, DVDD)5.0 V
Ambient Temperature25°C
Input Clock12.288 MHz (256 � fS Mode)
ADC Input Signal1.0078125 kHz, –1 dBFS (Full Scale)
DAC Input Signal1.0078125 kHz, 0 dBFS (Full Scale)
Input Sample Rate (fS)48 kHz
Measurement Bandwidth20 Hz to 20 kHz
Word Width24 Bits
Load Capacitance100 pF
Load Impedance47 k�
Performance of all channels is identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation
specifications).
AD1835A
*Guaranteed by design.
Specifications subject to change without notice.
AD1835A
TIMING SPECIFICATIONS
AD1835A
Specifications subject to change without notice.
Figure 1.MCLK and PD/RST Timing
AD1835A
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD1835A features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C, unless otherwise noted.)
AVDD, DVDD, ODVDD to AGND, DGND . .–0.3 V to +6.0 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . .–0.3 V to +0.3 V
Digital I/O Voltage to DGND . . . .–0.3 V to ODVDD + 0.3 V
Analog I/O Voltage to AGND . . . . . .–0.3 V to AVDD + 0.3 V
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . . .–40°C to +85°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
*Z = Pb-free part.
PIN FUNCTION DESCRIPTIONS
40, 52
41 to 44
PIN CONFIGURATION
AGND
AVDD
OUTRP2
OUTRN2
OUTLP2
OUTLN2
OUTRP1
OUTRN1
OUTLP1
OUTLN1
PD/RST
CIN
CLATCH
DVDD
OUTLN3OUTLP3
OUTRN3
OUTRP3
OUTLN4
OUTLP4
OUTRN4
OUTRP4
AGND
DLRCLK
DBCLK
DGND
FILTDFILTR
AGND
M/S
AGND
AVDD
ADCLNADCLP
ADCRN
ADCRP
AGND
AGND
DGNDCCLKCOUTASDATAODVDDMCLKALRCLKABCLKDSDATA4DSDATA3DSDATA2DSDATA1
DVDD
AVDD
AD1835A–Typical Performance Characteristics
TPC 1.ADC Composite Filter Response
TPC 2.ADC High-Pass Filter Response, fS = 48 kHz
TPC 3.ADC Composite Filter Response
(Pass-Band Section)
TPC 4.ADC High-Pass Filter Response, fS = 96 kHz
TPC 5.DAC Composite Filter Response, fS = 48 kHz
TPC 6.DAC Composite Filter Response, fS = 96 kHz
TPC 7.DAC Composite Filter Response, fS = 192 kHz
TPC 8.DAC Composite Filter Response, fS = 48 kHz
(Pass-Band Section)
TPC 9.DAC Composite Filter Response, fS = 96 kHz
(Pass-Band Section)
TPC 10.DAC Composite Filter Response, fS = 192 kHz
(Pass-Band Section)
AD1835A
DEFINITIONS
Dynamic Range
The ratio of a full-scale input signal to the integrated input noise
in the pass band (20 Hz to 20 kHz), expressed in decibels (dB).
Dynamic range is measured with a –60 dB input signal and is
equal to (S/[THD + N]) + 60 dB. Note that spurious harmonics
are below the noise with a –60 dB input, so the noise level
establishes the dynamic range. The dynamic range is specified
with and without an A-weight filter applied.
Signal-to-(Total Harmonic Distortion + Noise)[S/(THD + N)]
The ratio of the root-mean-square (rms) value of the fundamen-
tal input signal to the rms sum of all other spectral components
in the pass band, expressed in decibels (dB).
Pass Band
The region of the frequency spectrum unaffected by the attenu-
ation of the digital decimator’s filter.
Pass-Band Ripple
The peak-to-peak variation in amplitude response from equal-
amplitude input signal frequencies within the pass band, expressed
in decibels.
Stop Band
The region of the frequency spectrum attenuated by the digital
decimator’s filter to the degree specified by stop-band attenuation.
Gain Error
With a near full-scale input, the ratio of actual output to expected
output, expressed as a percentage.
Interchannel Gain Mismatch
With identical near full-scale inputs, the ratio of outputs of the
two stereo channels, expressed in decibels.
Gain Drift
Change in response to a near full-scale input with a change in
temperature, expressed as parts-per-million (ppm) per °C.
Crosstalk (EIAJ Method)
Ratio of response on one channel with a grounded input to a
full-scale 1 kHz sine wave input on the other channel, expressed
in decibels.
Power Supply Rejection
With no analog input, signal present at the output when a
300 mV p-p signal is applied to power supply pins, expressed in
decibels of full scale.
Group Delay
Intuitively, the time interval required for an input pulse to
appear at the converter’s output, expressed in microseconds.
More precisely, the derivative of radian phase with respect to
radian frequency at a given frequency.
Group Delay Variation
The difference in group delays at different input frequencies.
Specified as the difference between the largest and the smallest
group delays in the pass band, expressed in microseconds.
GLOSSARY
ADC—Analog-to-Digital Converter.
DAC—Digital-to-Analog Converter.
DSP—Digital Signal Processor.
IMCLK—Internal Master Clock Signal Used to Clock the ADC
and DAC Engines.
MCLK—External Master Clock Signal Applied to the AD1835A.
(continued from page 1)
Each DAC has independent volume control and clickless mute
functions. The ADC comprises two 24-bit conversion channels
with multibit �-� modulators and decimation filters.
The AD1835A also contains an on-chip reference with a
nominal value of 2.25 V.
The AD1835A contains a flexible serial interface that allows
glueless connection to a variety of DSP chips, AES/EBU
receivers, and sample rate converters. The AD1835A can be
configured in left-justified, right-justified, I2S, or DSP com-
patible serial modes. Control of the AD1835A is achieved by an
SPI® compatible serial port. While the AD1835A can be oper-
ated from a single 5 V supply, it also features a separate supply
pin for its digital interface which allows the device to be inter-
faced to other devices using 3.3 V power supplies.
The AD1835A is available in a 52-lead MQFP package and is
specified for the industrial temperature range of –40°C to +85°C.
FUNCTIONAL OVERVIEW
ADCs
There are two ADC channels in the AD1835A, configured as
a stereo pair. Each ADC has fully differential inputs. The
ADC section can operate at a sample rate of up to 96 kHz.
The ADCs include on-board digital decimation filters with
120 dB stop-band attenuation and linear phase response,
operating at an oversampling ratio of 128 (for 48 kHz opera-
tion) or 64 (for 96 kHz operation).
ADC peak level information for each ADC may be read from the
ADC Peak 0 and ADC Peak 1 registers. The data is supplied as a
6-bit word with a maximum range of 0 dB to –63 dB and a
resolution of 1 dB. The registers will hold peak information
until read; after reading, the registers are reset so that new peak
information can be acquired. Refer to the register description
for details of the format. The two ADC channels have a com-
mon serial bit clock and a left-right framing clock. The clock
signals are all synchronous with the sample rate.
The ADC digital pins, ABCLK and ALRCLK, can be set to
operate as inputs or outputs by connecting the M/S pin to
ODVDD or DGND, respectively. When the pins are set as
outputs, the AD1835A will generate the timing signals. When
the pins are set as inputs, the timing must be generated by the
external audio controller.
DACs
The AD1835A has eight DAC channels arranged as four inde-
pendent stereo pairs, with eight fully differential analog outputs
for improved noise and distortion performance. Each channel has
its own independently programmable attenuator, adjustable in
1024 linear steps. Digital inputs are supplied through four serial
data input pins (one for each stereo pair) and a common frame
(DLRCLK) and bit (DBLCK) clock. Alternatively, one of the
packed data modes can be used to access all eight channels on a
single TDM data pin. A stereo replicate feature is included where
the DAC data sent to the first DAC pair is also sent to the other
DACs in the part. The AD1835A can accept DAC data at a
sample rate of 192 kHz on DAC 1 only. The stereo replicate fea-
ture can then be used to copy the audio data to the other DACs.
high frequency noise present on the output pins, as well as to
provide differential-to-single-ended conversion. Note that the use
of op amps with low slew rate or low bandwidth may cause high
frequency noise and tones to fold down into the audio band;
care should be exercised in selecting these components.
The FILTD pin should be connected to an external grounded
capacitor. This pin is used to reduce the noise of the internal
DAC bias circuitry, thereby reducing the DAC output noise. In
some cases, this capacitor may be eliminated with little effect on
performance.
DAC and ADC Coding
The DAC and ADC output data stream is in a twos complement
encoded format. The word width can be selected from 16 bit,
20 bit, or 24 bit. The coding scheme is detailed in Table I.
Table I.Coding Scheme
AD1835A CLOCKING SCHEME
By default, the AD1835A requires an MCLK signal that is
256 times the required sample frequency up to a maximum of
12.288 MHz. The AD1835A uses a clock scaler to double the
clock frequency for use internally. The default setting of the
clock scaler is Multiply by 2. The clock scaler can also be set
Multiply by 1 (bypass) or by 2/3. The clock scaler is controlled
by programming the bits in the ADC Control 3 register. The
internal MCLK signal, IMCLK, should not exceed 24.576 MHz
in order to ensure correct operation.
The MCLK of the AD1835A should remain constant during
normal operation of the DAC and ADC. If it is necessary to
change the MCLK rate, then the AD1835A should be reset.
Additionally, if the MCLK scaler needs to be modified so that
the IMCLK doesn’t exceed 24.576 MHz, this should be done
during the internal reset phase of the AD1835A by programming
the bits in the first 3072 MCLK periods following the reset.
Selecting DAC Sampling Rate
The AD1835A DAC engine has a programmable interpolator
that allows the user to select different interpolation rates based
on the required sample rate and MCLK value available. TableII
shows the settings required for sample rates based on a fixed
MCLK of 12.288 MHz.
Table II. DAC Sample Rate Settings
Selecting an ADC Sample Rate
The AD1835A ADC engine has a programmable decimator,
which allows the user to select the sample rate based on the
AD1835A
Figure 2.Modulator Clocking Scheme
Figure 3.Format of SPI Timing
Table III. ADC Sample Rate Settings
To maintain the highest performance possible, the clock jitter of
the master clock signal should be limited to less than 300 ps
rms, measured using the edge-to-edge technique. Even at these
levels, extra noise or tones may appear in the DAC outputs if
the jitter spectrum contains large spectral peaks. It is highly
recommended that the master clock be generated by an inde-
pendent crystal oscillator. In addition, it is especially important
that the clock signal not be passed through an FPGA or other
large digital chip before being applied to the AD1835A. In most
cases, this will induce clock jitter due to the fact that the clock
signal is sharing common power and ground connections with
unrelated digital output signals.
RESET and Power-Down
PD/RST will power down the chip and set the control registers
Power Supply and Voltage Reference
The AD1835A is designed for 5 V supplies. Separate power supply
pins are provided for the analog and digital sections. These pins
should be bypassed with 100 nF ceramic chip capacitors, as
close to the pins as possible, to minimize noise pickup. A bulk
aluminum electrolytic capacitor of at least 22 �F should also be
provided on the same PC board as the codec. For critical applica-
tions, improved performance will be obtained with separate
supplies for the analog and digital sections. If this is not pos-
sible, it is recommended that the analog and digital supplies be
isolated by two ferrite beads in series with the bypass capacitor
of each supply. It is important that the analog supply be as clean
as possible.
The internal voltage reference is brought out on the FILTR pin
and should be bypassed as close as possible to the chip, with a
parallel combination of 10 µF and 100 nF. The reference volt-
age may be used to bias external op amps to the common-mode
voltage of the analog input and output signal pins. The current
drawn from the VREF pin should be limited to less than 50 �A.
Serial Control Port

Partno	Mfg	Dc	Qty	Available	Descript
AD1835AASZ	ADI	N/a	4	avai	2 ADC, 8 DAC, 96 kHz, 24-Bit Sigma Delta Codec