AD1833AAST Fast Delivery |IC PHOENIX CO.,LIMITED

AD1833AAST ,Multi-Channel, 24-Bit, 192 kHz Sigma-Delta DACspecifications).Parameter Min Typ Max Unit Test ConditionsANALOG PERFORMANCEDIGITAL-TO-ANALOG CONVE ..
AD1833AST ,Multichannel 24-Bit, 192 kHz, DACSpecifications subject to change without notice.Parameter Min Typ Max Unit Test ConditionsANALOG PE ..
AD1833AST ,Multichannel 24-Bit, 192 kHz, DACSpecifications subject to change without notice.ABSOLUTE MAXIMUM RATINGS* LQFP, θ Thermal Impedance ..
AD1835AASZ ,2 ADC, 8 DAC, 96 kHz, 24-Bit Sigma Delta Codecspecifications).Parameter Min Typ Max UnitANALOG-TO-DIGITAL CONVERTERSADC Resolution 24 BitsDynamic ..
AD1836ACSZ , Multichannel 96 kHz Codec
AD1836AS ,Multichannel 96 kHz CodecGENERAL DESCRIPTIONDACs: –95 dB THD + N, 108 dB SNR and Dynamic RangeThe AD1836 is a high-performan ..
AD829JRZ-REEL7 , High Speed, Low Noise Video Op Amp
AD829JRZ-REEL7 , High Speed, Low Noise Video Op Amp
AD829SQ/883B ,High-Speed, Low-Noise Video Op AmpApplications–IN 2 7 +VS0.02% Differential Gain+IN 3 6 OUTPUT0.04 Differential PhaseTOP VIEWLow Noi ..
AD829SQ/883B ,High-Speed, Low-Noise Video Op AmpHigh-Speed, Low-NoiseaVideo Op AmpAD829
AD8300AR ,+3 Volt, Serial Input Complete 12-Bit DACapplications.The AD8300 is specified over the extended industrial (–40

AD1833AAST
Multi-Channel, 24-Bit, 192 kHz Sigma-Delta DAC
REV.0
Multichannel,
24-Bit, 192 kHz, �-� DAC
FEATURES
5 V Stereo Audio System with 3.3 V Tolerant Digital
Interface
Supports 96 kHz Sample Rates on 6 Channels and
192 kHz on 2 Channels
Supports 16-/20-/24-Bit Word Lengths
Multibit �-� Modulators with
Perfect Differential Linearity Restoration for
Reduced Idle Tones and Noise Floor
Data Directed Scrambling DACs—Least Sensitive to
Jitter
Differential Output for Optimum Performance
DACs Signal-to-Noise and Dynamic Range:110 dB
–94 dB THD + N—6-Channel Mode
–95 dB THD + N—2-Channel Mode
On-Chip Volume Control per Channel with 1024-Step
Linear Scale
Software Controllable Clickless Mute
Digital De-emphasis Processing
Supports 256� fS, 512� fS, and 768� fS Master
Clock Modes
Power-Down Mode Plus Soft Power-Down Mode
Flexible Serial Data Port with Right-Justified,
Left-Justified, I2S Compatible, and DSP Serial Port Modes
Supports Packed Data Mode and TDM Mode
48-Lead LQFP Plastic Package
APPLICATIONS
DVD Video and Audio Players
Home Theater Systems
Automotive Audio Systems
Set-Top Boxes
Digital Audio Effects Processors
FUNCTIONAL BLOCK DIAGRAM
AGNDDGNDFILTR FILTD
MCLK
CDATA
CLATCH
CCLK
OUTLP1
OUTLN1
OUTLP2
OUTLN2
OUTLP3
OUTLN3
OUTRP3
OUTRN3
OUTRP2
OUTRN2
OUTRP1
OUTRN1
ZERO FLAGSDVDD1 DVDD2AVDD
RESET
SOUT
L/RCLK
BCLK
SDIN1
SDIN2
SDIN3
GENERAL DESCRIPTION
The AD1833A is a complete, high performance, single-chip,
multichannel, digital audio playback system. It features six audio
playback channels, each comprising a high performance digital
interpolation filter, a multibit S-D modulator featuring Analog
Devices’ patented technology, and a continuous-time voltage-out
analog DAC section. Other features include an on-chip clickless
attenuator and mute capability for each channel, programmed
through an SPI compatible serial control port.
The AD1833A is fully compatible with all known DVD formats,
accommodating word lengths of up to 24 bits at sample rates ofkHz and 96 kHz on all six channels while supporting a 192kHz
sample rate on two channels. It also provides the Redbook stan-
dard 50ms/15 ms digital de-emphasis filters at sample rates ofkHz, 44.1kHz, and 48kHz.
The AD1833A has a very flexible serial data input port that
allows glueless interconnection to a variety of ADCs, DSP chips,
AES/EBU receivers, and sample rate converters. It can be con-
figured in right-justified, left-justified, I2S, or DSP serial port
compatible modes. The AD1833A accepts serial audio data in MSB
first, twos complement format. The AD1833A can be operated
from a single 5 V power supply; it also features a separate supply
pin for its digital interface that allows it to be interfaced to devices
using 3.3 V power supplies.
The AD1833A is fabricated on a single monolithic integrated
circuit and is housed in a 48-lead LQFP package for operation
from –40∞C to +85∞C.
AD1833A–SPECIFICATIONS
TEST CONDITIONS, UNLESS OTHERWISE NOTED*
Supply Voltages (AVDD, DVDDX)5 V
Ambient Temperature25∞C
Input Clock12.288 MHz, (8� Mode)
Input SignalNominally 1 kHz, 0 dBFS
(Full-Scale)
Input Sample Rate48 kHz
Measurement Bandwidth20 Hz to 20 kHz
Word Width24 Bits
Load Capacitance100 pF
Load Impedance10 kW
*Performance is identical for all channels (except for the Interchannel Gain
Mismatch and Interchannel Phase Deviation specifications).
AD1833A
Specifications subject to change without notice.
DIGITAL TIMING
(Guaranteed over –40�C to +85�C, AVDD = DVDD = 5 V � 10%)
AD1833A
Figure 1.MCLK and RESET Timing
Figure 2.SPI Port Timing
Figure 3.Serial Port Timing
ABSOLUTE MAXIMUM RATINGS*
(TA = 25∞C, unless otherwise noted.)
AVDD, DVDDX to AGND, DGND . . . . . . . . –0.3 V to +6.5 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital I/O Voltage to DGND . . . . . –0.3 V to DVDD2 + 0.3 V
Analog I/O Voltage to AGND . . . . . . –0.3 V to AVDD + 0.3 V
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . –40∞C to +85∞C
Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150∞C
LQFP, qJA Thermal Impedance . . . . . . . . . . . . . . . . . 91∞C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215∞C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220∞C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
Figure 5.Auxiliary Interface Timing
ORDERING GUIDE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate
on the human body and test equipment and can discharge without detection. Although the AD1833A
features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to
high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid
performance degradation or loss of functionality.
AD1833A
PIN CONFIGURATION
OUTRP1
OUTRN1
AVDD
AVDD
AGND
AGND
AGND
OUTLP1
OUTLN1
AVDD
AVDD
AGND
AGND
AGND
DGND
DVDD1
ZEROA
ZERO3R
DGND
DVDD2
RESET
ZERO1L
ZERO3LZERO1R
OUTLN2OUTLP2OUTLN3OUTLP3AV
FILTDFILTRAGNDOUTRP3OUTRN3OUTRP2OUTRN2
ZERO2RCLATCH
CDATA
CCLK
L/RCLK
BCLK
MCLKSDIN1SDIN2SDIN3
SOUT
ZERO2L
PIN FUNCTION DESCRIPTIONS
5, 6, 7, 30, 31, 32, 41
8, 29
9DVDD1
DEFINITION OF TERMS
Dynamic Range
The ratio of a full-scale input signal to the integrated input noise in
the pass band (20 Hz to 20 kHz), expressed in decibels. Dynamic
range is measured with a –60 dB input signal and is equal to
(S/[THD + N]) +60 dB. Note that spurious harmonics are below
the noise with a –60 dB input, so the noise level establishes the
dynamic range. The dynamic range is specified with and without
an A-Weight filter applied.
Signal to (Total Harmonic Distortion + Noise)
[S/(THD + N)]
The ratio of the root-mean-square (rms) value of the fundamental
input signal to the rms sum of all other spectral components in
the pass band, expressed in decibels.
Pass Band
The region of the frequency spectrum unaffected by the attenuation
of the digital decimator’s filter.
Pass-Band Ripple
The peak-to-peak variation in amplitude response from equal-
amplitude input signal frequencies within the pass band, expressed
in decibels.
Stop Band
The region of the frequency spectrum attenuated by the digital
decimator’s filter to the degree specified by stop-band attenuation.
Gain Error
With a near full-scale input, the ratio of actual output to expected
output, expressed as a percentage.
Interchannel Gain Mismatch
With identical near full-scale inputs, the ratio of outputs of the
two stereo channels, expressed in decibels.
Gain Drift
Change in response to a nearly full-scale input with a change in
temperature, expressed as parts-per-million (ppm/∞C).
Crosstalk (EIAJ Method)
Ratio of response on one channel with a grounded input to a
full-scale 1 kHz sine wave input on the other channel, expressed
in decibels.
Power Supply Rejection
With no analog input, signal present at the output when a
300 mV p-p signal is applied to the power supply pins, expressed
in decibels of full scale.
Group Delay
Intuitively, the time interval required for an input pulse to appear
at the converter’s output, expressed in ms. More precisely, the
derivative of radian phase with respect to the radian frequency at
a given frequency.
Group Delay Variation
The difference in group delays at different input frequencies.
Specified as the difference between the largest and the smallest
group delays in the pass band, expressed in ms.
PIN FUNCTION DESCRIPTIONS (continued)
AD1833A
TPC 1.Pass-Band Response, 8� Mode
TPC 2.Transition Band Response, 8� Mode
TPC 3.Complete Response, 8� Mode
–Typical Performance Characteristics
TPC 4.Pass-Band Response, 4� Mode
TPC 5.40 kHz Pass-Band Response, 4� Mode
TPC 6.Transition Band Response, 4� Mode
TPC 7.Complete Response, 4� Mode
TPC 8.80 kHz Pass-Band Response, 2� Mode
TPC 9.Transition Band Response, 2� Mode
TPC 10.Complete Response, 2� Mode
AD1833A
FUNCTIONAL DESCRIPTION
Device Architecture
The AD1833A is a six-channel audio DAC featuring multibit
sigma-delta (S-D) technology. The AD1833A features three stereo
converters (providing six channels); each stereo channel is con-
trolled by a common bit-clock (BCLK) and synchronization
signal (L/RCLK).
General Overview
The AD1833A is designed to run with an internal MCLK
(IMCLK) of 24.576MHz and a modulator rate of 6.144MHz
(i.e., IMCLK/4). From this IMCLK frequency, sample rates ofkHz and 96kHz can be achieved on six channels or 192kHz
can be achieved on two channels. The internal clock should never
be run at a higher frequency but may be reduced to achieve
lower sampling rates, i.e., for a sample rate of 44.1 kHz, the appro-
priate internal MCLK is 22.5792 MHz. The modulator rate scales
in proportion with the MCLK scaling.
Interpolator
The interpolator consists of as many as three stages of sample
rate doubling and half-band filtering followed by a 16-sample
zero order hold (ZOH). The sample rate doubling is achieved
by zero stuffing the input samples, and a digital half-band filter
is used to remove any images above the band of interest and to
bring the zero samples to their correct values.
The interpolator output must always be at a rate of IMCLK/64.
Depending on the interpolation rates selected, one, two, or all
three stages of doubling may be switched in. This allows for
three different sample rate inputs for any given IMCLK. For an
IMCLK of 24.576 MHz, all three doubling stages are used with
a 48 kHz input sample rate; with a 96 kHz input sample rate, only
two doubling stages are used; and with a 192 kHz input sample
rate, only one doubling stage is used. In each case, the input
sample frequency is increased to 384 kHz (IMCLK/64). The
ZOH holds the interpolator samples for upsampling by the
modulator. This is done at a rate 16 times the interpolator
output sample rate.
Modulator
The modulator is a 6-bit, second order implementation and uses
data scrambling techniques to achieve perfect linearity. The modu-
lator samples the output of the interpolator stage(s) at arate of
(IMCLK/4).
OPERATING FEATURES
SPI Register Definitions
The SPI port allows flexible control of the device’s programmable
functions. It is organized around nine registers: six individual channel
volume registers and three control registers. Each write operation
to the AD1833A SPI control port requires 16 bits of serial data
in MSB-first format. The four most significant bits are used to
select one of nine registers (seven register addresses are reserved),
and the bottom 10 bits are written to that register. This allows a
write to one of the nine registers in a single 16-bit transaction. The
SPI CCLK signal is used to clock in the data. The incoming
data should change on the falling edge of this signal and remain
valid during the rising edge. At the end of the 16CCLK periods,
the CLATCH signal should rise to latch the data internally into
the AD1833A (see Figure 2).
The serial interface format used on the control port uses a 16-bit
serial word, as shown in Table I. The 16-bit word is divided into
several fields: Bits 15 through 12 define the register address, Bits11
and 10 are reserved and must be programmed to 0, and Bits9
through 0 are the data field (which has specific definitions,
depending on the register selected).
Table I.Control Port Map
NOTESMust be programmed to zero.Bit 15 = MSB.

Partno	Mfg	Dc	Qty	Available	Descript
AD1833AAST	ADI	N/a	3	avai	Multi-Channel, 24-Bit, 192 kHz Sigma-Delta DAC