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AD1819BJST ,AC?7 SoundPort CodecSPECIFICATIONSSTANDARD TEST CONDITIONS UNLESS OTHERWISE NOTEDDAC Test ConditionsTemperature 25

AD1819BJST
AC?7 SoundPort Codec
REV.0
AC’97 SoundPort® Codec
AC’97 FEATURES
Fully Compliant AC’97 Analog I/O Component
48-Terminal LQFP Package
Multibit SD Converter Architecture for Improved
S/N Ratio >90 dB
16-Bit Stereo Full-Duplex Codec
Four Analog Line-Level Stereo Inputs for Connection
from LINE, CD, VIDEO, and AUX
Two Analog Line-Level Mono Inputs for Speakerphone
and PC BEEP
Mono MIC Input Switchable from Two External
Sources
High Quality CD Input with Ground Sense
Stereo Line Level Output
Mono Output for Speakerphone
Power Management Support
ENHANCED FEATURES
Support for Multiple Codec Communications
DSP 16-Bit Serial Port Format
Variable 7 kHz to 48 kHz Sampling Rate with 1 Hz
Resolution
Supports Modem Sample Rates and Filtering
Phat™ Stereo 3D Stereo Enhancement
VHDL and Verilog Models of Serial Port Available
SoundPort is a registered trademark of Analog Devices, Inc.
Phat is a trademark of Analog Devices, Inc.
FUNCTIONAL BLOCK DIAGRAM
SYNC
BIT_CLK
MIC1
MIC2
AUX
VIDEO
PC_BEEP
LINE_OUT_L
MONO_OUT
LINE_IN
PHONE_IN
LINE_OUT_R
XTALOXTALI
CS1CHAIN_INCHAIN_CLK
RESET
SDATA_IN
CS0
SDATA_OUT
AD1819B
PRODUCT OVERVIEW
The AD1819B SoundPort Codec is designed to meet all require-
ments of the Audio Codec ’97, Component Specification, Revision
1.03, © 1996, Intel Corporation, found at www.Intel.com. In
addition, the AD1819B supports multiple codec configurations
(up to three per AC-Link), a DSP serial mode, variable sample
rates, modem sample rates and filtering, and built-in Phat Ste-
reo 3D enhancement.
The AD1819B is an analog front end for high performance PC
audio, modem, or DSP applications. The AC’97 architecture
defines a 2-chip audio solution comprising a digital audio con-
troller, plus a high quality analog component that includes
Digital-to-Analog Converters (DACs), Analog-to-Digital Con-
verters (ADCs) mixer and I/O.
The main architectural features of the AD1819B are the high
quality analog mixer section, two channels of SD ADC conver-
sion, two channels of SD DAC conversion and Data Direct
Scrambling (D2S) rate generators. The AD1819B’s left channel
ADC and DAC are compatible for modem applications support-
ing irrational sample rates and modem filtering requirements.
FUNCTIONAL DESCRIPTION
This section overviews the functionality of the AD1819B and is
intended as a general introduction to the capabilities of the
device. Detailed reference information may be found in the
descriptions of the Indexed Control Registers.
Analog Inputs
The codec contains a stereo pair of SD ADCs. Inputs to the
ADC may be selected from the following analog signals: tele-
phony (PHONE_IN), mono microphone (MIC1 or MIC2),
stereo line (LINE_IN), auxiliary line input (AUX), stereo CD
ROM (CD), stereo audio from a video source (VIDEO) and
post-mixed stereo or mono line output (LINE_OUT).
Analog Mixing
PHONE_IN, MIC1 or MIC2, LINE_IN, AUX, CD and
VIDEO can be mixed in the analog domain with the stereo
output from the DACs. Each channel of the stereo analog in-
puts may be independently gained or attenuated from +12 dB
to –34.5 dB in 1.5 dB steps. The summing path for the mono
inputs (PHONE_IN, MIC1, and MIC2 to LINE_OUT) dupli-
cates mono channel data on both the left and right LINE_OUT.
Additionally, the PC attention signal (PC_BEEP) may be
mixed with the line output. A switch allows the output of the
DACs to bypass the Phat Stereo 3D enhancement.
Analog-to-Digital Signal Path
The selector sends left and right channel signals to the program-
mable gain amplifier (PGA). The PGA following the selector
allows independent gain for each channel entering the ADC
from 0 dB to +22.5 dB in 1.5 dB steps.
Each channel of the ADC is independent, and can process
left and right channel data at different sample rates. All pro-
grammed sample rates from 7 kHz to 48 kHz have a resolution
of 1 Hz. The AD1819B also supports irrational V.34 sample
rates.
Sample Rates and D2S
The AD1819B default mode sets the codec to operate at 48 kHz
sample rates. The converter pairs may process left and right
channel data at different sample rates. The AD1819B sample
rate generator allows the codec to instantaneously change and
process sample rates from 7 kHz to 48 kHz with a resolution of
1 Hz. The in-band integrated noise and distortion artifacts in-
troduced by rate conversions are below –90 dB. The AD1819B
uses a 4-bit D/A structure and Data Directed Scrambling (D2S)
to enhance noise immunity on motherboards and in PC enclo-
sures, and to suppress idle tones below the device’s quantization
noise floor. The D2S process pushes noise and distortion arti-
facts caused by errors in the multibit D/A conversion process to
frequencies beyond the audible range of the human ear and then
filters them.
Digital-to-Analog Signal Path
The analog output of the DAC may be gained or attenuated
from +12 dB to –34.5 dB in 1.5 dB steps, and summed with any
of the analog input signals. The summed analog signal enters
the Master Volume stage where each channel of the mixer out-
put may be attenuated from 0 dB to –46.5 dB in 1.5 dB steps or
muted.
Host-Based Echo Cancellation Support
The AD1819B supports time correlated I/O data format by
presenting mic data on the left channel of the ADC and the
mono summation of left and right output on the right channel.
The ADC is splittable; left and right ADC data can be sampled
at different rates.
Telephony Modem Support
The AD1819B contains a V.34-capable analog front end for
supporting host-based and data pump modems. The modem
DAC typical dynamic range is 90 dB over a 4.2 kHz analog
output passband where FS = 12.8 kHz. The left channel of the
ADC and DAC may be used to convert modem data at the same
sample rate in the range between 7 kHz and 48 kHz. All pro-
grammed sample rates have a resolution of 1 Hz. The AD1819B
supports irrational V.34 sample rates with 8/7 and 10/7 select-
able sample rate multiplier coefficients.
Differences Between the AD1819A and AD1819B
The voltage reference (VREF) of the AD1819B remains active
while RESET is asserted. This eliminates the audible artifacts
associated with the RESET LO to HI transitions that can
occur during a Windows boot (power-up) or Windows warm
restart (reset).
AD1819B
STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED
DAC Test Conditions
Temperature25°CCalibrated
Digital Supply (VDD)5.0V0 dB Attenuation
Analog Supply (VCC)5.0VInput 0 dB
Sample Rate (FS)48kHz10 kW Output Load
Input Signal1008HzMute Off
Analog Output Passband20 Hz to 20 kHzADC Test ConditionsVIH (AC-Link)2.0VCalibratedVIL (AC-Link)0.8V0 dB GainVIH (CS0, CS1, CHAIN_IN)4.0VInput –3 dB Relative to Full ScaleVIL (CHAIN_CLK)1.0VLine Input Selected
ANALOG INPUT
PROGRAMMABLE GAIN AMPLIFIER—ADC
ANALOG MIXER— INPUT GAIN/AMPLIFIERS/ATTENUATORS
DIGITAL DECIMATION AND INTERPOLATION FILTERS*
*Guaranteed, not tested.
SPECIFICATIONS
AD1819B–SPECIFICATIONS
ANALOG-TO-DIGITAL CONVERTERS
Gain Error (Full-Scale Span Relative to Nominal Input Voltage)
Interchannel Gain Mismatch (Difference of Gain Errors)
DIGITAL-TO-ANALOG CONVERTERS
MASTER VOLUME
ANALOG OUTPUT
VREF Current Drive
VREFOUT Current Drive
*Guaranteed, not tested.
Specifications subject to change without notice.
STATIC DIGITAL SPECIFICATIONS
POWER SUPPLY
CLOCK SPECIFICATIONS*
POWER-DOWN STATES
Analog Mixer Power-Down (VREF and VREFOUT Off)
Digital Interface Power-Down*
Internal Clocks Disabled*
ADC and DAC Power-Down
VREF Standby Mode*
Total Power-Down
*Guaranteed, not tested.
Specifications subject to change without notice.
AD1819B
AD1819B
TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE RANGE)
SYNC Inactive to BIT_CLK Start-Up Delay
BIT_CLK Output Jitter*
BIT_CLK High Pulsewidth
Setup to Falling Edge of BIT_CLK
BIT_CLK Fall Time
SYNC Rise Time
SYNC Fall Time
SDATA_IN Rise Time
SDATA_IN Fall Time
SDATA_OUT Rise Time
SDATA_OUT Fall Time
End of Slot 2 to BIT_CLK, SDATA_IN Low
*Output Jitter is directly dependent on crystal input jitter.
RESET
BIT_CLKtRST_LOW
Figure 1.Cold Reset
Figure 2.Warm Reset
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1819B features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*
*Stresses greater than those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
*ST = Thin Quad Flatpack.
ENVIRONMENTAL CONDITIONS
Ambient Temperature Rating
TAMB = TCASE – (PD · qCA)
TCASE = Case Temperature in °C
PD = Power Dissipation in WCA = Thermal Resistance (Case-to-Ambient)JA = Thermal Resistance (Junction-to-Ambient)JC = Thermal Resistance (Junction-to-Case)
Figure 4.Data Setup and Hold
BIT_CLK
SYNC
SDATA_IN
tRISECLK
tRISESYNC
tRISEDIN
tRISEDOUT
tFALLCLK
tFALLSYNC
tFALLDIN
tFALLDOUT
SDATA_OUT
Figure 5.Signal Rise and Fall Time
Figure 6.AC-Link, Link Low Power Mode Timing
Figure 7.ATE Test Mode
AD1819B
PIN CONFIGURATION
48-Terminal LQFP
(ST-48)
PIN FUNCTION DESCRIPTIONS
Digital I/O
*Input if the AD1819B is configured as Slave 1 or Slave 2.
Daisy Chain Connections
*Output when configured as Master. Input when configured as Slave 1 or Slave 2.
Analog I/O
These signals connect the AD1819B component to analog sources and sinks, including microphones and speakers.
Filter/Reference
VREFOUT
AFILT1
AFILT2
FILT_R
FILT_L
RX3D
Power and Ground Signals
DVSS2
DVDD2
AVDD2
No Connects
AD1819B
XTL_OUTXTL_IN
MIC1
MIC2
AUX
VIDEO
PHONE_IN
MONO_OUT
PC_BEEP
LINE_IN
RESET
SYNC
BIT_CLK
SDATA_OUT
SDATA_IN
LINE_OUT_L
LINE_OUT_R
Figure 8.Block Diagram Register Map
Indexed Control Registers
NOTESAll registers not shown and bits containing an X are reserved.Odd register addresses are aliased to the next lower even address.Reserved registers should not be written.Zeros should be written to reserved bits.
AD1819B
Reset (Index 00h)
Note: Writing any value to this register performs a register reset, which cause all registers to revert to their default values (except
74h, which controls the serial configuration). Reading this register returns the ID code of the part and a code for the type of 3D
Stereo Enhancement.
ID [9:0]Identify Capability. The ID field decodes the capabilities of AD1819B on the following:
*The AD1819B contains none of the optional features identified by these bits.
SE [4:0]Stereo Enhancement. The 3D stereo enhancement field identifies the Analog Devices 3D Phat Stereo enhancement.
Master Volume (Index 02h)
RMV [4:0]Right Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from
0 dB to a maximum attenuation of –46.5 dB.
RMV5Right Master Volume Maximum Attenuation. Forces RMV [4:0] to all “1s,” –46.5 dB.
LMV [4:0]Left Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from
0 dB to a maximum attenuation of –46.5 dB.
LMV5Left Master Volume Maximum Attenuation. Forces LMV [4:0] to all “1s,” –46.5 dB.Master Volume Mute. When this bit is set to “1,” the left and right channels are muted.
Master Volume Mono (Index 06h)
MMV [4:0]Mono Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from
0 dB to a maximum attenuation of –46.5 dB.
MMM
PC Beep (Index 0Ah)
PCV [3:0]PC Beep Volume Control. The least significant bit represents 3 dB attenuation. This register controls the output
from 0 dB to a maximum attenuation of –45 dB. The PC Beep is routed to the Left and Right Line outputs even
when AD1819B is in a RESET State. This is so that Power-On Self Test (POST) codes can be heard by the user
in case of a hardware problem with the PC.
PCMPC Beep Mute. When this bit is set to “1,” the channel is muted.
Phone Volume (Index 0Ch)
PHV [4:0]Phone Volume. Allows setting the Phone Volume Attenuator in 32 steps. The LSB represents 1.5 dB, and the
range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
PHMPhone Mute. When this bit is set to “1,” the channel is muted.
Mic Volume (Index 0Eh)
MCV [4:0]Mic Volume Gain. Allows setting the Mic Volume attenuator in 32 steps. The LSB represents 1.5 dB, and the
range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
M20Microphone +20 dB Gain Block
0 = Disabled; Gain = 0 dB.
1 = Enabled; Gain = +20 dB.
MCMMic Mute. When this bit is set to “1,” the channel is muted.
Line In Volume (Index 10h)
RLV [4:0]Right Line In Volume. Allows setting the Line In right channel attenuator in 32 steps. The LSB represents
1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
LLV [4:0]Left Line In Volume. Allows setting the Line In left channel attenuator in 32 steps. The LSB represents
1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
AD1819B
CD Volume (Index 12h)
RCV [4:0]Right CD Volume. Allows setting the CD right channel attenuator in 32 steps. The LSB represents
1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
LCV [4:0]Left CD Volume. Allows setting the CD left channel attenuator in 32 steps. The LSB represents
1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
CVMCD Volume Mute. When this bit is set to “1,” the channel is muted.
Video Volume (Index 14h)
RVV [4:0]Right Video Volume. Allows setting the Video right channel attenuator in 32 steps. The LSB represents
1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
LVV [4:0]Left Video Volume. Allows setting the Video left channel attenuator in 32 steps. The LSB represents
1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.Video Mute. When this bit is set to “1,” the channel is muted.
Aux Volume (Index 16h)
RAV [4:0]Right Aux Volume. Allows setting the Aux right channel attenuator in 32 steps. The LSB represents
1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
LAV [4:0]Left Aux Volume. Allows setting the Aux left channel attenuator in 32 steps. The LSB represents
1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.Aux Mute. When this bit is set to “1,” the channel is muted.
PCM Out Volume (Index 18h)
ROV [4:0]Right PCM Out Volume. Allows setting the PCM right channel attenuator in 32 steps. The LSB represents
1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
LOV [4:0]Left PCM Out Volume. Allows setting the PCM left channel attenuator in 32 steps. The LSB represents
1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.PCM Out Volume Mute. When this bit is set to “1,” the channel is muted.
Volume Table (Index 0Ch to 18h)

Partno	Mfg	Dc	Qty	Available	Descript
AD1819BJST		N/a	9	avai	AC?7 SoundPort Codec