AD1816AJS ,SoundPort ControllerApplications Written for Windows 95,Full-Duplex Capture and Playback Operation at®Windows 3.1, Wind ..
AD1816AJS ,SoundPort ControllerSPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Figure 2. PIO Write C ..
AD1819B ,AC?7 SoundPort?CodecSPECIFICATIONSSTANDARD TEST CONDITIONS UNLESS OTHERWISE NOTEDDAC Test ConditionsTemperature 25
AD1816AJS
SoundPort Controller
FEATURES
Compatible with Microsoft® PC 97 Logo Requirements
Supports Applications Written for Windows® 95,
Windows 3.1, Windows NT, SoundBlaster® Pro,
AdLib®/OPL3®
Stereo Audio 16-Bit SD Codec
Internal 3D Circuit—Phat™ Stereo Phase Expander
MPC Level-3 Mixer
ISA Plug and Play Compatible
16-Bit Address Decode
Dual Type F FIFO DMA Support
MPU-401 Compatible MIDI Port
Supports Wavetable Synthesizers
Integrated Enhanced Digital Game Port
Bidirectional DSP Serial Port
Two I2S Digital Audio Serial Ports
Integrated OPL3 Compatible Music Synthesizer
Software and Hardware Volume Control
Full-Duplex Capture and Playback Operation at
Different Sample Rates
Supports Up to Six Different Sample Rates SimultaneouslyHz Resolution Programmable Sample Rates fromkHz to 55.2kHz
Power Management Modes
Operation from +5 V Supply
Built-In 24 mA Bus Drivers
100-Lead PQFP and TQFP Package
FUNCTIONAL BLOCK DIAGRAM
XTALI
XTALO
MIDI_INMIDI_OUT
A_1B_1
A_X
B_XA_2
B_2
A_YB_Y
PHONE_IN
MIC
LINE
SYNTH
VID
L_OUT
R_OUT
PCLKO
SDATA (1)
LRCLK (1)
BCLK (1)
SDATA (0)
LRCLK (0)
BCLK (0)
IOW
IOR
DACK (X)
AEN
PC_A (15:0)
PC_D (7:0)
IRQ (X)
DRQ (X)
SDI
SDO
SCLK
SDFS
DATACLK
SEL
XIRQPHONE_OUT
VOL_UPVOL_DN
SoundPort® Controller
SoundPort is a registered trademark of Analog Devices, Inc.
Phat is a trademark of Analog Devices, Inc.
All other trademarks are the property of their respective holders.AD1816A
PRODUCT OVERVIEWThe AD1816A SoundPort Controller is a single chip Plug and
Play multimedia audio subsystem for concurrently processing
multiple digital streams of 16-bit stereo audio in personal com-
puters. The AD1816A maintains full legacy compatibility with
applications written for SoundBlaster Pro and AdLib, while ser-
vicing Microsoft PC 97 application requirements. The AD1816A
includes an internal OPL3 compatible music synthesizer, Phat
Stereo circuitry for phase expanding the analog stereo output,
an MPU-401 UART, joystick interface with a built-in timer, a
DSP serial port and two I2S serial ports. The AD1816A on-chip
Plug and Play routine provides configuration services for all in-
tegrated logical devices. Using an external E2PROM allows the
AD1816A to decode up to two additional external user-defined
logical devices such as modem and CD-ROM.
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
PRODUCT OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 11
HOST INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
SERIAL INTERFACES . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
ISA INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
AD1816A Chip Registers . . . . . . . . . . . . . . . . . . . . . . . . . 21
AD1816A Plug and Play Device Configuration Registers . . 22
Sound System Direct Registers . . . . . . . . . . . . . . . . . . . . . 23
Sound System Indirect Registers . . . . . . . . . . . . . . . . . . . 29
SB Pro; AdLib Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 38
MPU-401 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Game Port Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
APPENDIX A.
PLUG AND PLAY INTERNAL ROM . . . . . . . . . . . . . .40
PLUG AND PLAY KEY AND “ALTERNATE KEY”
SEQUENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
AD1816 AND AD1816A COMPATIBILITY . . . . . . . . .42
USING AN EEPROM WITH THE AD1816 OR
AD1816A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
AD1816 FLAG BYTE . . . . . . . . . . . . . . . . . . . . . . . . . . .42
USING THE AD1816 WITHOUT AN EEPROM . . . . .42
AD1816A FLAG BYTES . . . . . . . . . . . . . . . . . . . . . . . . 43
USING THE AD1816A WITHOUT AN EEPROM . . . .44
MAPPING THE AD1816 EEPROM INTO THE
AD1816A EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . .45
PIN MUXING IN THE AD1816 AND AD1816A . . . . . 45
PROGRAMMING EXTERNAL EEPROMS . . . . . . . . .47
REFERENCE DESIGNS AND DEVICE DRIVERS . . .47
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 50
TABLE OF CONTENTS
FiguresFunctional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1.PIO Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2.PIO Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3.DMA Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4.DMA Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5.Codec Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6.DSP Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 7.I2S Serial Port Timing . . . . . . . . . . . . . . . . . . . . . . 7
Figure 8.Reset Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 9.Serial Interface Right-Justified Mode . . . . . . . . . . 17
Figure 10.Serial Interface I2S-Justified Mode . . . . . . . . . . . 17
Figure 11.Serial Interface Left-Justified Mode . . . . . . . . . . 17
Figure 12.DSP Serial Interface (Default Frame Rate) . . . . 20
Figure 13.DSP Serial Interface (User Programmed
Frame Rate) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 14.DSP Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 15.Codec Transfers . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 16.Recommended Application Circuit . . . . . . . . . .48
Figure 17.AD1816A Frequency Response Plots . . . . . . . . . 49
TablesTable I.DSP Port Time Slot Map . . . . . . . . . . . . . . . . . . . 18
Table II.Chip Register Diagram . . . . . . . . . . . . . . . . . . . . . 21
Table III.Logical Devices and Compatible Plug and
Play Device Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table IV.Internal Logical Device Configuration . . . . . . . . 23
Table V.Sound System Direct Registers . . . . . . . . . . . . . . . 23
Table VI.Codec Transfers . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table VII.Indirect Register Map and Reset/Default States . 30
Table VIII.Sound System Indirect Registers . . . . . . . . . . . 31
Table IX.SoundBlaster Pro ISA Bus Registers . . . . . . . . . . 38
Table X.AdLib ISA Bus Registers . . . . . . . . . . . . . . . . . . . 39
Table XI.MIDI ISA Bus Registers . . . . . . . . . . . . . . . . . . . 39
Table XII.Game Port ISA Bus Registers . . . . . . . . . . . . . . 39
Table XIII.AD1816 Pin Muxing . . . . . . . . . . . . . . . . . . . . 45
Table XIV.AD1816A Pin Muxing . . . . . . . . . . . . . . . . . . . 46
SPECIFICATIONS
STANDARD TEST CONDITIONS UNLESS
OTHERWISE NOTEDTemperature25°C
Digital Supply (VDD)5.0V
Analog Supply (VCC)5.0V
Sample Rate (FS)48kHz
Input Signal Frequency1008Hz
Audio Output Passband20 Hz to 20 kHz
VIH5.0V
VIL0V
DAC Test Conditions
0 dB Attenuation
Input Full Scale
16-Bit Linear Mode
100 kΩ Output Load
Mute Off
Measured at Line Output
ADC Test Conditions
0 dB Gain
Input –4 dB Relative to Full Scale
Line Input Selected
16-Bit Linear Mode
AD1816A
ANALOG INPUT
PROGRAMMABLE GAIN AMPLIFIER—ADC
CD, LINE, MICROPHONE, SYNTHESIZER, AND VIDEO INPUT ANALOG GAIN/ATTENUATORS/MUTE AT LINE OUTPUT
AD1816A
DIGITAL DECIMATION AND INTERPOLATION FILTERS*
ANALOG-TO-DIGITAL CONVERTERS
DIGITAL-TO-ANALOG CONVERTERS
MASTER VOLUME ATTENUATORS (L_OUT AND R_OUT, PHONE_OUT)
DIGITAL MIX ATTENUATORS*
ANALOG OUTPUTVREFX Output Impedance*
Master Volume Mute Click (Muted Analog Mixers), Muted
SYSTEM SPECIFICATIONS*
STATIC DIGITAL SPECIFICATIONSHigh Level Output Voltage (VOH), IOH = 8 mA†
POWER SUPPLY
CLOCK SPECIFICATIONS*
AD1816A
AD1816A
TIMING PARAMETERS (Guaranteed Over Operating Temperature Range)AEN Setup to IOW/IOR Falling
Data Hold from IOW Rising
DACK Hold from IOW/IOR Rising
Clock [SCLK] to Frame Sync [SDFS]
Clock [SCLK] to Output Data [SDO] Valid*
RESET Pulse Width
NOTES
*Guaranteed, not tested.
†All ISA pins MIDI_OUT IOL = 24 mA. Refer to pin description for individual output drive levels.
Specifications subject to change without notice.
DRQ (0, 1, 3)
DACK (0, 1, 3)
AEN
IOW
PC_D [7:0]
PC_A [15:0]Figure 2.PIO Write Cycle
Figure 1.PIO Read Cycle
Figure 3.DMA Read Cycle
Figure 4.DMA Write Cycle
DATA [7:0]
tBWDN
BYTE NN + 1N + 2N + 3
IOR/IOWFigure 5.Codec Transfers
Figure 6.DSP Port Timing
Figure 7. I2S Serial Port Timing
Figure 8.Reset Pulse Width
AD1816A
ENVIRONMENTAL CONDITIONSAmbient Temperature Rating:
TAMB = TCASE – (PD × θCA)
TCASE = Case Temperature in °C
PD = Power Dissipation in W
θCA = Thermal Resistance (Case-to-Ambient)
θJA = Thermal Resistance (Junction-to-Ambient)
θJC = Thermal Resistance (Junction-to-Case)
ORDERING GUIDE*S = Plastic Quad Flatpack; ST = Thin Quad Flatpack. JST package option
availability subject to 10,000 PC minimum order quantity.
ABSOLUTE MAXIMUM RATINGS**Stresses greater than those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1816A features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
The AD1816A latchup immunity has been demonstrated at ≥ +100 mA/–80 mA on all pins when
tested to Industry Standard/JEDEC methods.
PIN CONFIGURATION
100-Lead PQFP
(S-100)
GNDV
PC_D (0)GNDV
GND
PC_D (1)PC_D (2)PC_D (3)
PC_D (4)PC_D (5)PC_D (6)PC_D (7)
R_VIDL_VID
GNDA
REF
REF_X
R_FILT
L_FILT
R_AAFILT
L_AAFILT
R_LINE
L_LINE
PHONE_IN
MIC
R_SYNTHL_SYNTH
R_CD
L_CD
A_2A_1
IRQ (5)
IRQ (7)
IRQ (9)/IRQ (14)
IRQ (10)/IRQ (4)
IRQ (11)/IRQ (9)/IRQ (4)
IRQ (15)/IRQ (11)
DRQ (0)
DRQ (1)
DRQ (3)
VDD
GND
XCTL1/RING/LD_SEL1
XCTL0/PCLKO/PNPRST
MIDI_OUT
MIDI_IN
GND
XTALO
XTALI
VDD
DACK (0)
DACK (1)
DACK (3)
EE_CLK/GND
EE_DATA/GND
B_X
B_Y
A_X
A_Y
B_1
B_2
I2S0_DATA/VOL_UP
I2S0_LRCLK/VOL_DN
PHONE_OUT
R_OUT
L_OUT
I2S0_BCLK/GND
PC_A (15)
PC_A (14)
PC_A (13)
PC_A (12)
PC_A (11)
PC_A (10)
PC_A (9)
PC_A (8)
PC_A (7)
PC_A (6)
PC_A (5)
PC_A (4)
PC_A (3)
PC_A (2)
PC_A (1)
PC_A (0)
AEN
IOR
VDD
GND
RESET
RX3D
CX3D
IOW
NC = NO CONNECT
I2S1_DATA/IRQ (3)/IRQ (9)I
S1_BCLK/MDM_IRQ
S1_LRCLK/
MDM_SEL
/IRQ (12)/IRQ (13)
SPORT_SCLK/
LD_SEL
/NC
SPORT_SDFS/LD_DRQ/
VOL_UP
SPORT_SDO/
LD_DACK/VOL_DN
/GND
SPORT_SDI/LD_IRQ/
VOL_DN
/GND
AD1816A
PIN CONFIGURATION
100-Lead TQFP
(ST-100)
GNDV
PC_D (0)PC_D (1)PC_D (2)PC_D (3)GNDV
PC_D (4)PC_D (5)PC_D (6)PC_D (7)GNDIRQ (5)IRQ (7)
PHONE_OUT
R_OUTL_OUT
R_VIDL_VID
GNDA
REF
R_FILTL_FILT
R_AAFILT
L_AAFILT
R_LINEL_LINE
PHONE_IN
MIC
R_SYNTH
L_SYNTH
R_CD
L_CD
A_2A_1B_2B_1
IRQ (10)/IRQ (4)
IRQ (15)/IRQ (11)
DRQ (0)
DRQ (1)
DRQ (3)
VDD
GND
XCTL1/RING/LD_SEL1
XCTL0/PCLKO/PNPRST
MIDI_OUT
MIDI_IN
GND
XTALO
XTALI
VDD
DACK (0)
DACK (1)
DACK (3)
EE_CLK/GND
EE_DATA/GND
B_X
B_Y
A_X
A_Y
I2S0_BCLK/GND
PC_A (15)
PC_A (14)
PC_A (13)
PC_A (12)
PC_A (11)
PC_A (10)
PC_A (9)
PC_A (8)
PC_A (7)
PC_A (6)
PC_A (5)
PC_A (4)
PC_A (3)
PC_A (2)
PC_A (1)
PC_A (0)
AEN
IOR
VDD
GND
RESET
RX3D
CX3D
IOW
REF_X
IRQ (9)/IRQ (14)
NC = NO CONNECT
S1_BCLK/MDM_IRQ
S1_DATA/IRQ (3)/IRQ (9)
S1_LRCLK/
MDM_SEL
/IRQ (12)/IRQ (13)
SPORT_SCLK
/LD_SEL
SPORT_SDFS
/LD_DRQ
VOL_UP
SPORT_SDO
LD_DACK
/VOL_DN
/GND
SPORT_SDI
/LD_IRQ
VOL_DN
/GND
S0_DATA
VOL_UP
S0_LRCLK
VOL_DN
IRQ (11)/IRQ (9)/IRQ (4)
PIN FUNCTION DESCRIPTIONS
Analog Signals (All Inputs must be AC-Coupled)
AD1816A
Parallel Interface (All Outputs are 24 mA Drivers)IOR
IOW
Game Port
MIDI Interface Signal (24 mA Drivers)
Muxed Serial Ports (8 mA Drivers)
Miscellaneous Analog Pins
Crystal Pin
External Logical Devices
AD1816A
Hardware Volume Pins
Control PinsXCTL1*
Power SuppliesGNDA
VDD
GND
Optional EEPROM Pins*The position of this pin location/function is dependent on the EEPROM data.
HOST INTERFACEThe AD1816A contains all necessary ISA bus interface logic on
chip. This logic includes address decoding for all onboard
resources, control and signal interpretation, DMA selection and
control logic, IRQ selection and control logic, and all interface
configuration logic.
The AD1816A supports a Type “F” DMA request/grant archi-
tecture for transferring data with the ISA bus through the 8-bit
interface. The AD1816A also supports DACK preemption. Pro-
grammed I/O (PIO) mode is also supported for control register
accesses and for applications lacking DMA control. The
AD1816A includes dual DMA count registers for full-duplex
operation enabling simultaneous capture and playback on sepa-
rate DMA channels.
Codec Functional DescriptionThe AD1816A’s full-duplex stereo codec supports business audio
and multimedia applications. The codec includes stereo audio
converters, complete on-chip filtering, MPC Level-2 and
Level-3 compliant analog mixing, programmable gain and at-
tenuation, variable sample rate converters, extensive digital mixing
and FIFOs buffering the Plug and Play ISA bus interface.
Analog InputsThe codec contains a stereo pair of ∑Δ analog-to-digital con-
verters (ADC). Inputs to the ADC can be selected from the fol-
lowing analog signals: mono (PHONE_IN), mono microphone
(MIC), stereo line (LINE), external stereo synthesizer
(SYNTH), stereo CD ROM (CD), stereo audio from a video
source (VID) and post-mixed stereo or mono line output (OUT).
Analog MixingPHONE_IN, MIC, LINE, SYNTH, CD and VID can be mixed
in the analog domain with the stereo line OUT from the ΣΔ
digital-to-analog converters (DAC). Each channel of the stereo
analog inputs can be independently gained or attenuated from
+12dB to –34.5dB in 1.5dB steps, except for PHONE_IN,
which has a range of 0 dB to –45 dB steps. The summing path
for the mono inputs (MIC, and PHONE_IN to line OUT) du-
plicates mono channel data on both the left and right line OUT,
which can also be gained or attenuated from +12dB to –34.5dB
in 1.5dB steps for MIC, and +0dB to –45.0dB in 3 dB steps
for PHONE_IN. The left and right mono summing signals are
always identical being gained or attenuated equally.
Analog-to-Digital DatapathThe selector sends left and right channel information to the pro-
grammable gain amplifier (PGA). The PGA following the selec-
tor allows independent gain for each channel entering the ADC
from 0dB to 22.5dB in 1.5dB steps.
For supporting time correlated I/O echo cancellation, the ADC
is capable of sampling microphone data on the left channel and
the mono summation of left and right OUT on the right channel.
The codec can operate in either a global stereo mode or a global
mono mode with left channel inputs appearing at both channels of
the 16-bit ΣΔ converters. Data can be sampled at the programmed
sampling frequency (from 4kHz to 55.2kHz with 1Hz resolution).
Digital Mixing and Sample RatesThe audio ADC sample rate and the audio DAC sample rates
Up to four channels of digital data can be summed together and
presented to the stereo DAC for conversion. Each digital chan-
nel pair can contain information encoded at a different sample
rate. For example, 8 kHz .wav data received from the ISA inter-
face, 48 kHz MPEG audio data received from I2S(0), digital
44.1 kHz CD data received from I2S(1) and internally generated
22.05 kHz music data may be summed together and converted
by the DACs.
Digital-to-Analog DatapathThe internally generated music synthesizer data, PCM data
received from the ISA interface, data received from the I2S(0)
port and data received from the I2S(1) port, and the DSP serial
port passes through an attenuation mute stage. The attenuator
allows independent control over each digital channel, which can
be attenuated from 0 dB to –94.5 dB in 1.5 dB steps before be-
ing summed together and passed to the DAC, or the channel
may be muted entirely.
Analog Outputs and Phat StereoThe analog output of the DAC can be summed with any of the
analog input signals. The summed analog signal enters the
Master Volume stage where each channel L_OUT, R_OUT and
PHONE_OUT may be attenuated from 0 dB to –46.5 dB in
1.5 dB steps or muted.
Analog Outputs and Phat StereoThe AD1816A includes ADI’s proprietary Phat Stereo 3D
phase enhancement technology, which creates an increased
sense of spaciousness using two speakers. Our unique patented
feedback technology enables superior control over the width and
depth of the acoustic signals arriving at the human ear. The
AD1816A employs an electrical model of the speaker-to-ear
path allowing precise control over a signal’s phase at the ear. The
Phat Stereo circuitry expands apparent sound images beyond the
angle of the speakers by exploiting phase information in the audio
signal and creating a more immersive listening experience.
Digital Data TypesThe codec can process 16-bit twos complement PCM linear
digital data, 8-bit unsigned magnitude PCM linear data and
8-bit μ-law or A-law companded digital data as specified in the
control registers. The AD1816A also supports ADPCM en-
coded in the Creative SoundBlaster ADPCM formats.
Host-Based Echo Cancellation SupportThe AD1816A supports time correlated I/O data format by pre-
senting MIC data on the left channel of the ADC and the mono
summation of left and right OUT on the right channel. The
ADC sample rates are independent of the DAC sample rate allow-
ing the AD1816A to support ADC time correlated I/O data atkHz and DAC data at any other sample rate in the range ofkHz to 55.2 kHz simultaneously.
Telephony SupportThe AD1816A contains a PHONE_IN input and a
PHONE_OUT output. These pins are supplied so the AD1816A
may be connected to a modem chip set, a telephone handset or
down-line phone.
WSS and SoundBlaster CompatibilityWindows Sound System software audio compatibility is built
into the AD1816A.
AD1816AVirtually all applications developed for SoundBlaster, Windows
Sound System, AdLib and MIDI MPU-401 platforms run on the
AD1816A SoundPort Controller. Follow the same development
process for the controller as you would for these other devices.
As the AD1816A contains SoundBlaster (compatible) and
Windows Sound System logical devices. You may find the
following related development kits useful when developing
AD1816A applications.
Developer Kit for SoundBlaster Series, 2nd ed. © 1993,
Creative Labs, Inc., 1901 McCarthy Blvd., Milpitas, CA 95035
Microsoft Windows Sound System Driver Development Kit (CD),
Version 2.0, © 1993, Microsoft Corp., One Microsoft Way,
Redmond, WA 98052
The following reference texts can serve as additional sources of in-
formation on developing applications that run on the AD1816A.
S. De Furia & J. Scacciaferro, The MIDI Implementation Book,1986, Third Earth, Pompton Lake)
C. Petzold, Programming Windows: the Microsoft guide to writ-
ing applications for Windows 3.1, 3rd. ed., (©1992, Microsoft
Press, Redmond)
K. Pohlmann, Principles of Digital Audio, (©1989, Sams,
Indianapolis)
A. Stolz, The SoundBlaster Book, (©1993, Abacaus, Grand
Rapids)
J. Strawn, Digital Audio Engineering, An Anthology, (© 1985,
Kaufmann, Los Altos)
Yamamoto, MIDI Guidebook, 4th. ed., (©1987, 1989,
Roland Corp.)
Multimedia PC CapabilitiesThe AD1816A is MPC-2 and MPC-3 compliant. This compli-
ance is achieved through the AD1816A’s flexible mixer and the
embedded chip resources.
Music SynthesisThe AD1816A includes an embedded music synthesizer that
emulates industry standard OPL3 FM synthesizer chips and
delivers 20 voice polyphony. The internal synthesizer generates
digital music data at 22.05 kHz and is summed into the DACs
digital data stream prior to conversion. To sum synthesizer data
with the ADC output, the ADC must be programmed for a
22.05 kHz sample rate.
The synthesizer is a hardware
implementation of Eusynth-1+
code that was developed by
Euphonics, a research and devel-
opment company that specializes
in audio processing and electronic
music synthesis.
Wavetable MIDI InputsThe AD1816A has a dedicated analog input for receiving an
analog wavetable synthesizer output. Alternatively, a wavetable
synthesizer’s I2S formatted digital output can be directly con-
MIDIThe primary interface for communicating MIDI data to and from
the host PC is the compatible MPU-401 interface that operates
only in UART mode. The MPU-401 interface has two built-in
FIFOs: a 64-byte receive FIFO and a 16-byte transmit FIFO.
Game PortAn IBM-compatible game port interface is provided on chip.
The game port supports up to two joysticks via a 15-pin D-sub
connector. Joystick registers supporting the Microsoft Direct
Input standard are included as part of the codec register map.
The AD1816A may be programmed to automatically sample the
game port and save the value in the Joystick Position Data Reg-
ister. When enabled, this feature saves up to 10% CPU MIPS
by off-loading the host from constantly polling the joystick port.
Volume ControlThe registers that control the Master Volume output stage are
accessible through the ISA Bus. Master Volume output can also
be controlled through a 2-pin hardware interface. One pin is
used to increase the gain, the other pin attenuates the output
and both pins together entirely mute the output. Once muted, any
further activity on these pins will unmute the AD1816A’s output.
Plug and Play ConfigurationThe AD1816A is fully Plug and Play configurable. For mother-
board applications, the built-in Plug and Play protocol can be
disabled with a software key providing a back door for the BIOS
to configure the AD1816A’s logical devices. For information on
the Plug and Play mode configuration process, see the Plug and
Play ISA Specification Version 1.0a (May 5, 1994). All the
AD1816A’s logical devices comply with Plug and Play resource
definitions described in the specification.
The AD1816A may alternatively be configured using an optional
Plug and Play Resource ROM. When the EEPROM is present,
some additional AD1816A muxed-pin features become avail-
able. For example, pins that control an external modem logical
device are muxed with the DSP serial port. Some of these pin
option combinations are mutually exclusive (see Appendix A for
more information).
REFERENCESThe AD1816A also complies with the following related specifi-
cations; they can be used as an additional reference to AD1816A
operations beyond the material in this data sheet.
Plug and Play ISA Specification, Version 1.0a, © 1993, 1994,
Intel Corp. & Microsoft Corp., One Microsoft Way,
Redmond, WA 98052
Multimedia PC Level 2 Specification, © 1993, Multimedia PC
Marketing Council, 1730 M St. NW, Suite 707, Washington,
DC 20036
MIDI 1.0 Detailed Specification & Standard MIDI Files 1.0,
© 1994, MIDI Manufacturers Association, PO Box 3173
La Habra, CA 90632-3173
Recommendation G.711-Pulse Code Modulation (PCM) Of Voice
Frequencies (μ-Law & A-Law Companding), The International
Telegraph and Telephone Consultative Committee IX Plenary
Assembly Blue Book, Volume III - Fascicle III.4, General
SERIAL INTERFACES2S Serial PortsThe two I2S serial ports on the AD1816A accept serial data in the following formats: Right-Justified, I2S-Justified and Left-Justified.
Figure 9 shows the right-justified mode. LRCLK is HI for the left channel and LO for the right channel. Data is valid on the rising
edge of the BCLK. The MSB is delayed 16-bit clock periods from an LRCLK transition, so that when there are 64 BCLK periods
per LRCLK period, the LSB of the data will be right-justified to the next LRCLK transition.
Figure 9.Serial Interface Right-Justified Mode
Figure 10 shows the I2S-justified mode. LRCLK is LO for the left channel and HI for the right channel. Data is valid on the rising
edge of BCLK. The MSB is left-justified to an LRCLK transition, but with a single BCLK period delay.
Figure 10.Serial Interface I2S-Justified Mode
Figure 11 shows the left-justified mode. LRCLK is HI for the left channel and LO for the right channel. Data is valid on the rising
edge of BCLK. The MSB is left-justified to an LRCLK transition, with no MSB delay.
Figure 11.Serial Interface Left-Justified Mode
Bidirectional DSP Serial InterfaceThe AD1816A SoundPort Controller transmits and receives both data and control/status information through its DSP serial interface
port (SPORT). The AD1816A is always the bus master and supplies the frame sync and the serial clock. The AD1816A has four
pins assigned to the SPORT: SDI, SDO, SDFS and SCLK. The SPORT has two operating modes: monitor and intercept. The
SPORT always monitors the various data streams being processed by the AD1816A. In intercept mode, any of the digital data
streams can be manipulated by the DSP before reaching the final ADC or DAC stages.
The SDI and SDO pins handle the serial data input and output of the AD1816A. Communication in and out of the AD1816A requires
that bits of data be transmitted after a rising edge of SCLK and sampled on the falling edge of SCLK. The SCLK frequency is
always 11 MHz (or 1/3 or XTALI).
DSP Serial Port Interface time slots are mapped as shown in Table I.
AD1816A
Table I.DSP Port Time Slot Map9* I
*This data is ignored by the AD1816A unless the channel pair is in intercept mode (see below).
SS = Sound System Mode
SB = SoundBlaster Mode
At start-up (after pin reset), there are exactly 12 time slots per frame. The frame rate will be 57,291 and 2/3 Hz (11MHz sclk/
[16 bits × 12 slots]). Interfacing with an Analog Devices 21xx family DSP can be achieved by putting the ADSP-21xx in 24 slot per
frame mode, where the first 12 and second 12 slots in the ADSP-21xx frame are identical.
The frame rate can be changed from its default by a write to the DFS(2:0) bits in register 33. Rate choices are: Maximum (57,291
and 2/3Hz default), SS capture rate, SS playback rate, FM rate, I2S Port (1) rate, or I2S Port (0) rate. When the frame rate is less
than 57,261 and 2/3Hz, extra SCLK periods are added to fill up the time. The number of SCLK periods added will vary somewhat
from frame to frame.
To control the sample data flow of each channel through the DSP Port, valid input, valid output and request bits are located in the
control and status words. If the specified channel sample rate is equal to the frame rate, these bits may be ignored since they will
always be set to “1.”
By default, the DSP serial port allows only codec sample data I/O to be monitored. Intercept modes must be enabled to make substi-
tutions in sample data flow to and from the codec. There are five bits in SS register 33, which enable intercept mode for SS capture,
SS playback, FM playback, I2S Port (1) playback and I2S Port (0) playback.
Control Word Input (Slot 0 SDI)141312111098
FCLRRESRESSSCVISSPVIFMVIIS1VIIS0VI
ALIVER/WIA[5:0]
IA [5:0]Indirect Register Address. Sound System Indirect Register Address defines the address of indirect registers shown
in Table VI.
R/WRead/Write request. Either a read from or a write to an SS indirect register occurs every frame. Setting this bit ini-
tiates an SS indirect register read while clearing this bit initiates an SS indirect register write.
ALIVEDSP port alive bit. When set, this bit indicates to the power-down timer that the DSP port is active. When cleared,
this bit indicates that the DSP port is inactive.
IS0VII2S Port 0 Substitution Data Input Valid Flag. This bit is ignored if: (1) Intercept mode is not enabled for the I2S
port 0 channel pair, or (2) The AD1816A did not request data from the I2S port 0 channel pair in the previous
frame. Otherwise, setting this bit indicates that slots 10 and 11 contain valid right and left I2S Port 0 substitution
data. When this bit is cleared, data in slots 10 and 11 is ignored.
IS1VII2S Port 1 Substitution Data Input Valid Flag. This bit is ignored if: (1) Intercept mode is not enabled for I2S port
1 channel pair or (2) The AD1816A did not request data from the I2S port channel pair in the previous frame.
Otherwise, setting this bit indicates that Slots 8 and 9 contain valid right and left I2S Port 1 substitution data.
When this bit is cleared, data in slots 8 and 9 is ignored.
FMVIFM Synthesis Substitution Data Input Valid Flag. This bit is ignored if: (1) Intercept mode is not enabled for the
SSPVISS/SB Playback Substitution Data Input Valid Flag. This bit is ignored if: (1) Intercept mode is not enabled for
SS/SB playback or (2) The AD1816A did not request data for SS/SB playback in the previous frame (see the
SSPRQ bit in the Status Word Output). Otherwise, setting this bit indicates that Slots 4 and 5 contain valid right
and left SS/SB playback substitution data. If in “capture rate equal to playback rate” mode, setting this bit also in-
dicates that valid capture substitution data is being sent to the AD1816A. If not in modem mode, right and left
channel capture substitution data is accepted in Slots 2 and 3 respectively. If in modem mode, only mono capture
substitution data is accepted in slots 2 and 3. When this bit is cleared, data in all slots controlled by this bit, as de-
fined above, is ignored.
SSCVISS/SB Capture Substitution Data Input Valid Flag. This bit is ignored if: (1) Intercept mode is not enabled for SS/
SB capture or (2) The AD1816A did not request data for SS/SB capture in the previous frame (see the SSCRQ
bit in the Status Word Output). Otherwise, setting this bit indicates that valid SS/SB capture substitution data is
being sent to the AD1816A. If not in modem mode, or DSP port or ISA bus based, right and left channel capture
data is accepted in Slots 2 and 3 respectively. If in modem mode, only mono capture substitution data is accepted
in Slot 3, because Slot 2, which is mapped to the right capture channel, is being used for modem. This mono data
will, however, be sent to both left and right ISA SS/SB capture channels. When this bit is cleared, data in Slots 3
and 2 is ignored.
RESReserved:To ensure future compatibility write “0” to all reserved bits.
FCLRDSP Port Clear Status Flag. When this bit is set, (write 1), the PNPR and PDN flag bits in the status word (Bits
15 and 14 of slots 0 SDO) are cleared. When this bit is cleared, (writing a 0), it has no effect on PNPR and PDN
and preserves them in the previous states.
Status Word Output (Slot 0 SDO)141312111098
IS0RQI2S Port (0) Input Request Flag. This bit is set if intercept mode is enabled for I2S Port (0) and its four-word ste-
reo input buffer is not full.
IS1RQI2S Port (1) Input Request Flag. This bit is set if intercept mode is enabled for I2S Port (1) and its four-word ste-
reo input buffer is not full.
FMRQFM Synthesis Input Request Flag. This bit is set if intercept mode is enabled for FM synthesis and its four-word
stereo input buffer is not full.
SSPRQSS/SB Playback Input Request Flag. This bit is set if intercept mode is enabled for SS/SB playback and its four-
word stereo input buffer is not full.
SSCRQSS/SB Capture Input Request Flag. This bit is set if intercept mode is enabled for SS/SB capture and its
four-word stereo input buffer is not full.
MB0Mailbox 0 Status Flag. This bit is set if the most recent action to SS indirect register 42 (DSP port Mail Box 1)
was a write, and is cleared if the most recent action was a read. The status of this bit is also reflected in SS indirect
register 33. It may be used as a handshake bit to facilitate communication between a DSP on the DSP port and a
host CPU on the ISA bus.
MB1Mailbox 1 Status Flag. This bit is set if the most recent action to SS indirect register 43 (DSP port Mail Box 1)
was a write and is cleared if the most recent action was a read. The status of this bit is also reflected in SS indirect
register 33. It may be used as a handshake bit to facilitate communication between a DSP on the DSP port and a
host CPU on the ISA bus.
IS0VOI2S Port 0 Valid Out. This bit is set if Slots 10 and 11 contain valid right and left I2S Port 0 data.
IS1V1I2S Port 1 Valid Out. This bit is set if Slots 8 and 9 contain valid right and left I2S Port 1 data.
FMVOFM Synthesis Valid Out. This bit is set if Slots 6 and 7 contain valid left and right FM synthesis data.
SSPVOSS/SB Playback Valid Out. This bit is set if Slots 4 and 5 contain valid right and left SS/SB playback data.
SSCVOSS/SB Capture Valid Out. This bit is set if valid SS/SB capture data is being transmitted. If not in a modem mode,
Slots 2 and 3 will contain valid right and left SS/SB capture data. If in modem mode, only Slot 3 will contain valid
left SS/SB capture data as Slot 2 and the ADC right channel are used by the modem.
AD1816APNPRPlug and Play Reset flag. This bit is set by an AD1816A reset (RESETB pin asserted LOW) or by a Plug and Play
reset command. This bit is cleared by the assertion of the FCLR bit in the control word. While this bit is set, all at-
tempts to write an SS indirect register via the DSP port will be ignored and fail. This is to ensure that Plug and
Play resets are immediately applied to the application running on the DSP, without requiring them to continuously poll
the Plug and Play reset status bit. During the frame in which this bit is cleared (by asserting FCLR), an attempt to
write an SS indirect register will succeed. If the FCLR bit is continuously asserted, writes to indirect registers via
the DSP port will always be enabled. A Plug and Play reset command will set this PNPR bit HIGH during at least
one frame.
PDNPower-Down flag. This bit is set by an AD1816A reset (RESETB pin asserted LOW), or by an AD1816A power-
down. Before an AD1816A power-down sequence shuts down the DSP port, at least one frame will be sent with
this bit set. This bit can be cleared by the assertion of the FCLR (DSP port status clear) bit in the control word,
providing the AD1816A is no longer in power-down.
The SDFS pin is used for the serial interface frame synchronization. New frames are marked by a one SCLK duration HI pulse,
driven out on SDFS, one serial clock period before the frame begins. Upon initializing, there are exactly 12 time slots per frame and
16 bits per time slot. The frame rate is 57,291 and 2/3 Hz (11 MHz SCLK /(16 bits × 12 slots)). The frame rate can also be changed
from the default value by reprogramming the rate in registers. The frame rate can run at the default rate or be programmed to match
the modem sample rate, ADC capture rate, DAC playback rate, music sample rate, I2S(1) sample rate or I2S(0) sample rate. When
the frame rate is not equivalent to the sample rate, Valid Out, Request In and Valid In bits are used to control the sample data flow.
When the frame rate is equivalent to the sample rate, Valid and Request bits can be ignored.
Figure 12.DSP Serial Interface (Default Frame Rate)
Figure 13.DSP Serial Interface (User Programmed Frame Rate)
Figure 14 illustrates the flexibility of the DSP Serial Port interface. This port can monitor or intercept any of the digital streams man-
aged by the AD1816A.Any ADC or DAC data stream can be intercepted by the port, shipped to an external DSP or ASIC manipu-
lated, and returned to any DAC summing path or to the ADC.
Figure 14.DSP Serial Port
ISA INTERFACE
AD1816A Chip RegistersTable II, Chip Register Diagram, details the AD1816A direct register set available from the ISA Bus. Prior to any accesses by the
host, the PC I/O addressable ports must be configured using the Plug and Play Resources.
Table II. Chip Register DiagramSound System Codec
AD1816AMIDI MPU-401
Game Port
AD1816A Plug and Play Device Configuration RegistersThe AD1816A may be configured according to the Intel/Microsoft Plug and Play Specification using the internal ROM. Alterna-
tively, the PnP configuration sequence may be bypassed using the “Alternate Key Sequence” described in Appendix A.
The operating system configures the AD1816A Plug and Play Logical Devices after system boot. There are no “boot-devices” among
the Plug and Play Logical Devices in the AD1816A. Non-Plug and Play BIOS systems configure the AD1816A’s Logical Devices
after boot using drivers. Depending on BIOS implementations, Plug and Play BIOS systems may configure the AD1816A’s Logical
Devices before POST or after Boot. See the Plug and Play ISA Specification Version 1.0a for more information on configuration con-
trol. To complete this configuration, the system reads resource data from the AD1816A’s on-chip resource ROM or optional
EEPROM and from any other Plug and Play cards in the system, and then arbitrates the configuration of system resources with a
heuristic algorithm. The algorithm maximizes the number of active devices and the acceptability of their configurations.
The system considers all Plug and Play logical device resource data at the same time and makes a conflict-free assignment of re-
sources to the devices. If the system cannot assign a conflict-free resource to a device, the system does not configure or activate the
device. All configured devices are activated.
The system’s Plug and Play support selects all necessary drivers, starts them and maintains a list of system resources allocated to each
logical device. As an option, system resources can be reassigned at runtime with a Plug and Play Resource Manager. The custom
setup created using the manager can be saved and used automatically on subsequent system boots.
Plug and Play Device IDs (embedded in the logical device’s resource data) provide the system with the information required to find
and load the correct device drivers. One custom driver, the AD1816A Sound System driver from Analog Devices, is required for cor-
rect operation. In the other cases (MIDI, Game Port), the system can use generic drivers. Table III lists the AD1816A’s Logical
Devices and compatible Plug and Play device drivers.
Table III.Logical Devices and Compatible Plug and Play Device DriversThe configuration process for the logical devices on the AD1816A is described in the Plug and Play ISA Specification Version 1.0a
(May 5, 1994). The specification describes how to transfer the logical devices from their start-up Wait For Key state to the Config
state and how to assign I/O ranges, interrupt channels and DMA channels. See Appendix A for an example setup program and spe-
cific Plug and Play resource data.
Table IV describes in detail the I/O Port Address Descriptors, DMA Channels, Interrupts for the functions required for the
AD1816A Logical Device groups.
Table IV.Internal Logical Device ConfigurationNOTE
DMA channel 4 indicates single-channel mode.
Sound System Direct RegistersThe AD1816A has a set of 16 programmable Sound System Direct Registers and 36 Indirect Registers. This section describes all the
AD1816A registers and gives their address, name and initialization state/reset value. Following each register table is a list (in ascend-
ing order) of the full register name, its usage and its type: (RO) Read Only, (WO) Write Only, (STKY) Sticky, (RW) Read Write and
Reserved (res). Table V is a map of the AD1816A direct registers.
Table V.Sound System Direct Registers
Direct
AddressBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0SSBASE + 0CRDYVBL INADR[5:0]
SSBASE + 1PICITIVIDIRIGISI
SSBASE + 2Indirect SS Data [7:0]
SSBASE + 3Indirect SS Data [15:8]
SSBASE + 4RESPURCORORR [1:0] ORL [1:0]
SSBASE + 5PFHPDRPLRPULCFHCDRCLRCUL
SSBASE + 6PIO Playback/Capture [7:0]
SSBASE + 7 RESERVED
SSBASE + 8TRDDAZPFMT [1:0]PC/LPSTPIOPEN
SSBASE + 9 RESCFMT [1:0]CC/LCSTCIOCEN
SSBASE + 10RESERVED
SSBASE + 11RESERVED
SSBASE + 12JOYSTICK DATA [7:0]
AD1816A
[Base+0]Chip Status/Indirect Address76543210 RESET = [0x00]
INADR [5:0](RW)Indirect Address for Sound System (SS). These bits are used to access the Indirect Registers shown in Table VIII.
All registers data must be written in pairs, low byte followed by high byte, by loading the Indirect SS Data
Registers, (Base +2) and (Base +3).
VBLVolume Button Location. When using an EEPROM to configure the PnP state of the AD1816A, this bit determines
whether PQFP Pins 1 and 2 (TQFP Pins 99 and 100) are used for VOL_UP and VOL_DN or I2S0_DATA and2S0_LRCLK respectively.2S0_DATA and I2S0_LRCLKVOL_UP and VOL_DN
CRDY (RO)AD1816A Ready. The AD1816A asserts this bit when AD1816A can accept data.AD1816A not readyAD1816A ready
[Base+1]Interrupt Status76543210RESET = [0x00](RO)SoundBlaster generated Interrupt.No interruptSoundBlaster interrupt pending(RW)Game Interrupt (Sticky, Write “0” to Clear).No interruptAn interrupt is pending due to Digital Game Port data ready(RW)Ring Interrupt (Sticky, Write “0” to Clear).No interruptAn interrupt is pending due to a Hardware Ring pin being asserted(RW)DSP Interrupt (Sticky, Write “0” to Clear).No interruptAn interrupt is pending due to a write to the DIT bit in indirect register [33] bit <13>(RW)Volume Interrupt (Sticky, Write “0” to Clear).No interruptAn interrupt is pending due to Hardware Volume Button being pressed(RW)Timer Interrupt. This bit indicates there is an interrupt pending from the timer count registers. (Sticky,
Write “0” to Clear).No interruptInterrupt is pending from the timer count register(RW)Capture Interrupt. This bit indicates that there is an interrupt pending from the capture DMA count register.
(Sticky, Write “0” to Clear).No interruptInterrupt is pending from the capture DMA count register(RW)Playback Interrupt. This bit indicates that there is an interrupt pending from the playback DMA count
register. (Sticky, Write “0” to Clear).No interruptInterrupt is pending from the playback DMA count register
[Base+2]Indirect SS Data Low Byte76543210 RESET = [0xXX]
[Base+3]Indirect SS Data High Byte76543210RESET = [0xXX]
[Base+4]PIO DebugRESPURCORORR[1:0]ORL[1:0] RESET = [0x00]
All bits in this register are sticky until any write that clears all bits to 0.
ORL/ORR(RO)Overrange Left/Right detect. These bits record the largest output magnitude on the ADC right and left
[1:0]channels and are cleared to 00 after any write to this register. The peak amplitude as recorded by these bits is
“sticky,” i.e., the largest output magnitude recorded by these bits will persist until these bits are explicitly
cleared. They are also cleared by powering down the chip.
COR(RO)Capture Over Run. The codec sets (1) this bit when capture data is not read within one sample period after the
capture FIFO fills. When COR is set, the FIFO is full and the codec discards any new data generated. The
codec clears this bit immediately after a 4 byte capture sample is read.
PUR(RO)Playback Under Run. The codec sets (1) this bit when playback data is not written within one sample period af-
ter the playback FIFO empties. The codec clears (0) this bit immediately after a 4 byte playback sample is writ-
ten. When PUR is set, the playback channel has “run out” of data and either plays back a midscale value or
repeats the last sample.
[Base+5]PIO Status76543210RESET = [0x00]
CUL(RO)Capture Upper/Lower Sample. This bit indicates whether the PIO capture data ready is for the upper
or lower byte of the channel.Lower byte readyUpper byte ready or any 8-bit mode
CLR(RO)Capture Left/Right Sample. This bit indicates whether the PIO capture data waiting is for the left channel ADC
or the right channel ADC.Right channelLeft channel or mono
CDR(RO)Capture Data Ready. The PIO Capture Data register contains data ready for reading by the host. This bit should be
used only when direct programmed I/O data transfers are desired (FIFO has at least 4 bytes before full).ADC is stale. Do not reread the informationADC data is fresh. Ready for next host data read
CFH(RO)Capture FIFO Half Full. (FIFO has at least 32 bytes before full.)
PUL(RO)Playback Upper/Lower Sample. This bit indicates whether the PIO playback data needed is for the upper or
lower byte of the channel.Lower byte neededUpper byte needed or any 8-bit mode
PLR(RO)Playback Left/Right Sample. This bit indicates whether the PIO playback data needed is or the left channel
DAC or the right channel DAC.Right channel neededLeft channel or mono
PDR(RO)Playback Data Ready. The PIO Playback data register is ready for more data. This bit should only be used
when direct programmed I/O data transfers are desired (FIFO can take at least 4 bytes).DAC data is still valid. Do not overwriteDAC data is stale. Ready for next host data write value
PFH(RO)Playback FIFO Half Empty. FIFO can take at least 32 bytes, eight groups of 4 bytes.
AD1816A
[Base+6]PIO DataPIO Playback/Capture [7:0]RESET = [0x00]
PIO Playback/The Programmed I/O (PIO) Data Registers for capture and playback are mapped to the same address. Writes
Capture [7:0]send data to the Playback Register and reads will receive data from the Capture Register.
Reading this register will increment the capture byte state machine so that the following read will be from the
next appropriate byte in the sample. The exact byte may be determined by reading the PIO Status Register.
Once all relevant bytes have been read, the state machine will stay pointed to the last byte of the sample
until a new sample is received.
Writing data to this register will increment the playback byte tracking state machine so that the following
write will be to the correct byte of the sample. Once all bytes have been written, subsequent byte writes will be
ignored. The state machine is reset when the current sample is transferred.
Note: All writes to the FIFO “MUST” contain 4 bytes of data.
* 1 sample of 16-bit stereo
* 2 samples of 16-bit mono
* 2 samples of 8-bit stereo (Linear PCM, μ-law PCM, A-Law PCM)
* 4 samples of 8-bit mono (Linear PCM, μ-law PCM, A-Law PCM)
[Base+7]ReservedReserved [7:0]RESET = [0xXX]
[Base+8]Playback Configuration76543210RESET = [0x00]
PEN(RW)Playback Enable. This bit enables or disables programmed I/O data playback.DisableEnable
PIO(RW)Programmed Input/Output. This bit determines whether the playback data is transferred via DMA or PIO.DMA transfers onlyPIO transfers only
PST(RW)Playback Stereo/Mono select. These bits select stereo or mono formatting for the input audio data
streams. In stereo, the Codec alternates samples between channels to provide left and right channel in-
put. For mono, the Codec captures samples on the left channel stereo.MonoStereo
PC/L(RW)Playback Companded/Linear Select. This bit selects between a linear digital representation of the audio signal
or a nonlinear companded format for all output data. The type of linear PCM or the type of companded for-
mat is defined by PFMT [1:0].Linear PCMCompanded
PFMT [1:0](RW)Playback Format. Use these bits to select the playback data format for output data according to Table VI and
Figure 15.
DAZ(RW)DAC zero. This bit forces the DAC to zero.Repeat last sampleForce DAC to ZERO
TRD(RW)Transfer Request Disable. This bit enables or disables Codec DMA transfers during a Codec interrupt (indi-
cated by the SS Codec Status register’s INT bit being set [1]). This assumes Codec DMA transfers were en-
abled and the PEN or CEN bits are set.Transfer Request EnableTransfer Request Disable
