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AD826 ,Low Cost, High Speed, Low Power Dual Operational AmplifierSPECIFICATIONSAParameter Conditions V Min Typ Max UnitSDYNAMIC PERFORMANCEUnity Gain Bandwidth ±5 V ..
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AD826AR ,High-Speed, Low-Power Dual Operational AmplifierSPECIFICATIONSAParameter Conditions V Min Typ Max UnitSDYNAMIC PERFORMANCEUnity Gain Bandwidth ±5 V ..
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AD1803JRU-REEL
Modem/Telephony Codec
REV.0
Modem/Telephony Codec
FEATURES
Low Power Modem Telephony Codec
16-Bit Oversampling �-� Converter Technology
Intel AC’97 Rev 2.1-Compliant Modem Codec
Implementation
AC’97 or DSP Style Serial Interface
Supports All Modem/Fax Standards Including V.90
Multiple Crystal/Clock Rates Supported
Programmable Gain, Attenuation and Mute
On-Chip Signal Filters
Digital Interpolation and Decimation Filters
Analog Output Low Pass
Programmable Sample Rates
From 6.4 kHz to 16 kHz
With 1 Hz, 8/7 Hz and 10/7 Hz Resolution
FUNCTIONAL BLOCK DIAGRAM
Digital Codec Engine with Variable Sample
Rate Conversion
Digital Monitor Speaker Output
24-Lead TSSOP Package
0.6 �m CMOS Technology
Operation from 3.3 V or 5 V Supply
Advanced Power Management
APPLICATIONS
Modems (PC and Embedded)
Voice and Telephony
Fax Machines, Answering Machines, Speakerphones
PBX Systems
Smart Appliances
REFERENCE DESIGN
Available
AD1803–SPECIFICATIONS
STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTEDTemperature25°C
Digital Supply3.3 V/5 V
Analog Supply3.3 V/5 V
Sample Rate (fS)8 kHz
Input Signal1008 Hz
Analog Output Pass Band20 Hz to 4 kHz
ADC FFT Size512
DAC FFT Size4096
VIH2.1 V
VIL1.2 V
VOH2.9 V
VOL0.3 V
IOH–2.0 mA
IOL+2.0 mA
DAC Output Test Conditions
0 dB Attenuation Relative to Full-Scale
Input 0 dB
Mute Off
10 kΩ Output Load
ADC Input Test Conditions
Autocalibrated
0 dB PGA Gain
Mute Off
Input –1.0 dB Relative to Full-Scale
ADC RECEIVE PATHFull-Scale Input Voltage (RMS Values Assume Sine Wave Input, PGA Gain = 0 dB,
Resistance—Rx Input*
Capacitance—Rx Input*
Rx Programmable Gain
Analog-to-Digital Converter
*Guaranteed, not tested.
Specifications subject to change without notice.
DAC TRANSMIT PATHDigital-to-Analog Converter
Programmable Gain/Attenuator
Full-Scale Output Voltage
Pin Capacitance—AD1803 Tx
AD1803
MONITOR OUTPUTNOTES
*Guaranteed, not tested.
Specifications subject to change without notice.
The table above assumes the G[4]/MOUT pin is loaded with a 1 kΩ resistor in series with a parallel 4.7 kΩ resistor and 100 nF
capacitor combination tied to digital ground. This filter, with the output taken from the middle node, has a 1500 Hz corner to filter
out high-frequency Σ-∆ noise, and generates an approximate 1 V p-p output when using a 5 V digital supply with the monitor output
configured as first order (Bits MDM[1:0] set to 10 in Register 0 × 60 Bank 2) if the filter output load is greater than or equal
to 20 kΩ.
DIGITAL DECIMATION AND INTERPOLATION FILTERS1Pass-Band (–3.0 dB Point)
Pass-Band Ripple
Transition Band
Stop-Band Edge
Stop-Band Rejection (Plus 3 dB Roll-Off)
Group Delay
Group Delay Variation Over Pass Band
NOTESGuaranteed, not tested.The stop band repeats itself at multiples of 64 × fS, where fS is the sampling frequency. Thus the digital filter will attenuate to –78.0 dB or better across the frequency
spectrum except for a range ±0.555 × fS wide at multiples of 64 × fS.
Specifications subject to change without notice.
TYPICAL SUPPLY CURRENT (For Most Common Modes of Operation)
AD1803ASSUMPTIONSAssumes all inputs are static (not switching) and all output loads are capacitive (nonresistive).Excludes current drawn by CLKOUT pin board loading.Assumes the serial interface is configured in AC’97 primary mode with 20 pF loads on pins SDATA_IN and BIT_CLK. Typical current will be approximately
0.8mA less if the serial interface is configured in DSP mode with 20 pF loads on pins SYNC, BIT_CLK, and SDATA_IN (due to a lower BIT_CLK frequency).Assumes a 20 pF load on Pin G[4]/MOUT.Assumes the G[4]/MOUT pin is loaded with a 1 kΩ resistor in series with a parallel 4.7 kΩ resistor and 100 nF capacitor combination tied to digital ground. This
filter, with the output taken from the middle node, has a 1500 Hz corner to filter out high-frequency Σ-∆ noise, and generates an approximate 1 V p-p output when
using a 5 V digital supply with the Monitor output configured as first order (Bits MDM[1:0] set to 10 in Register 0 × 60 Bank 2) if the filter output load is greater
than or equal to 20 kΩ.Assumes no DAC load. 0.6mA should be added if a 600 Ω load is used.All currents in mA unless otherwise noted.
Specifications subject to change without notice.
STATIC DIGITAL SPECIFICATIONSHigh Level Input Voltage (VIH): Digital Inputs
Low Level Input Voltage (VIL)
High Level Output Voltage (VOH), IOH = –0.5 mA
Low Level Output Voltage (VOL), IOL = +0.5 mA
Input Leakage Current
Specifications subject to change without notice.
POWER SUPPLYPower Supply Range—Analog (3.3 V/5 V) AVDD
Power Supply Range—Digital (3.3 V/5 V) DVDD
Analog and Digital Supply Current—5 V
Analog and Digital Supply Current—3.3 V
Power Supply Rejection (100 mV p-p Signal @ 1 kHz)
NOTES
*Refer to table on typical supply current.
Specifications subject to change without notice.
CLOCK SPECIFICATIONSInput Clock Frequency
Specifications subject to change without notice.
TIMING PARAMETERS (Guaranteed Over Operating Temperature Range and Supply Power)NOTES
*Output jitter is directly dependent on crystal input jitter.
AD1803Figure 1.Cold RESET
Figure 2.Warm RESET
Figure 3.Clock Timing
Figure 4.Data Setup and Hold
Figure 5.Signal Rise and Fall Time
Figure 6.Propagation Delay
Figure 7.AC Link Low Power Mode Timing
ABSOLUTE MAXIMUM RATINGS**Stresses greater than those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ENVIRONMENTAL CONDITIONSAmbient Temperature Rating
TAMB = TCASE—(PD × θCA)
TCASE = Case Temperature in °C
PD = Power Dissipation in W
θCA = Thermal Resistance (Case-to-Ambient)
θJA = Thermal Resistance (Junction-to-Ambient)
θJC = Thermal Resistance (Junction-to-Case)
PACKAGE CHARACTERISTICS
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1803 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
PIN CONFIGURATION
24-Lead TSSOP
(RU-24)
AD1803
PIN FUNCTION DESCRIPTIONS
Analog SignalsDGND
AVDD
Clock Signals
Serial Interface Signals (See Pins G[3:2] for Serial Interface Mode Selection)
General-Purpose I/O and Barrier Interface Signals
NOTESSee Registers 0x4C through 0x54 and Bank 1 Register 0x60 for G[7:0] (General Purpose I/O) pin control.By default all G[7:0] pins serve as inputs with weak (~30 kΩ equivalent) internal pull-up devices enabled.Input voltage on Pins G[7:2,0] must not exceed DVDD by more than 0.3 V.Input voltage on Pin G[1] must not exceed AVDD by more than 0.3 V.The states of pins G[3:2] are sampled when RESET is deasserted (driven from LOW to HIGH) for the first time after power is applied to select AD1803 serial
interface mode. Once sampled, serial interface mode can be changed only by removing power from the AD1803.
G[3]/WAKE G[2]Serial Interface Mode
HIGHHIGHAC’97 Mode—Primary Device (ID: 00)
HIGHLOWAC’97 Mode—Secondary Device (ID: 01)
LOWHIGHAC’97 Mode—Secondary Device (ID: 10)
LOWLOWDSP Mode
Analog Signals
PRODUCT OVERVIEWThe AD1803 is a low power 16-bit codec for modem, voice,
and telephony applications. It can also be used as a cellular
telephone interface.
The AD1803 is an Intel AC’97 Rev 2.1-compliant modem
codec (refer to Intel’s AC’97 specifications at www.intel.com)
with selectable AC’97 or a DSP-style serial interface.
The AD1803 codec uses high-performance �-� ADC and DACs
with programmable gain/attenuation. It has a digital �-� monitor
output with selectable mix from ADC and DAC channels for
call progress monitoring.
The AD1803 supports advanced power management with
several power-saving modes. The codec supports seven general
purpose I/O pins and a wake interrupt signaling mechanism on
GPIO events.
SERIAL INTERFACE MODE SELECTIONWhen power is first applied to the AD1803, RESET must be
asserted (RESET pin driven LOW), and kept asserted until the
power has stabilized. While RESET is asserted, the AD1803’s
serial interface mode is chosen by the state of Pins 12 and 13:
Pin 12Pin 13Mode ChosenHIGHHIGHAC’97 Mode—Primary Device (ID: 00)
HIGHLOWAC’97 Mode—Secondary Device (ID: 01)
LOWHIGHAC’97 Mode—Secondary Device (ID: 10)
LOWLOWDSP Mode
Note that Pins 12 and 13 have weak pull-up devices internal to
the AD1803 which are enabled by default. Therefore, if these
pins are floated, AC’97 primary mode will be chosen. When
RESET is deasserted (RESET pin driven HIGH) for the first
time after power is applied, the states of Pins 12 and 13 are
latched locking in serial interface mode. Subsequent changes of
logic level presented on Pins 12 and 13 will have no effect on
serial port mode until power is removed from the AD1803.
After this first deassertion of RESET, Pins 12 and 13 will take
on new roles and serve as general purpose I/O control pins. The
AD1803 does not need an active clock source for proper opera-
tion during this mode selection.
SERIAL INTERFACE BEHAVIOR AND PROTOCOL WHEN
IN AC’97 MODEThe AD1803 serial interface is compatible with the Intel’s
“Audio Codec ’97” Revision 2.1 specification as either a pri-
mary or secondary modem/handset codec device. Consult this
specification for complete behavioral details. By default the
AD1803 will use Slot 5 to send and receive sample data,
but this may be changed to Slot 10 or 11. See Bits SPCHN,
SPGBP, SPDSS, SPISO, and SPDL[1:0] in Register 0x5E for
additional AC’97 mode configuration enhancements.
AC’97 Interface Modes
Primary ModeEntered if GPIO[3] pin is HIGH and GPIO[2] pin is HIGH
when RESET pin is deasserted first time:
AD1803 is Timing Master: Drives BIT_CLK @ 12.288 MHz
AD1803 accepts the 48 kHz SYNC Timing Signal
AD1803 requires a crystal or clock on XTALI (see Bits
XTALI[1:0] in Register 0x5C for frequency).
Secondary ModesEntered if GPIO[3] pin is HIGH and GPIO[2] pin is LOW
when RESET pin is deasserted first time or if GPIO[3] pin is
LOW and GPIO[2] pin is HIGH when RESET pin is deasserted
first time:
AD1803 is Timing Slave: Accepts BIT_CLK @ 12.288 MHz
AD1803 accepts the 48 kHz SYNC Timing Signal
AD1803 does not require a crystal or clock on XTALI (see Bits
XTALI[1:0] in Register 0x5C for frequency) unless wake from
an event during RESET is desired.
AD1803
SERIAL INTERFACE BEHAVIOR AND PROTOCOL
WHEN IN DSP MODEIn DSP mode, the AD1803 requires a clock on XTALI to do
anything useful. This clock can be created by placing a crystal
between pins XTALI and XTALO with appropriate trim
capacitors. Alternatively, a clock can be driven directly onto the
XTALI pin from an external source, in which case XTALO
must be floated. When the AD1803 serial interface is configured
in DSP mode, the clock presented on the XTALI pin is assumed
to be 24.576 MHz. However, a 12.288 MHz or 32.768 MHz
clock could be used instead, providing:The AD1803 is informed via a register write what the true
clock frequency is before the codec is enabled; andIt is acceptable to have the serial port Bit clock and frame
sync run at rates different from the start-up nominal until the
AD1803 is informed of the true XTALI clock frequency.
Within 1 ms after RESET is deasserted and the AD1803 receives a
clock on XTALI, the AD1803 will begin driving a 4.096 MHz
Bit clock onto the BIT_CLK pin (assuming a 24.576 MHz
XTALI clock). Approximately 100 µs later, the AD1803 will
begin driving an 8kHz frame sync onto the SYNC pin (again
assuming a 24.576 MHz XTALI clock). If the AD1803 receives an
XTALI clock that is higher/lower than the expected 24.576 MHz
default, these frequencies will be scaled up/down (lineally) until
the AD1803 is informed of the actual XTALI clock frequency by a
write to Bits XTAL[1:0] in Register 0x5C. See Bits XTAL[1:0]
for further details including allowed alternate XTALI frequencies.
Each serial interface frame consists of a single 16-Bit word sent
into the AD1803 on the SDATA_OUT pin, and a single 16-Bit
word sent out of the AD1803 on the SDATA_IN pin. These
words are simultaneously transferred during the first 16 clocks
of the BIT_CLK pin after the start of a frame. The start of a
frame is marked by a one BIT_CLK long HIGH pulse of the
SYNC pin one BIT_CLK period before the first bit in the frame.
Data is transmitted MSB first. Logic levels on all pins (SYNC,
SDATA_IN, and SDATA_OUT) are updated on BIT_CLK
rising edges, and should be sampled on BIT_CLK falling edges.
By default all frames are designated as data frames for deliv-
ery of two’s complement DAC and ADC samples to and from
the AD1803’s codec. To deliver control information into the
possible because of this. If the LSB of the word into the
AD1803 is set to 0, no control frame is requested and the next
frame will be another data frame. If the LSB of the word into
the AD1803 is set to 1, a control frame is requested and the
next frame will be a control frame.
When a control frame is requested, an extra frame is inserted
between data frames avoiding an interruption of codec sample
data flow. The 16-bit control word into the AD1803 consists of,
from MSB to LSB: a register read/write request bit (0 to request
a write, 1 to request a read); the six MSBs of a 7-bit register
address (where the LSB is removed to save space since it’s
always a 0); a byte select bit (0 to select the lower byte of the
16-bit control register addressed, 1 to select the upper byte of
the 16-bit control register addressed); and, finally, eight bits of
data that will be written into the addressed register if a write is
requested. Otherwise, these last eight bits will be ignored. While
it may seem peculiar to have a 7-bit register address with an
always 0 LSB consequently dropped when sent to the AD1803,
it should be noted that AD1803 register addresses are defined
by the AC’97 specification, whether configured in an AC’97 mode
or in DSP mode. While the AC’97 2.1 specification reserves odd
addresses for future feature expansion, there was not room in a
DSP mode control word for this unused bit. The 16-bit control
word out of the AD1803 consists of, from MSB to LSB, eight
unused bits that are always 0s, followed by eight bits of data
that reflect the contents of the register addressed within the
current frame if a read was requested. Otherwise they are all 0s.
When serial interface frames first commence after RESET is
deasserted, there will be 512 bits per frame (8 kHz frame rate/
4.096 MHz bit clock rate) where only the first 16 bits per frame
are typically utilized. Bits out of the AD1803 after the first 16
will typically all be set to 0, and bits into the AD1803 after the
first 16 are typically ignored. However, when a control frame
is requested via the control frame request bit in a data frame, the
control frame will be inserted between data frames, and placed
256 bits after the start of the data frame that requested the control
frame. This control frame will of course be marked by an
additional 1-bit clock long pulse HIGH of the SYNC pin. Note
that the spacing between data frames is always unaffected by
the insertion of a control frame.
Although at Startup the frame rate is 8 kHz and there are
Figure 8.AC’97 Interface Timing
switched from 8 kHz to the programmed codec sample rate,
and whenever the codec is powered down again, the frame
rate will switch back to 8 kHz. With the bit clock always fixed
at 4.096 MHz, this gives rise to a first cause of variation in the
number of bits between starts of data frames. A second cause of
varying number of bits between starts of data frames is the
presence of a subtle jitter in the assertion of frame sync when
the codec is enabled. Although on average there will be an exact
match between the programmed sample rate and the frame rate,
the frame sync itself will vary up to 4% of a sample period from
the ideal assertion point in time.
When the serial interface is in DSP mode, it is possible to access
only the upper or lower 8-bit byte of a 16-bit control register at
a time. While this is sufficient for manipulating many of the
AD1803 features, some features require more than eight control
bits and span multiple 8-bit bytes and/or multiple 16-bit words.
To allow all bits of a feature to take effect simultaneously, writes
to certain control bytes of certain registers are actually held in
holding latches until a particular control byte of the feature is
written. Note that a read of a control register always returns the
contents of a holding latch (if present for that register), which
does not necessarily reflect the control setting currently being
used by the AD1803. The only feature in the AD1803 that
incorporates this complication is the codec sample rate, which
writes to the lower byte of Register 0x40 and does not take
effect until the upper byte of Register 0x40 is written.
Figure 9.Frame Types
Figure 10.Frame Ordering
AD1803
REGISTER BANKSRegister addresses are based on Intel’s AC’97 specification.
However, since the AC’97 specification lacks sufficient vendor-
defined register space to control all extended features of the
AD1803, some control registers must be accessed indirectly using
register banks. See Bits BNK[1:0] in Register 0x5C for details.
REGISTER ACCESS RESTRICTIONSNearly all control registers may be read or written at any time.
However, below is a list of restrictions that must be followed to
ensure proper operation of the AD1803:The clock frequency delivered to the AD1803 on XTALI
must be identified (via a write to Bits XTAL[1:0] in Register
0x5C) before the codec is enabled (via a write of 0 to Bits
DPDN or APDN in Register 0x3E).During ADC calibration, codec sample rate (Register 0x40),
and ADC source and gain level must not be changed, and
digital impedance synthesis (see DISE bit in Register 0x5E)
must not be enabled. Calibration is initiated each time the
AD1803’s ADC is enabled (see Bit APDN in Register 0x3E)
and whenever a 1 is written to Bit ADCAL in Register 0x5C.
Completion of calibration may be determined by polling the
ADCAL bit.
GENERAL-PURPOSE I/O PIN OPERATIONRefer to Registers 0x4C through 0x54 and Bank 1 Register 0x60
for complete details. See Figure 12.
VOICE/HANDSET SUPPORTIn addition to modem applications, the AD1803 can be used for
Voice/Handset support.
Table I.Voice Features
Table II.Input Resistance vs. Gain Setting
STICKY (REG. 0x50[n])
0 = NONSTICKY INPUT
1 = STICKY INPUT
AC '97 MODE SLOT 12, OR
GPIO STATUS (REG. 0x54[n])
WAKE ENABLE (REG. 0x52[n])
OTHER INTERRUPT SOURCESINTERRUPT
DVDD
POLARITY (REG. 0x4E[n])
0 = CMOS
1 = OPEN DRAINS
CONFIG (REG. 0x4C[n])
0 = OUTPUT
1 = INPUT
GPIO[n] OUTPUT DATA
AC'97 MODES: FROM AC-LINK SLOT12
DSP MODE: FROM REG. 0�54Figure 11.Conceptual Diagram of GPIO Pin Behavior
Table III.Register Summary
Table IV.Register Bit Mapping0x5C
0x5E
0x60/1
0x64/1
0x60/2
0x7A
0x7C
Res = Reserved Bit. To ensure future compatibility, reserved bits should be set to “0” when written and ignored when read.
AD1803
REGISTER DESCRIPTION
Extended Modem ID RegisterAddress 0x3CA write to this register has no effect on the states of bits within this register, but does trigger Register 0x3E and Bank 2 Register 0x60
to be cleared to their default states, which powers down the AD1803’s codec resources.
ID[1:0]Interface Identification. These bits may be read to determine the AD1803’s serial interface mode of operation.
Serial interface mode is chosen by the states of Pins 13 and 12 when RESET is deasserted (RESET pin driven
from LOW to HIGH) for the first time after power is applied to the AD1803.
00 = AC-Link Primary (mode chosen if Pin 12 is HIGH and Pin 13 is HIGH on first deassertion of RESET).
01 = AC-Link Secondary (mode chosen if Pin 12 is HIGH and Pin 13 is LOW on first deassertion of RESET).
10 = AC-Link Secondary (mode chosen if Pin 12 is LOW and Pin 13 is HIGH on first deassertion of RESET).
11 = DSP-Link (mode chosen if Pin 12 is LOW and Pin 13 is LOW on first deassertion of RESET).
LIN1Modem Line 1 Supported. For AC’97 compatibility, this bit returns a 1 when read to indicate that the AD1803
supports AC’97 modem line 1 features.
Extended AD1803 Status and ControlDefault = 0xFF00Address 0x3ERes = Reserved Bit. To ensure future compatibility, reserved bits should be set to “0” when written and ignored when read.
This register is forced to its default when: 1) Power is first applied to the AD1803; 2) The RESET pin is driven LOW; or 3) Register
0x3C is written with any value.
DPDNAD1803 DAC Power-Down. When this bit is set to 1 (default), all DAC resources within the AD1803 will be
powered down, and all DAC data sent to the AD1803 over the serial interface will be ignored. When this bit is set
to 0, the digital DAC resources within the AD1803 will be powered up, but the analog DAC resources within
the AD1803 will be powered up only if the AD1803’s voltage reference is powered up (Bit VPDN in this regis-
ter set to 0), and the AD1803’s analog codec is selected as the partner to the AD1803’s digital codec (Bit ACSEL
in Register 0x5C set to 0).
0 = Enable AD1803 Digital DAC Resources, Conditionally Enable AD1803 Analog DAC Resources.
1 = Power-Down All AD1803 DAC Resources (default).
APDNAD1803 ADC Power-Down. When this bit is set to 1 (default), all ADC resources within the AD1803 will be
powered down, and all ADC data words sent out of the AD1803 over the serial interface will be midscale (zero)
(and tagged invalid if the serial interface is configured in an AC’97 mode). When this bit is set to 0, the digital
ADC resources within the AD1803 will be powered up, but the analog ADC resources within the AD1803 will be
powered up only if both the AD1803’s voltage reference is powered up (Bit VPDN in this register set to 0), and
the AD1803’s analog codec is selected as the partner to the AD1803’s digital codec (Bit ACSEL in Register 0x5C
set to 0). Each time the AD1803’s analog codec is powered up, an ADC DC offset calibration is automatically
initiated. This calibration requires approximately 104 sample periods (defined by Register 0x40), but cannot be
started until after the AD1803’s voltage reference is powered up (by setting Bit VPDN in this register to 0),
which itself requires about 48 ms. Bit VSTA in this register may be polled first to determine if the voltage reference
is powered up, and then Bit ADCAL in Register 0x5C may be polled to determine if calibration is completed.
During calibration, codec sample rate, ADC source, and ADC gain level must not be changed.
0 = Enable AD1803 Digital ADC Resources, Conditionally Enable AD1803 Analog ADC Resources.
1 = Power-Down All AD1803 ADC Resources (default).
VPDNAD1803 Voltage Reference Power-Down. Writes to this bit initiate codec voltage reference power-up and power-
down sequences. Bit VSTA in this register may be polled to monitor current voltage reference status. Until the
voltage reference is fully powered up, the AD1803’s analog ADC and DAC channels will ignore the setting of Bits
APDN and DPDN and remain powered down.
0 = Enable Voltage Reference.
1 = Power-Down Voltage Reference (default).
