AD1385KD ,16-Bit 500 kHz Wide Temperature Range Sampling ADCCHARACTERISTICS±10 V FSR, V = –0.4 dB, T to TIN MIN MAXSample Rate 500 500 kHz5Signal-to-Noise Rati ..
AD1580-A ,1.2 V Micropower, Precision Shunt Voltage ReferenceFEATURESSOT-23 PackageWide Operating Range: 50 mA–10 mAInitial Accuracy: 60.1% maxTemperature Drift ..
AD1580ART ,1.2 V Micropower, Precision Shunt Voltage ReferenceSpecifications subject to change without notice.1ABSOLUTE MAXIMUM RATINGSORDERING GUIDEReverse Curr ..
AD1580ART-REEL ,1.2 V Micropower, Precision Shunt Voltage ReferenceSpecifications subject to change without notice.ORDERING GUIDE1ABSOLUTE MAXIMUM RATINGSInitialRever ..
AD1580ART-REEL7 ,1.2 V Micropower, Precision Shunt Voltage ReferenceSPECIFICATIONSA INModel AD1580A AD1580BMin Typ Max Min Typ Max UnitsReverse Volta ..
AD1580ARTZ-REEL7 , 1.2 V Micropower, Precision Shunt Voltage Reference
AD8196ACPZ , 2:1 HDMI/DVI Switch with Equalization
AD8196ACPZ-R7 , 2:1 HDMI/DVI Switch with Equalization
AD8197B ,4:1 HDMI/DVI Switch with EqualizationFEATURES FUNCTIONAL BLOCK DIAGRAM 4 inputs, 1 output HDMI/DVI links Enables HDMI 1.3-compliant rece ..
AD820 ,Single Supply, Precision, Rail to Rail Low Power FET-Input Op AmpAPPLICATIONS3 V/µs slew rate are provided for a low supply current of 800 µA.Battery-Powered Precis ..
AD8200 ,High COmmon-Mode Voltage, Single Supply Difference AmplifierSpecifications subject to change without notice.–2– REV. AAD8200ABSOLUTE MAXIMUM RATINGS* PIN CONFI ..
AD8200YR , High Common-Mode Voltage, Single-Supply Difference Amplifier
AD1385KD
16-Bit 500 kHz Wide Temperature Range Sampling ADC
FUNCTIONAL BLOCK DIAGRAMREV.0
16-Bit 500 kHz
Wide Temperature Range Sampling ADC
FEATURES
16-Bit Resolution
500 kHz Sampling Rate
Differential Linearity Autocalibration
Specified over –558C to +1258C Range
SNR 90 dB @ 100 kHz (min)
THD –88 dB @ 100 kHz (min)
0.0006% FSR DNL (typ)
0.0015% FSR INL (typ)
No Missing Codes65, 610 V Bipolar Input Ranges
Zero Offset Autocalibration
APPLICATIONS
Medical Imaging
CAT
Magnetic Resonance
Radar
Vibration Analysis
Parametric Measurement Unit (ATE)
Digital Storage Oscilloscopes
Waveform Recorders
Analytical Instruments
PRODUCT DESCRIPTIONThe AD1385 is a complete 500 kHz, 16-bit, sampling analog-
to-digital converter contained in a single package. Its differential
linearity autocalibration feature allows this high resolution, high
speed converter to offer outstanding noise and distortion perfor-
mance, as well as excellent INL and DNL specifications, over
the full military temperature range. Autocalibration effectively
eliminates DNL drift over temperature.
The AD1385 architecture includes a low noise, low distortion
track/hold, a three pass digitally corrected subranging ADC, and
linearity calibration circuitry. A complete linearity calibration
requires only 15 ms. Precision thin-film resistors and a propri-
etary DAC contribute to the part’s outstanding dynamic and
static performance.
The AD1385 uses four power supplies, ±5 V and ±15 V, and an
external 10 MHz clock. Power dissipation is nominally 2.76 W.
Two user selectable bipolar input ranges, ±5 V and ±10 V, are
provided. Careful attention to grounding and a single package
make it easy to design PCBs to achieve specified performance.
The AD1385’s pinout is nearly identical to that of the AD1382,
a factory calibrated 16-bit, 500 kHz SADC. Just two additional
connections, to enable and monitor autocalibration, are required.
This commonality provides an easy upgrade path to extend sys-
tem performance and operating temperature range.
AD1385–SPECIFICATIONS
(TA = +258C, VS = 615 V, VDD = +5 V, VSS = –5 V, 10 MHz External Clock,
unless otherwise noted)
NOTESIntegral linearity is inferred from FFTs. Differential linearity is derived from histograms.Performance over temperature is specified at the temperature at which the last calibration was performed.FSR = Full-Scale Range.Adjustable to zero.SNR excludes harmonics 2-9 of the fundamental.THD includes harmonics 2-9 of the fundamental.Aperture delay is the time from the rising edge on the Hold Command Input to the opening of the switch in the Track/Hold.
Specifications subject to change without notice.
TIMING SPECIFICATIONS1, 2NOTESRefer to Figures 17, 18 and 24.
AD1385
(TA = –558C to +1258C, VS = 615 V, VDD = +5 V, VSS = –5 V)
AD1385
ABSOLUTE MAXIMUM RATINGS*+VS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 V
–VS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–18 V
VDD to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 V
VSS to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–7 V
AGND to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . .±0.3 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±VS
Reference Input . . . . . . . . . . . . . . . . . . . . . . . . . .0 V to +11 V
Digital Inputs . . . . . . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Output Short Circuit Duration
Reference Output . . . . . . . . . . . . . . . . . . . . . . . . .Indefinite
Track/Hold Output . . . . . . . . . . . . . . . . . . . . . . . . . . .1 sec
Digital Outputs . . . . . . . . . . . . . .1 sec for Any One Output
Case Temperature (Operating) . . . . . . . . . .–55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . .–65°C to +150°C
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE*DH-48A = Bottom Brazed Ceramic DIP.
AD1385 PIN CONNECTIONSThe AD1385 is housed in a 48-pin bottom-brazed ceramic
bathtub package. The pinout is as follows:
DNC = DO NOT CONNECT.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1385 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
Figure 4.Full-Scale Sine Wave Power Spectral Density,
±5 V Range, 16384-Point FFT, 500 kHz Sample Rate
Figure 5.Full-Scale Sine Wave Power Spectral Density,
±5 V Range, 16384-Point FFT, 500 kHz Sample Rate
Figure 6.100 kHz Intermodulation Performance, ±5 V
Range, 16384-Point FFT, 500 kHz Sample Rate
Figure 1.Spurious-Free Range vs. Input Amplitude,
±5 V Range, 2048-Point FFT, 500 kHz Sample Rate
Figure 2.Spurious-Free Range vs. Input Amplitude,
±10 V Range, 2048-Point FFT, 500 kHz Sample Rate
Figure 3.Full-Scale Sine Wave Power Spectral Density,
±5 V Range, 16384-Point FFT, 500 kHz Sample Rate
AD1385Figure 7.200 kHz Intermodulation Performance, ±5 V
Range, 16384-Point FFT, 500 kHz Sample Rate
Figure 8.Full-Scale Sine Wave Power Spectral Density,
±10 V Range, 16384-Point FFT, 500 kHz Sample Rate
Figure 9.Full-Scale Sine Wave Power Spectral Density,
±10 V Range, 16384-Point FFT, 500 kHz Sample Rate
Figure 10.Full-Scale Sine Wave Power Spectral Density,
±10 V Range, 16384-Point FFT, 500 kHz Sample Rate
Figure 11.100 kHz Intermodulation Performance, ±10 V
Range, 16384-Point FFT, 500 kHz Sample Rate
Figure 12.200 kHz Intermodulation Performance, ±10 V
Range, 16384-Point FFT, 500 kHz Sample Rate
Figure 13.AD1385 Functional Block Diagram
THEORY OF OPERATIONThe AD1385 performs conversions using a three-pass subrang-
ing technique. This proven circuit concept, implemented with
state of the art components, allows the ADC, track-hold, and a
low noise reference to fit into a single hermetic package, simpli-
fying the task of board design. The T/H and ADC portions of
the AD1385 are distinct circuits with inputs and outputs avail-
able on separate pins. This functional division allows greatest
application flexibility. The AD1385’s major functional blocks
are shown in Figure 13.
The T/H uses a low noise high performance hybrid amplifier and
high speed analog switches to achieve precision performance. It
operates as an inverting amplifier during Track mode. Summing
junction switch S1 disconnects the analog input to place the cir-
cuit into Hold mode; the amplifier’s output stays constant because
the dc path to its inverting input is broken. S1 also grounds the
junction of R1 and R2 to minimize signal feedthrough. Pedestal
is independent of the analog input level because all switching
is done near ground. This ensures very low nonlinearity and
distortion.
A precision Reference DAC and an 8-bit flash ADC form the
heart of the AD1385’s subranging design. High speed amplifiers
combine the analog input and DAC output to produce the volt-
ages encoded by the flash ADC during each pass. A logic array
provides all necessary timing, control, and computation.
The first rising clock edge after Start Convert goes high begins
the conversion (provided the previous conversion is complete).
The Hold Command goes high and switches the T/H into hold.
The held signal from the T/H goes through S2, S3, and Error
Amp 2 to the flash ADC. During this pass Error Amp 2 actually
attenuates the ADC input to keep the voltage within the flash
ADC’s input range. The flash ADC is strobed after a 100 ns
settling period. The 8-bit result is saved in the logic array and is
routed to the MSBs of the Reference DAC.
Error Amp 1 amplifies the difference between the Reference
S4 routes this error signal to the flash ADC, which is strobed a
second time after Error Amp 1 has settled. The new 8-bit result
is used to correct the previous result, increasing the accuracy of
this intermediate answer to 13-bit precision. Following this the
Reference DAC is updated.
Both error amplifiers are active during the third pass. S2 is
closed, allowing Error Amp 2 to amplify Error Amp 1’s output.
S3 now brings Error Amp 2’s output to the flash ADC. The
flash ADC is strobed a final time after the DAC and both error
amplifiers have settled. The logic array combines the data from
the third flash conversion with the earlier 13-bit word to pro-
duce the final 16-bit result. The T/H is returned to track mode,
and Error Amp 2 is reconnected as an attenuator 50 ns after the
completion of the third flash conversion to prepare for the next
conversion.
The output data are placed on the data bus in two 8-bit bytes
to be read by the host system. The Data Strobe output synchro-
nizes the data transfer by providing a rising edge for the first
byte and a falling edge for the second byte. The Hi/Lo Byte
Select input allows the user to choose which data byte is pre-
sented first. B1 Select sets the polarity of the MSB to provide
either complementary twos complement or complementary off-
set binary data.
The AD1385’s internal linearity calibration capability may be
used to compensate for shifts in Reference DAC linearity with
time and temperature. The calibration sequence uses the
AD1385’s error amplifiers and flash converter to directly mea-
sure Reference DAC linearity errors. The routine calculates the
Corrections required to each of the Reference DAC’s 8 MSBs
and stores these in an internal memory; the memory address is
determined by the Reference DAC’s codes. The RAM data con-
trol a Correction DAC whose output is summed with the Refer-
ence DAC’s output. Together the two DACs provide the 18-bit
linearity required for accurate A/D conversions. Calibration
corrects only linearity errors, and has a negligible effect on
gain and offset errors. A calibration cycle requires 15 ms and
AD1385
CONNECTION AND OPERATION OF THE AD1385
Analog InputThe analog input should be connected to the Track/Hold Input
(Pin 25). Two pin programmable operating ranges are available:
±5 V and ±10 V. Connect the Track/Hold Output to VIN A and/
or VIN B as follows:
Harmonic distortion is lower when using the ±5 V range, while
noise is lower when using the ±10 V range.
The AD1385’s noise and distortion performance exceed the
capability of most signal sources. Maintaining this performance
at the system level requires attention to every detail of ground-
ing, bypassing, and signal sources. A low impedance high band-
width signal source is essential to achieve low distortion. Few
monolithic amplifiers exist which can maintain signal fidelity at
levels comparable with the AD1385’s performance, even at low
frequencies. High bandwidth means increased noise and de-
creased SNR. See Testing the AD1385 for techniques of achiev-
ing the lowest possible noise and distortion.
GroundingProper treatment of the AD1385’s power and ground connec-
tions is vital to achieve the best possible system performance.
The ideal grounding arrangement is to have a single, solid, low
impedance ground plane beneath the device to which all ground
and supply bypassing connections are made. This results in the
lowest possible ground noise and minimizes undesired interac-
tions between the sensitive circuits inside the AD1385. Aperture
uncertainty, for example, can be degraded by noise in Power
Ground because the Hold Command signals are referenced to
this ground. The digital interface between the AD1385 and the
rest of the user’s system is also critical. The following discussion
will help in obtaining optimal performance. These guidelines are
general and apply equally well to other high performance analog
and digital circuits.
The AD1385 must connect to three other parts of the system:
the input signal(s), the power supplies, and the digital interface.
The system designer must determine the magnitude and type of
ground currents and whether they are constant or dynamic. A
system block diagram is a valuable aid to understanding how
grounds should be connected for good performance. Figure 14
shows recommended ground connections for the AD1385 in a
typical system.
The AD1385 has a net ground current of about 40 mA. Most of
this flows in the power grounds. There are also substantial dy-
namic currents in the power grounds. The signal grounds have
primarily low level static (dc) currents. Signal and power
grounds are separated inside the hybrid because the resistance
and inductance inherent in thick-film construction would cause
interactions between ground currents, leading to poor perfor-
mance. (Remember that an LSB can be as small as 156 μV.)
Care must be taken to prevent the AD1385’s ground currents
from flowing in the signal ground between the signal source and
the AD1385 if this ground has significant resistance. This is not
usually a problem if the signal source is located on the same
board as the AD1385 because the resistance can be made very
low through the use of a ground plane.
The signal source’s ground and supply currents must be consid-
ered when the source and ADC share common power supplies.
A ground loop formed by the AD1385, the signal source, and
the power supplies can cause significant errors.
The connection between the AD1385’s ground plane and the
system’s digital ground is best made away from the AD1385.
This will prevent noisy system ground currents from passing
through critical parts of the ADC. In a very noisy environment it
may be wise to isolate the entire analog circuit. Figure 14 shows
the required isolation provided by a digital buffer. The buffer
can then drive resistive and/or capacitive loads without compro-
mising ground at the ADC. Using separate isolated supplies for
the ADC and signal source will result in a single-point connec-
tion between system digital ground and the ADC’s ground plane
at the digital buffer.
Power Supplies and BypassingThe AD1385 has four sets of power supply pins. These are:
±5 V Analog(VDD1/VSS1)
±15 V(+VS1/–VS1)
±15 V(+VS2/–VS2)
±5 V Power(VDD2/VSS2)
A single source may be used to supply like voltages (e.g., VDD1,
VDD2 from the same +5 V supply). Each of the four ±5 V supply
pins should have a distinct low impedance connection to a
well-bypassed central source node. This is required because
each pin draws large transient currents. These dynamic cur-
rents, if passed through a common supply path, would intro-
duce crosstalk and increase the AD1385’s apparent noise. The
two sets of ±15 V supplies need not be split in this fashion.
Every AD1385 supply pin should be bypassed to the ground
plane with a high quality ceramic capacitor of 0.01 μF to 0.1 μF.
This capacitor should be located as close as possible to the
AD1385 to minimize lead lengths. Each VDD and VSS pin must
also be bypassed to the ground plane with a 10 μF solid tanta-
lum bypass capacitor located close to the AD1385. Ten micro-
farad bypass capacitors for ±VS2 (Pins 21 and 23) are also
necessary. These power distribution concepts are shown in
Figure 15.
All power supplies should be of the linear type. Switching power
supplies are not recommended as they can introduce consider-
able high frequency noise into sensitive analog signal paths, de-
DIGITAL INTERFACES
10 MHz ClockThe AD1385 requires a stable external clock. A 10 MHz clock
provides a sample rate of 500 kilosamples per second. Since
the ADC operates synchronously with this clock, clock phase
noise will appear as jitter in the aperture time. Lower clock
frequencies may be used, and the sample rate will be reduced
proportionately.
Standard TTL and CMOS crystal oscillator modules may be
used successfully to generate the required 10 MHz clock signal.
These oscillators often create considerable power supply tran-
sient noise. The oscillator should be bypassed with both ce-
ramic and solid tantalum capacitors using minimum lead
lengths. A 10 Ω resistor in series with the +5 V supply provides
additional isolation and low-pass filtering of transients pro-
duced by the oscillator. See Figure 16.
Figure 16.Isolating Clock Noise. Bypass Capacitors
Should Be Located Close to the Oscillator
Transmission line effects cannot be ignored when supplying the
AD1385’s 10 MHz clock. The large impedance mismatch be-
tween typical PCB traces and the AD1385’s CMOS clock input
can give rise to reflections and high frequency transients when
the 10 MHz clock source is located more than a few inches
from the AD1385. This noise can corrupt local ground and
cause degradation in the AD1385’s apparent SNR perfor-
mance. A series termination resistor of 50 Ω to 100 Ω, located
at the clock source, will usually eliminate this problem.
START CONVERT (PIN 18)
Synchronous OperationThe Start Convert signal acts like the data input of a flip-flop. A
conversion begins on the first rising clock edge after Start Con-
vert goes high (provided setup time requirements are met). This
edge drives Hold Command Out high, switching the T/H into
Hold mode. Hold Command Out (Pin 19) should be connected
to Hold Command In (Pin 22) for synchronous operation.
Continuous conversions at a 500 kHz rate may be obtained by
holding Start Convert high. The 10 MHz clock may be divided
down and used to drive the Start Convert input when a lower
conversion rate is desired. This will provide clock-synchronized
conversions at the lower rate. Synchronous conversion timing is
shown in Figures 17 and 18.
Start Convert may also be used as a gate to capture data in a
time window. The rising and falling edges of Start Convert
define the beginning and end of the window during which
conversions are desired.
Some restrictions apply when using a pulse to drive the Start
Convert input. Start Convert is ignored during a conversion for
Figure 15.Recommended AD1385 Power Distribution. All
10 μF and 0.01 μF capacitors must have minimum lead
length and be located as close as possible to the by-
passed pins. Make all ground connections directly to the
groundplane.
If separate ground planes are used for Signal and Power
Ground, the supplies should be bypassed as follows:
SupplyBypass to±5 V AnalogSignal Ground
±15 V (+VS1/–VS1)Signal Ground
±15 V (+VS2/–VS2)Power Ground
±5 V PowerPower Ground
Care is also required when using a +5 V powered crystal oscil-
lator to provide the AD1385’s clock signal. These devices produce
considerable supply noise and proper bypassing is essential.
The oscillator should be bypassed with both ceramic and solid
tantalum capacitors using minimum lead lengths. A 10 Ω resis-
tor in series with the +5 V supply provides additional isolation
and low pass filtering of transients produced by the oscillator.
ReferenceThe AD1385 has an excellent internal reference with a typical
temperature coefficient of 5 ppm/°C. The Reference Out (Pin
39) is normally connected to Reference In (Pin 32). An exter-
nal reference may be connected to the reference input if desired.
The reference input pin requires negligible current. The refer-
ence input voltage should not exceed +11 V and must remain
more positive than 0 V. The reference output requires no by-
passing and should not be capacitively loaded. If an external
reference is used, it must have low noise to avoid degrading the
signal to noise ratio of the AD1385.
The reference output can source up to 2 mA of static (dc) cur-
rent without affecting the performance of the AD1385. By using
the AD1385’s internal reference as the system reference, gain
AD1385Figure 17.Start-Convert Controlled Conversion Timing
Figure 18.Free Running Conversion Timing
At this point a new conversion will be initiated. The minimum
setup and hold times for Start Convert relative to the rising
clock edge are 10 ns. Start Convert transitions should not be
placed in the window which begins 100 ns (one clock period)
after the rising edge of Hold Command Out and which ends
1300 ns (thirteen clock periods) after this rising edge (see Fig-
ure 17). This minimizes internal coupling between Start Con-
vert and sensitive internal circuit nodes.
Transmission line effects at the Start Convert input should be
considered when designing circuit boards for the AD1385. A se-
ries termination resistor of 50 Ω to 100 Ω is recommended when
the source of Start Convert is more than a few inches away from
the AD1385. This will control reflections and transients which
could otherwise degrade the part’s performance.
Asynchronous OperationIn synchronous operation the T/H is placed into Hold mode by
the first rising clock edge after Start Convert goes high. This
rising edge of Start Convert places the T/H into Hold mode; the
A/D conversion cycle begins with the first rising clock edge after
the Start Convert transition, and Start Convert must remain
high during at least one rising clock edge in order to begin the
conversion. The width of Start Convert should be either less
than 150 ns or greater than 1400 ns to minimize coupling be-
tween the falling edge of Start Convert and sensitive internal
nodes. In asynchronous operation the T/H will remain in Hold
