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AD1380JD-AD1380KD
Low Cost 16-Bit Sampling ADC
REV.B
Low Cost
16-Bit Sampling ADC
FUNCTIONAL BLOCK DIAGRAM
PRODUCT DESCRIPTIONThe AD1380 is a complete, low cost 16-bit analog-to-digital
converter, including internal reference, clock and sample/hold
amplifier. Internal thin-film-on-silicon scaling resistors allow
analog input ranges of ±2.5V, ±5V, ±10V, 0V to +5V andV to +10V.
Important performance characteristics of the AD1380 include
maximum linearity error of ±0.003% of FSR (AD1380KD) and
maximum 16-bit conversion time of 14μs. Transfer characteris-
tics of the AD1380 (gain, offset and linearity) are specified for
the combined ADC/SHA, so total performance is guaranteed as
a system. The AD1380 provides data in parallel and serial form
with corresponding clock and status outputs. All digital inputs
and outputs are TTL or 5V CMOS compatible.
FEATURES
Complete Sampling 16-Bit ADC With Reference and
ClockkHz Throughput61/2
LSB Nonlinearity
Low Noise SHA:300mV p-p
32-Pin Hermetic DIP
Parallel and Serial Outputs
Low Power:900mW
APPLICATIONS
Medical and Analytical Instrumentation
Signal Processing
Data Acquisition Systems
Professional Audio
Automatic Test Equipment (ATE)
Telecommunications
AD1380–SPECIFICATIONSNOTESLogic “0” = 0.8V, max. Logic “1” = 2.0 V, min for inputs. For digital outputs Logic “0” = 0.4 V max. Logic “1” = 2.4 V min.Tested on ±10 V and 0V to +10 V ranges.Adjustable to zero.
(typical @ TA = +258C, VS = +15V, +5V combined sample-and-hold A/D converter
unless otherwise noted)
THEORY OF OPERATIONA 16-bit A/D converter partitions the range of analog inputs into16 discrete ranges or quanta. All analog values within a given
quantum are represented by the same digital code, usually as-
signed to the nominal midrange value. There is an inherent
quantization uncertainty of ±1/2LSB, associated with the reso-
lution, in addition to the actual conversion errors.
The actual conversion errors that are associated with A/D con-
verters are combinations of analog errors due to the linear cir-
cuitry, matching and tracking properties of the ladder and
scaling networks, reference error and power supply rejection.
The matching and tracking errors in the converter have been
minimized by the use of monolithic DACs that include the
scaling network. The initial gain and offset errors are specified
at ±0.1% FSR for gain and ±0.05% FSR for offset. These errors
may be trimmed to zero by the use of external trim circuits as
shown in Figures 2 and 3. Linearity error is defined for unipolar
ranges as the deviation from a true straight line transfer charac-
teristic from a zero voltage analog input, which calls for a zero
digital output, to a point which is defined as a full scale. The
linearity error is based on the DAC resistor ratios. It is unadjust-
able and is the most meaningful indication of A/D converter
accuracy. Differential nonlinearity is a measure of the deviation
in the staircase step width between codes from the ideal least
significant bit step size (Figure 1).
Monotonic behavior requires that the differential linearity error
be less than 1LSB; however, a monotonic converter can have
missing codes. The AD1380 is specified as having no missing
codes over temperature ranges as specified on the data page.
ABSOLUTE MAXIMUM RATINGSSupply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18V
Logic Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . +7V
Analog Ground to Digital Ground . . . . . . . . . . . . . . . . ±0.3V
Analog Inputs (Pins 6, 7, 31) . . . . . . . . . . . . . . . . . . . . . . ±VS
Digital Input . . . . . . . . . . . . . . . . . . . . –0.3V to VDD +0.3V
Output Short Circuit Duration to Ground
Sample/Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . Indefinite
Data . . . . . . . . . . . . . . . . . . . . . . 1 sec for Any One Output
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +175°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +300°C
ORDERING GUIDEThere are three types of drift error over temperature: offset, gain
and linearity. Offset drift causes a shift of the transfer character-
istic left or right on the diagram over the operating temperature
range. Gain drift causes a rotation of the transfer characteristic
about the zero for unipolar ranges or minus full-scale point for
bipolar ranges. The worst case accuracy drift is the summation
of all three drift errors over temperature. Statistically, however,
the drift error behaves as the root-sum-squared (RSS) and can
be shown as: RSS=∈G
∈G = Gain Drift Error (ppm/°C)
∈O = 0ffset Drift Error (ppm of FSR/°C)
∈L = Linearity Error (ppm of FSR/°C)
Figure 1.Transfer Characteristics for an Ideal Bipolar A/D
DESCRIPTION OF OPERATIONOn receipt of a CONVERT START command, the AD1380
converts the voltage at its analog input into an equivalent 16-bit
binary number. This conversion is accomplished as follows: the
16-bit successive approximation register (SAR) has its 16-bit
outputs connected to both the device bit output pins and the
corresponding bit inputs of the feedback DAC. The analog
input is successively compared to the feedback DAC output,
one bit at a time (MSB first, LSB last). The decision to keep
or reject each bit is then made at the completion of each bit
comparison period, depending on the state of the comparator
at that time.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1380 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
AD1380
GAIN ADJUSTMENTThe gain adjust circuit consists of a 100ppm/°C potentiometer
connected across ±VS with its slider connected through a
300kΩ resistor to the gain adjust Pin 3 as shown in Figure 2.
If no external trim adjustment is desired, Pin 5 (OFFSET ADJ)
and Pin 3 (GAIN ADJ) may be left open.
Figure 2. Gain Adjustment Circuit (±0.2% FSR)
OFFSET ADJUSTMENTThe zero adjust circuit consists of a 100ppm/°C potentiometer
connected across ±VS with its slider connected through a
1.8MΩ resistor to Comparator Input Pin 5 for all ranges. As
shown in Figure 3, the tolerance of this fixed resistor is not
critical, and a carbon composition type is generally adequate.
Using a carbon composition resistor having a –1200ppm/°C
tempco contributes a worst-case offset tempco of 32LSB14 ×ppm/LSB14 × 1200ppm/°C = 2.3ppm/°C of FSR, if the
OFFSET ADJ potentiometer is set at either end of its adjust-
ment range. Since the maximum offset adjustment required is
typically no more than ±16LSB14, use of a carbon composition
offset summing resistor typically contributes no more thanppm/°C of FSR offset tempco.
Figure 3.Offset Adjustment Circuit (±0.3% FSR)
An alternate offset adjust circuit, which contributes negligible
offset tempco if metal film resistors (tempco <100ppm/°C) are
used, is shown in Figure 4.
Figure 4.Low Tempco Zero Adjustment Circuit
In either adjust circuit, the fixed resistor connected to Pin 5
should be located close to this pin to keep the pin connection
runs short. Comparator Input Pin 5 is quite sensitive to external
noise pickup and should be guarded by analog common.
TIMINGThe timing diagram is shown in Figure 5. Receipt of a CON-
VERT START signal sets the STATUS flag, indicating conver-
sion in progress. This, in turn, removes the inhibit applied to
the gated clock permitting it to run through 17 cycles. All the
SAR parallel bits, STATUS flip-flops and the gated clock in-
hibit signal are initialized on the trailing edge of the CONVERT
START signal. At time t0, B1 is reset and B2 – B16 are set un-
conditionally. At t1 the Bit 1 decision is made (keep) and Bit 2 is
reset unconditionally. This sequence continues until the Bit 16
(LSB) decision (keep) is made at t16. The STATUS flag is reset,
indicating that the conversion is complete and the parallel
output data is valid. Resetting the STATUS flag restores the
gated clock inhibit signal, forcing the clock output to the low
Logic “0” state. Note that the clock remains low until the next
conversion.
Corresponding parallel data bits become valid on the same
positive-going clock edge.
DIGITAL OUTPUT DATABoth parallel and serial data from TTL storage registers is in
negative true form (Logic “1” = 0V and Logic “0” = 2.4V).
Parallel data output coding is complementary binary for unipolar
ranges and complementary offset binary for bipolar ranges.
Parallel data becomes valid at least 20ns before the STATUS
flag returns to Logic “0,” permitting parallel data transfer to be
clocked on the “1” to “0” transition of the STATUS flag (see
Figure 6).
Figure 6.LSB Valid to Status Low
Serial data coding is complementary binary for unipolar input
ranges and complementary offset binary for bipolar input
ranges. Serial output is by bit (MSB first, LSB last) in NRZ
(non-return-to-zero) format. Serial and parallel data outputs
change state on positive-going clock edges. Serial data is guaran-
teed valid 120ns after the rising clock edges, permitting serial
data to be clocked directly into a receiving register on the
negative-going clock edges as shown in Figure 7. There are 17
negative-going clock edges in the complete 16-bit conversion
cycle. The first negative edge shifts an invalid bit into the regis-
ter, which is shifted out on the last negative-going clock edge.
All serial data bits will have been correctly transferred and be in
the receiving shift register locations shown at the completion of
the conversion period.
Figure 7.Clock High to Serial Out Valid
INPUT SCALINGThe AD1380 inputs should be scaled as close to the maximum
input signal range as possible in order to utilize the maximum
signal resolution of the A/D converter. Connect the input signal
as shown in Table I. See Figure 8 for circuit details.
Figure 8.AD1380 Input Scaling Circuit
Table I.AD1380 Input Scaling ConnectionsNOTE
Pin 5 is extremely sensitive to noise and should be guarded by analog common.
AD1380
Table II.Transition Values vs. Calibration CodesNOTE
For LSB value for range and resolution used, see Table III.
*Voltages given are the nominal value for transition to the code specified.
Table III.Input Voltage Range and LSB ValuesNOTES
***COB = Complementary Offset Binary.
***CTC = Complementary Twos Complement—achieved by using an inverter to complement the most significant bit to produce (MSB).
***CSB = Complementary Straight Binary.
CALIBRATION (14-Bit Resolution Examples)External ZERO ADJ and GAIN ADJ potentiometers, connected
as shown in Figures 2 and 3, are used for device calibration. To
prevent interaction of these two adjustments, Zero is always
adjusted first and then Gain. Zero is adjusted with the analog
input near the most negative end of the analog range (0 for
unipolar and –FS for bipolar input ranges). Gain is adjusted
with the analog input near the most positive end of the analog
range.
0 to +10V Range:Set analog input to +1 LSB14 = 0.00061V.
Adjust Zero for digital output = 11111111111110. Zero is
now calibrated. Set analog input to +FSR – 2LSB =
+9.99878V. Adjust Gain for 00000000000001 digital output
code; full scale (Gain) is now calibrated. Half-scale calibra-
tion check: set analog input to +5.00000V; digital output
code should be 01111111111111.
–10 V to +10 V Range:Set analog input to –9.99878V; adjust
zero for 1111111111110 digital output (complementary offset
binary) code. Set analog input to 9.99756V; adjust Gain for
00000000000001 digital output (complementary offset binary)
Figure 9.Analog and Power Connections for Unipolar 0V
to +10V Input Range
