AD1376KD ,Complete, High Speed 16-Bit A/D Converterapplications requiring moderate speed and high accuracy or
stability over commercial (0°C to +70°C ..
AD1376KD ,Complete, High Speed 16-Bit A/D ConverterANALOG
DEVICES
AD1377JD ,Complete, High Speed 16-Bit A/D ConverterAPPLICATIONS
The AD1376 and AD1377 are excellent for use in high resolu-
AD1376/AD1377
Compl ..
AD1377JD ,Complete, High Speed 16-Bit A/D ConverterFEATURES
Complete 16-Bit Converters with Reference
and Clock
t0.003% Maximum Nonlinearity
No Mi ..
AD1377KD ,Complete, High Speed 16-Bit A/D Convertersapplications resistors. They are packaged in a
compact 32-pin, ceramic seam sealed (hermetic) dual ..
AD1380JD ,Low Cost 16-Bit Sampling ADCSpecifications subject to change without notice.REV. B–2–AD1380ABSOLUTE MAXIMUM RATINGS There are t ..
AD818ARZ-REEL7 , Low Cost, Low Power Video Op Amp
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AD8190ACPZ , 2:1 HDMI/DVI Switch with Equalization
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AD8191ASTZ , 4:1 HDMI/DVI Switch with Equalization
AD8191ASTZ-RL , 4:1 HDMI/DVI Switch with Equalization
AD1376JD-AD1376KD-AD1377JD-AD1377KD
Complete, High Speed 16-Bit A/D Converter
ANALOG
DEVICES
Complete, High Speed
16-BitA/D Converters
h01378/M1377
FEATURES
Complete 16-Bit Converters with Reference
and Clock
t0.003% Maximum Nonlinearity
No Missing Codes to 14 Bits over Temperature
Fast Conversion
17 IM' to 16 Bit (AD1376)
10 us to 16 Bits (AD1377)
Short Cycle Capability
Adjustable Clock Rate
Parallel and Serial Outputs
Low Power: 645 mW Typical (AD1376)
585 mW Typical (AD1377)
Industry Standard Pin Out
PRODUCT DESCRIPTION
The AD1376 and AD1377 are high resolution, 16-bit analog-to-
digital converters with internal reference, clock and laser-
trimmed thin-film applications resistors. They are packaged in a
compact 32-pin, ceramic seam sealed (hermetic) dual-in-line
packages (DIP). Thin-film scaling resistors provide bipolar input
ranges of 12.5 V, t5 V, t10 V and unipolar input ranges of 0
to +5 V, 0 to +10 V, and 0 to +20 V.
Digital output data is provided in parallel and serial form with
corresponding clock and status outputs. All digital inputs and
outputs are TTL compatible.
APPLICATIONS
The AD1376 and AD1377 are excellent for use in high resolu-
tion applications requiring moderate speed and high accuracy or
stability over commercial (0°C to +70°C) temperature ranges
(for extended temperature ranges, the pin compatible AD1378
is recommended.) Typical applications include medical and ana-
lytic instrumentation, precision measurement for industrial
robotics, automatic test equipment (ATE), and multichannel
data acquisition systems, servo control systems, or anywhere
wide dynamic range is required. A proprietary monolithic DAC
and laser-trimmed thin-film resistors guarantee a maximum non-
linearity of t0.003% (1/2 LSBH.) The converters may be short
cycled to achieve faster conversion times-15 ws to 14-bits for
the AD1376, or 8 'IS to 14 bits for the AD1377.
PRODUCT HIGHLIGHTS
1. The AD1376 and AD1377 provides 16-bit resolution with a
maximum linearity error of t0.003% (1/2 LSBH) at +25°C.
2. AD1376 conversion time is 14 its (typical) short cycled to 14
bits, and 16 us to 16 bits.
3. AD1377 conversion time is 8 is (typical) short cycled to 14
bits, and 9 us to 16 bits.
4. Two binary codes are available on the digital output. They
are CSB (Complementary Straight Binary) for unipolar input
voltage ranges and COB (Complementary Offset Binary) for
bipolar input ranges. Complementary Twos Complement
(CTC) coding may be obtained by inverting Pin 1 (MSB).
5, The AD1376 and AD1377 include internal reference and
clock, with external clock rate adjust pin, and serial and par-
allel digital outputs.
FUNCTIONAL BLOCK DIAGRAM
(M58) BITS 1
SHORT CYCLE
CONVERT COMMAND
AD1376/AD1377
an " 16-3" SAR
tLSB FOR " BITS) BIT "
(L5! FOR " BITS) BIT "
BIT 15
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use; nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
REFERENCE +5V dc SUPPLV VL
GAIN ADJUST
+ tSV dc SUPPLY Vcc
COMPARATOR IN
BIPOLAR OFFSET
3.751(1) 3.75M) .
IG-BIT D/A CONVERTER
CLK RATE CTRL
ANALOG COMMON
- 15V dc SUPPLY Ves
CLOCK OUT
DIGITAL COMMON
COMPARATOR
STATUS
SERIAL OUT
One Technology Way, PO. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703 wa: 710/394-6577
Telex: 924491 Cable: -ANALOG NORWOODMASS
M137Ml01377-SPEiyFliyfrl01G (typical at T, = +25°c, Vs = :15, +5 ll unless otherwise noted)
Model AD137GJD/ADI377JD AD1376KD/AD1377KD Units
RESOLUTION 16 (max) * Bits
ANALOG INPUTS
Voltage Ranges
Bipolar :25, "c5, t10 * Volts
Unipolar 0 to +5, 0 to +10, 0 to -.-20 * Volts
Impedance (Direct Input)
0 to +5 V, :2.5 V 1.88 * kn
0 to + 10 v, :5.0 V 3.75 * kfl
0 to +20 V, tio V 7.50 A kfl
DIGITAL INPUTSl
Convert Command Positive Pulse 50 ns Wide (min) Trailing Edge Initiates Conversion
Logic Loading 1 * LS TTL Load
TRANSFER CHARACTERISTICS'
ACCURACY
Gain Error :0.053 (t0.2 max) * %
Offset Error
Unipolar :0.053 (t0.1 max) A % of FSR4
Bipolar :0.053 (t0.2 max) A % of FSR
Linearity Error (max) :0.006 t0.003 % of FSR
Inherent Quantization Error :1/2 * LSB
Differential Linearity Error :0.003 * % of FSR
POWER SUPPLY SENSITIVITY
:15 V dc (:0.75 V) 0.0015 * % of FSR/% AVs
+5 V dc (:0.25 V) 0.001 A % of FSR/% AVs
CONVERSION TIME5
12 Bits (AD1376) 11.5 (13 max) * us
14 Bits (AD1376) 13.5 (15 max) * ws
16 Bits (AD1376) 15.5 (17 max) * us
14 Bits (AD1377) 8.75 max * us
16 Bits (AD1377) 10 max * us
POWER SUPPLY REQUIREMENTS
Rated Voltage, Analog :15, :0.5 (max) * V dc
Rated Voltage, Digital +5, :0.25 (m,ax) A V dc
AD1376 Power Consumption 645 (850 max) * mW
+15 V Supply Drain +16 * mA
-15 V Supply Drain -21 * mA
+5 V Supply Drain +18 * mA
AD1377 Power Consumption 600 (800 max) * mW
+ 15 V Supply Drain +10 * mA
- 15 V Supply Drain -23 * mA
+5 V Supply Drain +18 * mA
WARM-UP TIME 1 minute * minutes
DRIFT"
Gain :15 (max) :5 (t 15 max) ppm/°C
Offset
Unipolar t2 (t4 max) t2 (t4 max) ppm of FSRf'C
Bipolar :10 (max) +3 (t 10 max) ppm of FSR/T
Linearity t2 (t3 max) t0.3 (e max) ppm of FSR/T
Guaranteed No Missing Code
Temperature Range
0 to 70 (13 Bits)
0 to 70 (14 Bits)
DIGITAL OUTPUT"
(A11 Codes Complementary)
Parallel & Serial
Output Codes7 F
Unipolar CSB *
Bipolar COB, CTCs *
Output Drive 5 * LSTTL Loads
Status Logic "I'' During Conversion
Status Output Drive 5 (max) * LSTTL Loads
Internal Clock9
Clock Output Drive 5 (max) * LSTTL Loads
Frequency 1040/ 1750 * kHz
-2- REV. B
h01378/Nll377
AD1376]D/ADI377JD AD1376KD/AD1377KD Units
TEMPERATURE RANGE -
Specification 0 to +70 * T
Operating -25 to -85 * “C
Storage -55 to + 125 A "C
1Logic "o'' r 0.8 V, max. Logic "l" = 2.0 V, min for inputs. For digital outputs Logic "O'' = --0.4 V max. Logic "l" - 2.4 V min.
'Tested on :10 V and 0 to ' 10 V ranges.
'Adjustable to zero,
'Full Scale Range.
'Guaranteed but not 100% production tested.
“Conversion time may be shortened with "Short Cycle" set for lower resolution.
'CSB-Complementary Straight Binary. COB-Complementary Offset Binary. CTC-Complementary Twos Complement.
TTC coding obtained by inverting MSB (Pin l).
"With Pin 23, clock rate controls tied to digital ground.
"Specifications same as AD1376JD/AD1377JD.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ........................... t18 V tt AD1376
Logic Supply Voltage ....................... +7 V E
Analog Inputs (Pins 24 and 25) ................ t25 V g
Analog Ground to Digital Ground .............. t0.3 V 2
Digital Inputs ................ -0.3 V to Vor, +0.3 V E VA
Junction Temperature ...................... + 175°C Cr SHORT CYCLED TO 12 BITS
Storage ......q..........r....'....'.... + 15°C ' SHORT CYCLED TO " BITS
Lead Temperature (10 seconds) ................ + 300°C ii SHORT CYCLED TO " m
g l/ZLSB12-BIT
Maximum Conversion. g trot
Temperature Linearity Time Package E y)ho.
. . * a .
Model Range Error (16 Bits) Option , non Ntts. b2LSBt3-BiT
AD1376JD 0°C to +70°C i0.006% l7 p.s DH-32E , o.ooa ‘:\\
AD1376KD 0°C to +70°c t0.003% 17 us DH-32E g TeLSB14-BlT
AD1377JD 0°C to +70°c t0.006% 10 us DH-32E tMm, 6 IO, " 20
AD1377KD 0°C to +70°C t0.003% 10 us DH-32E CONVERSION TIME -PB
'DH-SZE = Ceramic DIP. See Section 14 for package outline information.
Figure 2. AD1376 Nonlinearity vs. Conversion Time
- 0.053
AD1376! $33533 qthtMMi
ADI 377KB 2 3ppmf'C. + M
:2ppm/‘c, 203087.. (11251:
+0.0‘5 20.00333. trr25t
wmz t, :1Sme’C Mr, tC'"
' :2: af+0038 N /
' . l Cl NA s /
0.003 I:
(l' 0\V\\\ ILlrll ' ii ., 7),,M
E_m\ X“x\AXT\Y\X g jj-U" '' KALWLZA
' -9,006 A l \ 'a-on" : J
Fs-om "N, o r “K4
-o.o12 l
--IhM35 -lt.' I
4,0155 l
a .25 .10 0 140 +20 +30 +40 +50 +60 +70
TEMPERATURE - 'C TEMPERATURE - "C
Figure 1. Linearity Error vs. Temperature
Figure 3. Gain Drift Error vs. Temperature
MI 376/ADI377
DESCRIPTION OF OPERATION
On receipt of a CONVERT START command, the AD1376 or
AD1377 converts the voltage at its analog input into an equiva-
lent 16-bit binary number. This conversion is accomplished as
follows: the 16-bit successive-approximation register (SAR) has
its 16-bit outputs connected both to the device bit output pins
and to the corresponding bit inputs of the feedback DAC. The
analog input is successively compared to the feedback DAC out-
put, one bit at a time (MSB first, LSB last). The decision to
keep or reject each bit is then made at the completion of each
bit comparison period, depending on the state of the comparator
at that time.
GAIN ADJUSTMENT
The gain adjust circuit consists of a 100 ppm/°C potentiometer
connected across tVs with its slider connected through a
300 kfl resistor to the gain adjust Pin 29 as shown in Figure 4.
If no external trim adjustment is desired, Pin 27 (offset adj) and
Pin 29 (gain adj) may be left open.
300ktt
10m AD1376/
100ppml°c TO
1 001m ADI377
0.0tpF
-15V if
Figure 4, Gain Adjustment Circuit it0.2% FSR)
OFFSET ADJUSTMENT
The zero adjust circuit consists of a 100 pprnf'C potentiometer
connected across tVs with its slider connected through a
1.8 Mn resistor to Comparator Input Pin 27 for all ranges. As
shown in Figure 5, the tolerance of this fixed resistor is not
critical, and a carbon composition type is generally adequate.
Using a carbon composition resistor having a - 1200 ppm/°C
tempco contributes a worst-case offset tempco of 32 LSB” X
61 ppm/LSB,4 x 1200 ppml°C = 2.3 ppmf'C of FSR, if the
OFFSET ADJ potentiometer is set at either end of its adjust-
ment range. Since the maximum offset adjustment required is
typically no more than t16 LSB 14, use of a carbon composition
offset summing resistor typically contributes no more than
1 ppm/°C of FSR offset tempco.
AD1376I
AD1377
Figure 5. Offset Adjustment Circuit (10.3% FSR)
An alternate offset adjust circuit, which contributes negligible
offset tempco if metal film resistors (tempco <100 ppm/T) are
used, is shown in Figure 6.
180KB M.F. 180kn M.F.
AD1376/
OFFSET 11f
AD1377
ADJ 100m
Figure 6. Low Tempco Zero Adjustment Circuit
In either adjust circuit, the fixed resistor connected to Pin 27
should be located close to this pin to keep the pin connection
runs short. Comparator Input Pin 27 is quite sensitive to exter-
nal noise pick-up and should be guarded by analog common.
TIMING
The timing diagram is shown in Figure 7. Receipt of a CON-
V ERT START signal sets the STATUS flag, indicating conver-
sion in progress. This, in turn, removes the inhibit applied to
the gated clock, permitting it to run through 17 cycles. All the
SAR parallel bits, STATUS flip-flops, and the gated clock in-
hibit signal are initialized on the trailing edge of the CONVERT
START signal. At time to, B1 is reset and B, - B16 are set un-
conditionally. At t1 the Bit 1 decision is made (keep) and Bit 2
is reset unconditionally. This sequence continues until the Bit
16 (LSB) decision (keep) is made at TIS. The STATUS flag is
reset, indicating that the conversion is complete and that the
parallel output data is valid. Resetting the STATUS flag restores
the gated clock inhibit signal, forcing the clock output to the
low Logic "o'' state. Note that the clock remains low until the
next conversion.
Corresponding parallel data bits become valid on the same
positive-going clock edge.
, MAXIMUM THROUGHPUT TIME
CONVERT
START “ME m---]
INTERNAL
STATUS to t, i" t. t. ts ts h t. t. no m In tn “1 1.. 1..
M532: m. . . . . . . "m m
sltzj:
sttajj'
9115:"
EIY7:'
alts'“
an 10'"
51115 "T"
“Ti“gc; yyar, Wmmfilfilflu FY.
"T" "D'
t, 'i',iijiiiriio':,i','fli'/'l'hhvlll'21 Is so in Mm AND MUST REMAIN Low DURING
convert COMM AND v DN Is INI IATED av THE' 'TRAILING EDGE" or THE
2 M58 DECISIO
I CLOCK REMAINS Low Arm! LAST " DECISION
Figure 7. Timing Diagram (Binary Code 0110011101111010)
DIGITAL OUTPUT DATA
Both parallel and serial data from TTL storage registers is in
negative true form (Logic "l" = O V and Logic "O'' = 2.4 V).
Parallel data output coding is complem.entary binary for unipolar
ranges and complementary offset binary for bipolar ranges. Par-
allel data becomes valid at least 20 ns before the STATUS flag
returns to Logic "o'', permitting parallel data transfer to be
clocked on the "I'' to "O'' transition of the STATUS flag (see
Figure 8).
err 15
VALID l f
BUSY I l
(STATUS) J \
20ns MIN TO sans
Figure 8, LSB Valid to Status Low
M- REV. B
All1378/h01377
Serial data coding is complementary binary for unipolar input
ranges and complementary offset binary for bipolar input
ranges. Serial output is by bit (MSB first, LSB last) in NRZ
(nonreturn-to-zero) format. Serial and parallel data outputs
change state on positive-going clock edges. Serial data is guaran-
teed valid 120 ns after the rising clock edges, permitting serial
data to be clocked directly into a receiving register on the
negative-going clock edges as shown in F igure 9. There are 17
CLOCK -l"'-""-L._l'
SERIAL l I
'4 k- 30ns TO 120ns MAX
Figure 9. Clock High to Serial Out Valid
negative-going clock edges in the complete l6-bit conversion
cycle. The first negative edge shifts an invalid bit into the regis-
ter, which is shifted out on the last negative-going clock edge.
All serial data bits will have been correctly transferred and be in
the receiving shift register locations shown at the completion of
the conversion period.
Short Cycle Input: A Short Cycle Input, Pin 32, permits the
timing cycle shown in Figure 7 to be terminated after any num-
ber of desired bits has been converted, permitting somewhat
shorter conversion times in applications not requiring full l6-bit
resolution. When 10-bit resolution is desired, Pin 32 is con-
nected to Bit 11 output Pin ll. The conversion cycle then ter-
minates and the STATUS flag resets after the Bit 10 decision
(timing diagram of Figure 7). Short cycle connections and asso-
ciated 8-, 10-, 12-, 13-, 14-, and 15-bit conversion times are
summarized in Table I, for a 1.6 MHz clock (AD1377) or
933 kHz (AD1376).
INPUT SCALING
The ADC (ADC) inputs should be scaled as close to the maxi-
mum input signal range as possible in order to utilize the maxi-
mum signal resolution of the A/D converter. Connect the input
signal as shown in Table H. See Figure 10 for circuit details.
REV. B
Maximum Maximum i
Conversion Conversion Connect Short
Resolution Time-vs Time-ws Status Flag _ Cycle Pin 32 to
Bits I (% FSR) (AD1377) (AD1378) Reset i Pin:
16 0.0015 10 17.1 tus N/C (Open)
15 0.003 9.4 16.1 tls 16
14 0.006 8.7 15.0 tH 15
13 0.012 8.1 13.9 I13 14
12 0.024 7.5 12.9 :12 l 13
10 0.100 6.3 10.7 t”, 11
8 0.390 5.0 8.6 ts l 9
Table I. Short Cycle Connections
Input Connect Connect Connect
Signal Output Pin 26 Pin 24 Input
Line Code to Pin to Signal to
t10 V COB 27 Input 24
Signal
:5 V COB 27 Open 25
:25 V COB 27 Pin 27 25
0 V to +5 V CSB 22 Pin 27 25
0 V to +10 V CSB 22 Open 25
0 V to +20 V CSB 22 Input 24
Signal
Note: Pin 27 is extremely sensitive to noise and should b guarded by
analog common.
Table II. Input Scaling Connections
