AD1324KZ ,Ultrahigh Speed Pin Driver with Inhibit ModeCHARACTERISTICS See Notes 1, 3
Logic High Range - 1.6 +7.0 Volts
Logic Low Range -2.0 +6.6 . Volt ..
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AD1324KZ
Ultrahigh Speed Pin Driver with Inhibit Mode
ANALOG
DEVICES
Ultrahigh Speed Pin Driver
with Inhibit Mode
MI 324
FEATURES
200 MHz Driver Operation
Driver Inhibit Function
200 ps Edge Matching
Guaranteed Industry Specifications
50 n Output Impedance
2 Vlns Slew Rate
Variable Output Voltages for ECL, TTL and CMOS
High Speed Differential Inputs for Maximum Flexibility
Hermetically Sealed Small Gull Wing Package
APPLICATIONS
Automatic Test Equipment
Semiconductor Test Systems
Board Test Systems
Instrumentation & Characterization Equipment
PRODUCT DESCRIPTION
The AD1324 is a complete high speed pin driver designed for
use in digital or mixed signal test systems. By combining a high
speed monolithic process with a unique surface mount package,
this product attains superb electrical performance while preserv-
ing optimum packaging densities and long term reliability in an
ultrasmall l6-lead, hermetically sealed gull wing package.
Featuring unity gain programmable output levels of -2 V to
+7 V with output swing capability of less than 100 mV to 9 V,
the AD1324 is designed to stimulate ECL, TTL and CMOS
logic families. The 200 MHz (2.5 ns pulsewidth) data rate
capacity, and matched output impedance allows for real-time
stimulation of these digital logic families. To test I/O devices,
the pin driver can be switched into a high impedance state
(inhibit mode) electrically removing the driver from the path,
through the inhibit mode feature. The pin driver leakage cur-
rent in inhibit is typically 50 nA, and output charge transfer "
entering inhibit is typically less than 15 pC.
The AD1324 transition from HI/LO or to inhibit is controlled
through the data and inhibit inputs. The input circuitry is
implemented utilizing high speed differential inputs with a
common-mode range of 3 volts. This allows for direct interface
FUNCTIONAL BLOCK DIAGRAM
PACKAGE
AD1 324
to the precision of differential ECL timing or the simplicity of
stimulating the pin driver from a single ended TTL or CMOS
logic source. The analog logic HI/LO inputs are equally easy to
interface. T ypically requiring 15 WA of bias current, the
AD1324 can be directly coupled to the output of a digital-to-
analog converter.
The AD1324 is available in a l6-lead, hermetically sealed gull
wing package and is specified to operate over the ambient com-
mercial temperature range from 0°C to +70°C.
A01324-SPEiyFltym0hl
(All measurements made in free air at +25%. Output load 10 kn/ii pF with
+lls = +10 ll, -lls = -5.2 ll unless otherwise specified)
AD1324KZ
Parameter Min Typ Max Units Comments
DIFFERENTIAL INPUT
CHARAfTERISTICi;
D to D, INH to INH
Input Voltage, Any Input -3.0 +5.5 Volts r
Differential Input Range 0.4 ECL 3.0 Volts
Bias Current - 1350 +200 + 500 “A
REFERENCE INPUTS See Note 1
VHIGH Range (Vu) -2.5 +7.5 Volts
VLOW Range (VL) -2.5 +7.5 Volts
Bias Currents -40 t 15 40 WA
Bias Current Change 2 10 WA See Note 2
OUTPUT CHARACTERISTICS See Notes 1, 3
Logic High Range - 1.6 +7.0 Volts
Logic Low Range -2.0 +6.6 Volts
Amplitude [Vu-VL] 0.4 +9.0 Volts
Accuracy
Initial Offset -200 +200 mV
Gain Error -3.0 - 1.0 0.0 % of Vse,
Linearity Error See Note 4
-1.0 V to +5.6 V -(0.2% + 10) (0.2% + 10) % of VSE-r f mV VL
-1.0 V to +6.0 V -(0.2% + 10) (0.2% + 10) % of VSET + mV Vs,
-2.0 V to -1.0 V -(0.2% + 40) (0.2% + 40) % of VSET + mV VL, vH
+6.0 V to +7.0 V -(0.2% + 40) (0.2% + 40) % of Vsm + mV VH
+5.6 V to +7.0 V -(0.2% + 40) (0.2% + 40) % of VSET + mV Vt.
Output Voltage Drift 0.5 mWC
Current Drive
Static 30 mA
Dynamic 100 mA See Note 5
Current Limit 35 85 mA Output to GN D
Output Resistance 48.5 50.0 51.5 fl See Note 6
Leakage Current in Inhibit Mode
-1Vto +6 V -1 :0.25 +1 WA T, - 95°C i 5°C; See Note 7
-2 V to +7 V -10 - 10 " T, = 95°C t 5°C; See Note 7
DYNAMIC PERFORMANCE See Note 8
Driver Mode
Delay Time 0.9 1.2 1.5 ns See Note 9
Prop Delay TC 1.0 ps/°C
Delay Time Matching Edge-to-Edge 0 50 250 ps
Rise & Fall Times See Note 10
1 V Swing 0.4 0.6 0.8 ns Measurement 20%-80%
2 V Swing 1.0 1.2 1.4 ns Measurement 10%-90%
3 V Swing 1.4 1.7 2.0 ns Measurement 10%-90%
5 V Swing 2.3 2.6 2.9 ns Measurement 10%-90%
9 V Swing 5.5 6.5 ns Measurement 10%-90%
Toggle Rate 200 MHz ECL Output
Large Signal Slew Rate 1.5 V/ns
Minimum Pulsewidth, Vom- = 2 V 2.0 us See Figure ll
Overshoot & Preshoot
I V to 7 V -(3% Vo) -50 +(3%V0) +50 mV % of VOUT Swing; See Note 11
Settling Time
1V to 7 V, +(1% x Vo) 15 ns See Note 11
Delay Time vs. PW 100 ps See Note 12
DYNAMIC PERFORMANCE
Inhibit Mode Delay Time See Note 13
Drive-to-Inhibit 1.0 1.3 1.6 ns
Inhibit-to-Drive 1.4 1.9 2.4 ns
Delay Time Matching _
Edge-to-Edge 0 100 400 ps 1 V Swing
Overshoot & Preshoot 300 mV
Output Capacitance 3.5 5 pF
Output Charge Going
into Inhibit Mode 5 pC
A01 324
AD1324KZ '
Parameter Min Typ Max Units Comments
POWER SUPPLIES
-Vs to +Vs Range 15.2 15.6 Volts
Supply Range See Note 24
Positive Supply + 8.0 +10.0 + l 1.0 Volts
Negative Supply - 7.2 A 5.2 - 4.2 Volts
Current
Positive Supply 42 82 100 mA
N egative Supply _ 100 - 82 - 42 mA
PSRR 5 20 mVN +VS, -Vs = :2.5%
1The output voltage range is specified for -2 V to +7 V for typical power supply values of -5.2 V and + 10.0 V but can be offset for different values of V01. I.
such as -l V to +8 V or -4 V to +5 V as long as the required headroom of 3 V is maintained between both VH and -v,,, and VL and -V,
2VH and VL, inputs have internal buffers which reduce the input bias current requirements. These buffers also reduce the amount of bias current change when
the output switches logic levels.
'v,, must remain at least 400 mV more positive than VL for specified performance. v,, may be as much as 5 V more negative than v,., with degraded
performance.
"Linearity testing is performed in l V increments over the following ranges:
VL Linearity: vs, fixed at +7.0 v, VL - -2.0 V to +6.6 V;
VH Linearity: VL fixed at -2.0 V, VH = -1.6 V to +7.0 V.
Linearity error includes the error due to interaction for a minimum amplitude of 400 mV. Interaction error testing is performed with VH - -0.6 V, VI. =
-l.0 V and with V" = +6.0 V, VL = +5.6 V.
'Transient output current can easily exceed the AD1324's steady-state current limit when driving capacitive loads. The transient output current capability can
be increased by connecting 0.039 " capacitors between Pin 5 and +V,, and between Pin 6 and -Vs. This will prevent the driver from current limiting by
providing the "edge" current necessary when driving capacitive loads. These capacitors will not affect the driver's dc current limit.
6Driver output impedance is 50 n for a 3 V p-p signal into a 50 n load.
7While in inhibit mode, the output voltage must not go more than 6 V above VHIGH or 6 V below VLOW.
8The driver output has 2 ns length of 50 ll coaxial cable attached with a 10 kQ/6 pF probe, 1 GHz bandwidth or equivalent at the far end.
"Delay times are measured from the crossing of differential ECL levels at the input to the 50% point of an 800 mV driver output with VH and VL set at
t400 mV, respectively. _
"Rise and fall time performance guaranteed over the output range of +V,,, _4 V to -Vs +4.2 V except for 9 V swing, which is measured over the output range
of +VS _3 V to -VS , 3.2 V.
'tue to uncontrolled inducpmces in the test socket, overshoot, preshoot and settling time cannot be 100% tested. These characteristics are guaranteed by
characterization data .
"Delay matching vs. PW is defined as the amount of change in propagation delay, with respect to the leading edge, due to change in pulsewidth of the input
signal. The specification applies over the pulsewidth range of 2.5 ns to 100 ns.
"Inhibit mode delay times are measured from the crossing of differential (ECL) INH inputs to a 200 mV crossing at the pin driver's output connected to
2 ns length of 50 n coaxial cable. The cable is terminated to ground through a 50 ft resistor. The measurement is made at the 50 it resistor to GND with
a 10 kfl/6 pF scope probe.
"A supply range of 15.2 V must be maintained to guarantee a 9 V output swing.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS' NOTES
. V " . . n .
Power Supply Voltage Stresses above those listed under Absolute Maximyrn Ratings may cause
permanent damage to the device. This 15 a stress rating only, and functional
+Vs to GND """"""""""""" + 13 V operation of the device at these or any other conditions above those indicated
--Vs to GND ............-..-.. -8.2 V in the operational sections of this specifications is not implied. Exposure to
Difference from +VS to -Vs ................. 16 V absolute maximum rating conditions for extended periods may affect device
Inputs reliability.
. - tTo ensure lead coplanarity (:0.002 inches) and solderability handling with
Difference from D to D "'_', ................. 4.75 V bare hands should be avoided and the device should be stored in an
Difference {HENH t0 INH F............... 4,75 V environment at 24°C, 15°C (75°F, : 1ty'F) with relative humidity not to exceed
D, D, INH, INH ......... +Vs - 13 V, -Vs + 11.5 V 65%.
VHtoVL ......................... -IV,+9V
VH, VL .............. -eVs - 13.2 V, -Vs + 13.2 V
Driver Output ORDERING GUIDE
Voltage ............... +Vs - 13.2 V, -Vs + 13.2 V
Short Circuit to GND ................... Indefinite M d l {emperature D . ti gaff:
Operating Temperature Range ............. 0°C to -70oC 0 e ange escnp ion p tO
Storage Temperature Range ........... -65T to + 125°C AD1324KZ 0 to +70°C 16-Lead Z-16A
Lead Temperature Range (Soldering 20 sec)t ....... +300°C Gull Wing
*For outline information see Package Information section.
A01324
AD1324
TOP VIEW
(Not To Scale)
UVGUI§UMJ
CONNECTION DIAGRAMS
Dimensions shown in inches and (mm).
PIN DESCRIPTION
SUGGESTED LANDING PADS LOCATION
le 21 '
til I: 0.050 (1.27)
l:| AD1 324 E
E I: 0.025 (0.63)
l-osx, (13.71) -rl I
0.710 (18.03)
Pin No. Symbol Function
1 GND Circuit Ground
2 N/C No Connection
3 VOUT Driver Output
4 N/C No Connection
5 ch, Positive Decouple
6 CI, Negative Decouple
7 VL Voltage Logic Low
8 GND Internal Ground'
9 LID Lid Connection'
10 VH Voltage Logic High
11 B Driver Input
12 D Driver Input
13 W Inhibit Input
14 INH Inhibit Input
15 -Vs Negative Supply
16 +Vs Positive Supply
'It is recommended to connect Pins 8 and 9 to Circuit Ground.
Definition of Terms-MUN
OFFSET ERROR
The offset error for logic high is determined by holding the out-
put of the driver at logic high, and applying zero volts to the
logic high reference input. The driver output value represents
the offset "high" error. The same approach is used to identify
offset "low" error.
VHIGH OFFSET - Vow
where:
VH = 0V
9 = HIGH
D = LOW
INH = LOW
INH = HIGH
GAIN ERROR
Defined as the ratio of the driver's output voltage to its logic set
level voltage and is expressed in terms of percent of set level.
The gain error is typically seen as 1.0% and is always in the
negative direction with respect to the logic set level.
Voz'r - V ff - i_rrsrris_t OFFSET
VIIIUIIGAIA' P/o) = --rr,, - X 100
where:
VH = 5.0 V+VHIGH OFFSET
B = HIGH
D = LOW
INH = LOW
INH = HIGH
LINEARITY ERROR
The deviation of the transfer function from a reference line. For
the AD1324, the linearity error is calculated by subtracting the
worst case gain error from the best case gain error (for the speci-
fied range) and dividing the result by two. This method guaran-
tees that the maximum linearity error for any set level within
the specified range will be within the specified limits.
I , , y '
. a ' HIGH GAIN [max I - 1 HIGH GAIN WW
"HIGH LINEARI'IT i/ol = —T— x 100
DELAY TIME
The amount of time it takes the input signal to propagate
through the driver and be converted to the desired logic levels.
The measurement technique is defined in the notes and is
shown in Figure 2.
EDGE-TO-EDGE MATCHING
Edge-to-edge matching is the difference, in time, between the
delay time of the rising edge and the falling edge.
MINIMUM PULSEWIDTH
Defined as the smallest pulse applied to the input of the driver
which can maintain an output signal amplitude of 2 V. The
minimum pulsewidth is measured at the 50% point of the
waveform.
OVERSHOOT AND PRESHOOT
The amount by which the driver's output voltage exceeds the
desired set voltage. Preshoot is similar to overshoot but is the
amount by which the driver's output goes above or below the
initial voltage when driving to the new set level (or inhibit
mode). See Figure 3.
IDEAL TRANSFER CURVE
OFFSET & GAIN ERROR REMOVED
6.5V - --------- GAIN /OF-'FSET ERROR REMOVED
CURVATURE = ERROR
LINEARITY UNCoMPENSATED OUTPUT
OFFSET
ERROR 6.
(NOT TO SCALE)
v vs, m = CV)
WHERE vOUT = Vser , |OFFSET annonl - GAIN ERROR t LINEARITY ERROR
Figure 1. Definition of Terms
D j< jt
Vor; = +400mV
V OL-- 400mv
vor, = +1V
v L---IV
12 4 by P4
INHIBIT MODE DELAY TIME
Figure 2. Timing Diagram for Driver and Inhibit
Propagation Delay
+394, (Vow) +50mV"
_------------ - - tl% (VOUT)
OVERSH0OT FINAL VALUE /ft
ERROR v v
BAND - V _ - - - -
3% (vOUT ) -50mV*
+37. (vow) '50mV*
_ _ _ - ________ +1%(VOUT)
PHESHOOT
ERROR INITIAL VALUE
BAND 1 _------
_ - - :3} IvoerL-sfmr - - -1%(Vour)
--- 15ns ---F
- 500ns >
‘LIMITS ARE ,300mV FOR INHIBIT MODE OVERSHOOT AND PRESHOOT
Figure 3. Definition of Waveform Aberrations
