AD1139K ,High Accuracy 18-Bit Digital-to-Analog ConverterGENERAL DESCRIPTION
The AD1139 is the first DAC offering 18-bit resolution (1 part
in 262,144) ..
AD1170 ,High Resolution, Programmable Integrating A/D ConverterMI IN --$fEtlFltli'rMiS (typical C4 +25°C, Its = +15ll, ll, = +5ll unluss otherwise specified,)
..
AD12250A , 24 bit, 96 kHz Stereo A/D Converter
AD12250A-SG , 24 bit, 96 kHz Stereo A/D Converter
AD1315KZ ,High Speed Active Load with Inhibit Modespecifications (48 mA) typically associated with lineBy combining a high speed monolithic process w ..
AD1324KZ ,Ultrahigh Speed Pin Driver with Inhibit ModeCHARACTERISTICS See Notes 1, 3
Logic High Range - 1.6 +7.0 Volts
Logic Low Range -2.0 +6.6 . Volt ..
AD8184ARZ-REEL7 , 700 MHz, 5 mA 4-to-1 Video Multiplexer
AD8185ARU ,380 MHz, 25 mA, Triple 2:1 MultiplexersSPECIFICATIONS (T = 258C, V = 65 V, R = 1 kV unless otherwise noted)A S LParameter Condition Min Ty ..
AD8185ARUZ , 380 MHz, 25 mA, Triple 2:1 Multiplexers
AD8186ARU ,450 MHz, Single Supply, Triple 2:1 Multiplexer (G= +1)SPECIFICATIONS V = 2.5 V, R = 150 to 2.5 V; unless otherwise noted.)REF L AD8186/AD8187Parameter ..
AD8186ARU-REEL , 480 MHz Single-Supply (5 V) Triple 2:1 Multiplexers
AD8186ARU-REEL , 480 MHz Single-Supply (5 V) Triple 2:1 Multiplexers
AD1139K
High Accuracy 18-Bit Digital-to-Analog Converter
ANALOG
DEVICES
High Accuracy, 18-Bit
DigitaI-to-Analog Converter
as Q: 'o 1
megiy' [ED311819 t
FEATURES
18-Bit Resolution
Low Nonlinearity
Differential: :1/2LSB max
Integral: :1/2LSB max
High Stability
Differential TC: , Tppmf'C max
Integral TC: =1/2ppml°c max
Gain TC (with Reference): t4ppmf'C max
Fast Settling
Full $cale: 40p.s to :0.00019%
LSB." 6.1.3 to :0.00019%
Small Hermetic 32-Lead Triple DIP Package
Low Cost
APPLICATIONS
Automatic Test Equipment
Scientific Instrumentation
Beam Positioners
Digital Audio
GENERAL DESCRIPTION
The AD1139 is the first DAC offering 18-bit resolution (1 part
in 262,144) and true l8-bit accuracy in a component size hybrid
package. A proprietary bit switching technique provides high
accuracy, speed and stability without compromising small size
or low cost.
The AD1139 is a complete DAC with precision internal reference,
latched data inputs and a quality output voltage amplifier. The
analog output voltage ranges are pin programmable to + 5V,
+ 10V, t 5V and t 10V. Current output is also provided for
use with external amplifiers. The internal precision - 10V refer-
ence has a low t 3ppm/°C maximum temperature coefficient
and is available for ratiometric applications.
The AD1139K is a true 18-bit accurate DAC with ct: 1/2LSB
maximum differential and integral nonlinearity. The differential
and integral nonlinearity temperature stability is guaranteed at
t1pprnfC maximum and t l/2ppm/°C maximum, respectively.
The AD1139 settles to within t 1/2LSB at 18 bits (t0.00019%)
in 40p.s for a full-scale step (10V). The glitch energy is a low
400mV M 500ns for a major carry, and wideband output noise is
only ISuV.
The ADI 139 operates from i 15V dc and + 5V dc power supplies.
Digital inputs are 5V CMOS compatible with binary input
coding for unipolar output ranges and offset binary coding for
bipolar ranges.
Information furnished by Analog Devices is believed to be accurate
and reliable. However, no responsibility is assumed by Analog Devices
for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implica-
tion or otherwise under any patent or patent rights of Analog Devices.
PRODUCT HIGHLIGHTS
1. Eighteen-bit resolution with t 1/2LSB maximum differential
and integral nonlinearity in a hermetic M-lead triple DIP
package.
2. Complete DAC with internal reference, stable low-noise
output amplifier, latched DAC inputs, reference output and
internal application resistors for programmable output voltage
ranges.
3. Temperature compensated internal precision reference with
10.1% maximum initial accuracy and f.: 3ppm/°C maximum
tempco.
4. Four pin programmable output voltage ranges (+ 5V, + 10V,
t 5V, t 10V) and current output available (- lmA,
t 0. SmA).
5. The 18-bit parallel input latch assists in microprocessor
interface.
6. Accurate measurements of the DAC's output are unusually
simple since the AD1139 does not suffer from code dependent
ground current errors.
7. True analog output remote sense capability.
One Technology Way; P. O. Box 9106; Norwood, MA 02062-9106
Tel: 617/329-4700 TWX: 710/394-6577
West Coast Atlantic
714/641-9391 215/643-7790
Central
214/231-5094
ll"'"'"' itttitaltii) +mltttd ratMstqxEtsmlasstrthertristsspaeiiiai)
AD1139] AD1139K
ttl,,,, 18 Bits .
ACCURACY
Differential Nonlinearity ' ILSB max , 1I2LSB max
(-- s0.0003886max) (= t0.00019% max)
Integral Nonlinearity s ILSB max t 1/2LSB mu
(= t0.00038%max) (= :0.00019%max)
Monotonicity (18 Bits) Guaranteed '
Initial Ermn'
Unipolu Gain Error t 0.01% _
Bipolar Gain Error 2 0.02% .
Offset Error t 0.01% .
BipolaroffsetError 20.01% .
STABILITY (ppm FSR’PC)
Differential Noniinearirys t 1 max 2 0.5 Iyp, , 1 max
Integral Nontinearitr3 t 0.5 mu .
GainOncluding VREF) t 4m .
Offset
Unipolar Mode 1 1 max *
Bipolar Mode t 1 max .
STABILITY (Long Term, ppm FSR‘IIOOO hour)
Differential Nonlinearity‘ ' 0. 5 .
Gain (including Vup) t 15 A
Offset t l .
Bipolar Offset t 2 .
Rcfmno: Output Voltage t 15 .
WARMUP TIME (MINIMUM) 15 minutes .
REFERENCE VOLTAGE (V m)
otttputvoltage(Ca) SmAmu) -10v(t0.1%max) .
Noise (RV = 0. 1- 1 0Ha) 20wV pk-pk 1thsV pk-pk
Noise (RV = lOOkHz) SOuV rms .
Tempco 3ppm/“Cmax A
DYNAMIC PERFORMANCE
Settling Time to 1/2LSB(@ 18 Bits)'
Voltage
Unipolar(10v Step) 40ps .
Bipolar (20V Step) 60ws .
Unipolar (LSB Step) 6ps .
Bipolar (LSB Step) 8ws .
Slew Rate 2hhss .
Currents
Full-Sale Step lows .
LSB Step 6ws .
Glitch Energy (MaiorCarry
a 20MHz Bandwidth O-ICHOV Range) 400mV (500ns Duration) .
DIGITAL INPUTS (W CMOS Compatible)
vIL sosv .
v... >3.W .
Unipolar Code Binary (BIN) .
Bipolar Code Offset Binary (OBN) .
ANALOG OUTPUT
Current' -imA, t 0.5m .
Voltage (Pin Ptxsgmmmable) + 5V, + 10V, t 5V, ' 10V .
Noise (Includes Vm)
BW = 0.1-10Hz(uV pk-pk) 2 M FSR 1 x FSR
BW = 100kHz(Unipolar) ISwV mas .
BW - 100kH2 (Bipolar) 4SuV rms *
VOLTAGE COMPLIANCE t IOmV .
Source Resistance
Unipolar 3.3m .
Bipolar 2.85m *
Source Capacitance lOpF .
POWER SUPPLY REQUIREMENTS
+ " dc ( ' 5%) 1009A .
:15Vdc(:5%) +25mA,-30mA .
POWER SUPPLY REI ECTION
( 2 15V dc)
Gain , 2.5ppmM .
Offset :0.3ppml% .
Refemnce Output t 2.5ppmm .
( + SV dc)
Differential Nontioearity ' o. lSpme/o '
TEMPERATURE RANGE
Opening (Rated Performance) o to + 70'C .
Slang: . - 40'Cto + 85''C
(1-9) $325 $450
(100+) $195 $295
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
SEATING PLANE
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0.19214”)
0.1mm"
0.0091013}
cm: (0.301
l nu 22.45)
um [2:21)
CAUTION: OBSERVE PROPER PLUG-IN POLARITV TO
PREVENT DAMAGE TO CONVERTER
PIN DESIGNATIONS
PIN DESCRIPTION Pm DESCRIPTION
1 SIGNAL GND 32 GAIN TRIM
2 BIPOLAR OFFSET 31 REF OUT
3 Iom- 30 - tSV
4 AMP IN 29 + 1 5V
5 20V SPAN 28 + w
6 10V SPAN " P_O_WER GND
7 AMP OUT 26 WR
tt 0317 (M83) 25 D30 (L83)
9 D816 24 DBI
" 0815 23 DB2
1 1 0814 22 DB3
" 0813 21 DB4
" D812 20 DBS
" DBI 1 " DB6
" 0810 1 8 DB7
" DBS " DB8
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tNVERTER
10m (x m) e GAIN mm
OFFSET Q REF OUT
AMPIN .
0 AMP OUT
ssamu. GND 1 OUTPUT
AMPLIFIER -t51f
loo, ' tout Aoms G H“
mm P Q +sv
20V SPAN ' I a
10V SPAN 6 WER GND
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26 'TI
AD1139 Functional Block Diagram
ANALOG OUTPUT RANGE
The AD1139 is pin programmable to provide a variety of analog
outputs, either current or voltage. A unipolar output current of
0 to - lmA is available at Pin 3 and can be offset by 0.5mA
(connect Pin 2 to Pin 3) for a biolar output of $0.5m. Output
voltage ranges (+ SV, + 10V, t5V and , 10V) are available at
Pin 7 by connecting the current output (Pin 3) to the amplifier
input (Pin 4) and the appropriate internal feedback resistors to
the amplifier output (Pin 7) as shown in Figure 1.
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3.0TUt
o ISV o-- v
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“mu . $%
tvx-uv
(rgggg
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onouuo "ir' : muaunm
was man lull} INPUT
DB" 0 y", Din
FIW OPERATION
.AtLettNEtTPetCt2MtEt_AttErN"AMEASSHtWm
“MAID", - IWOFEMTDN.
Figure 1. Output Voltage and Trim Configuration
OFFSET & GAIN CALIBRATION
Initial offset and gain errors can be adjusted to zero by poten-
tiometers as shown in Figure l. The offset adjust range is plus
0.03% to minus 0.02% of full scale range (wiper of potentiometer
to REF OUT equals plus 0.03%). The gain adjust range is plus
0.06% to minus 0.08% of full scale range (wiper to REF OUT
equals plus 0.06%). Measurement instruments used should be
capable of resolving lp.V at plus ful1sca1e for the chosen output
range and within lpV of zero.
Procedure:
UNIPOLAR MODE
1. Apply a digital input of all "Os."
2. Adjust the offset potentiometer until a 0.000000V output is
obtained.
. Apply a digital input of all “Is.”
. Adjust the gain potentiometer until plus full-scale output is
obtained (see Table I for exact value).
BIPOLAR MODE
1. Apply a digital input of 100 ..... OOO,
2. Adjust the offset potentiometer until a 0.000000V output is
obtained.
. Apply a digital input of all "Is."
. Adjust the gain potentiometer until plus full-scale output is
obtained (see Table I for exact value).
CodeOOO....00 Codei11...11
Unipolar + sv o.oooooov + 4.999981V
+ 10V o.oooooov + 9.999962V
Codeloo....00 Codelll....ll Codeooo....00
Bipolar t sv o.oooooov + 4.999962V - s.oooooov
t 10v o.oooooov + 9.999924v - 10.000000V
Table I. Full-Scale and Offset Calibration Voltages
Symbol Parameter Requirement
tos Data Setup Time 160ns min
to” Data Hold Time 120ns min
twn Write Pulse Width 200nsmin
Table II. Timing Requirements
TIMING DIAGRAM & LATCH CONTROL
Timing requirements for the AD1139 are shown in Table II.
The timing diagram is shown in Figure 2. The WRite line controls
an 18-bit wide data input latch. This latch is transparent when
the WRite line is LOW, allowing all bits to be accessed directly.
When the WRite line is activated HIGH, the data present at the
inputs is held in the latch and the appropriate analog voltage is
seen at the output.
X DATAVALID x
cc----, ttr, r--.
-i._._y'f""""-"'-
=rt":,,--=Q
Figure 2. AD1139 Timing Diagram
GROUNDING & GUARDING
The current from measurement ground (Pin I) is small and
independent of the digital input code to the DAC. This greatly
simplifies making error free analog measurements. Connect this
high quality ground to the system's or app1ication's high quality
ground. Connect the DAC's power ground (Pin 27) to the system
return, also connect the system's high quality ground to the
system return. It is most important that the measurement ground
(Pin J) and power ground (Pin 27) be connected externally for
War circuit operation.
The current output pin (low, Pin 3) is sensitive to external
noise sources, such as digital input lines. This pin and any
components connected to this pin should be surrounded by a
grounded guard as shown in Figure 3.
EXTENAL AMPLIFIER
(UMPCLAR HANG!)
Figure 3. Guarding Recommendations
REMOTE SENSE APPLICATION
The AD1139's remote sense capability allows driving heavy
loads or long cables without the usual, accompanying gain errors.
By sensing at the load, as described in Figure 4, the load current
will pass through the amplifier's output and the power ground,
but not through the sense lines. The potential gain errors that
would be induced by this load current are therefore minimized.
The load should not exceed , mm or 2 nanofarads to insure
proper operation of the AD1139's internal output amplifier.
Ito” Qur'CaIu
Figure 4. Remote Sensing
RATIOMETRIC DAC TESTING APPLICATION
The AD1139's highly stable reference output can be conveniently
used in the testing of other high resolution DACs. Figure 5
describes how the REF OUT (Pin 31) is used as the external
reference input to a device-under-test. The gain of the device-
under-test will now accurately track the AD1139's gain and
eliminate reference contribution to gain error.
When used as a reference DAC to test the integral and differential
linearity of 14- and 16-bit DACs, the AD1139 provides a meas-
urement capability with just 1/16LSB of uncertainty at 14 bits.
Gain and offset errors of the device-under-test (D.U.T.) may be
accounted for in software. Once zeroed, the integral linearity
error can be measured as the difference between the reference
DAC (AD1139) and the D.U.T. as seen at the digital voltmeter.
The differential linearity error is then determined by incrementing
or decrementing the D.U.T. digital input by lLSB, and comparing
the new output at the DVM with the previous output. The
difference between these two measurements should be exactly
one ideal LSB. The amount of disagreement from one ideal
LSB is the differential linearity error.
NTERFACE
CONTROL
Figure 5. Ratiometric DAC Testing
IBM* PC INTERFACE
Figure 6 illustrates a typical IBM personal computer interface
which uses three 8-bit external latches and two decoder chips.
The three HCI' 374 latches are connected to the data bus (D0
through D7). The HOT 138 decoder chip decodes the address
bus and enables each latch, including the AD1139's internal
DAC latch, to see the appropriate digital word. The HCT 688
chip and the HCT138 decoder define the I/O address space
where the four latches will reside. In the Figure 6 example, they
reside in the address space as shown in Table III.
110 Address Selected Latch Data Bits
380H Low Byte DBO-DB7
381H Mid Byte DB8-DB15
382H High Byte DB16, DB17
383H AD1139 Latch DBO-DB17
Table III. IBM tn terface Address Locations
*IRM is a trademuk of International Business Machines Corp.
a nu...
CONNECT TO THE
PC'S + 6V SUPPLY'
BUS PIN # a I
CONNECT TO
THE A011 39's
+ SV SUPPLY' + 51t
+15V-15V +5V
HCT374 _
AD1139
HCT374
HCT374
D7 (A2)
D6 (A3)
DS (A4)
D4 (A5)
D3 (A6)
D2 (A7)
DI (AB)
on (A9)
iWt (amio DJE___J
A0 tAsn-l-. oe-----
At o"')-,-- Fa-----
: HCT 12
7 138 11
s tl,'-
+5V o- 't
-"c.1,
A3 (Azs)_2i "
A4 (A27) "
A6 (A26)__s_‘ '
A6 ous)--''-) H T ‘5
A7 tAw.-'.'... C 688
A8 (A23) " 9
A9 lA22) "
A10 (A2t)---
AEN ov,,-.-'.)
'THE PC'S - SV de LOGIC SUPPLIES SHOULD BE KEPT SEPARATE
FROM THEADI139 +5V chUPPLY, TO KEEP LOGIC
INDUCED NOISE TO A MINIMUM.
Figure 6. AD1139 to IBM PC Compatible Interface
LONG-TERM STABILITY VS. TEMPERATURE
Adjusting the linearity of any DAC after it is installed in the
application is often difficult or impossible. It is preferable to
maintain some specified accuracy over the useful working life of
the product (commonly 5 to 10 years). Stable linearity performance
over time can, therefore, be a very important parameter for the
Accelerated testing to determine the expected linearity stability
over time can be accomplished by two different methods. Linearity
is first measured at + LPC. The DAC is then operated at a
fixed elevated temperature for an extended period of time. The
DAC is then retested at + 25°C, and the change in linearity
error vs. time is calculated. The ARRHENIUS EQUATION
(used in reliability calculations) can be used to determine what
the acceleration factor is from + 25°C to the elevated test tem-
perature. Knowing the acceleration factor and the linearity error
vs. time at the elevated temperature, one could calculate the
expected long-term stability of linearity at nominal
temperatures.
A second test method determines how long it will take for the
linearity to shift by a specific error band (we chose t 2ppm for
our example) at any specified temperature. The first step is to
measure the linearity at a moderately elevated temperature (e.g.,
+ 85°C) and then monitor how long it takes at this temperature
to reach the error band limit. The second step is to perform the
same test at a much higher elevated temperature (e.g., + 125°C).
The two resulting time vs. temperature points are then plotted
on semilog paper. A line drawn through the two points allows
extrapolation to the length of time expected to reach the error
band (t prm) at other temperatures, including + 25°C.
