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9639
N-CHANNEL 150V
Figure 1. Logic DiagramSERIAL ACCESS SPI BUS 4K (512 x 8) EEPROM
NOT FOR NEW DESIGN1 MILLION ERASE/WRITE CYCLES
40 YEARS DATA RETENTION
SINGLE 3V to 5.5V SUPPLY VOLTAGE
SPI BUS COMPATIBLE SERIAL INTERFACE
1 MHz CLOCK RATE MAX
BLOCK WRITE PROTECTION
STATUS REGISTER
16 BYTE PAGE MODE
WRITE PROTECT
SELF-TIMED PROGRAMMING CYCLE
E.S.D.PROTECTION GREATER than 4000V
The ST95P04 will be replaced shortly by the
updated version ST95040
DESCRIPTIONThe ST95P04 is a 4K bit Electrically Erasable
Programmable Memory (EEPROM) fabricated with
SGS-THOMSON’s High Endurance Single Polysili-
con CMOS technology. The 4K bit memory is or-
ganised as 32 pages of 16 bytes. The memory is
accessed by a simple SPI bus compatible serial
interface. The bus signals are a serial clock input
(C), a serial data input (D) and a serial data output
(Q). The device connected to the bus is selected
when the chip select input (S) goes low. Commu-
nications with the chip can be interrupted with a
hold input (HOLD). The write operation is disabled
by a write protect input (W).
Table 1. Signal NamesJune 1996 1/16
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and
other relevant quality documents. MIL-STD-883C, 3015.7 (100pF, 1500Ω) EIAJ IC-121 (Condition C) (200pF, 0Ω)
Table 2. Absolute Maximum Ratings (1)
SIGNALS DESCRIPTION
Serial Output (Q). The output pin is used to trans-fer data serially out of the ST95P04. Data is shifted
out on the falling edge of the serial clock.
Serial Input (D). The input pin is used to transferdata serially into the device. It receives instructions,
addresses, and data to be written. Input is latched
on the rising edge of the serial clock.
Serial Clock (C). The serial clock provides thetiming of the serial interface. Instructions, ad-
dresses, or data present at the input pin are latched
on the rising edge of the clock input, while data on
the Q pin changes after the falling edge of the clock
input.
Chip Select (S). This input is used to select theST95P04. The chip is selected by a high to low
transition on the S pin when C is at ’0’ state. At any
time, the chip is deselected by a low to high transi-
tion on the S pin when C is at ’0’ state. As soon as
the chip is deselected, the Q pin is at high imped-
ance state. This pin allows multiple ST95P04 to
share the same SPI bus. After power up, the chip
is at the deselect state. Transitions of S are ignored
when C is at ’1’ state.
Figure 2A. DIP Pin Connections
Figure 2B. SO Pin Connections
ST95P04
Figure 3. Block Diagram
ST95P04
Figure 4. AC Testing Input Output WaveformsInput Rise and Fall Times ≤ 50ns
Input Pulse Voltages 0.2VCC to 0.8VCC
Input and Output Timing
Reference Voltages 0.3VCC to 0.7VCC
AC MEASUREMENT CONDITIONSNote that Output Hi-Z is defined as the point where data
is no longer driven.
Note: 1. Sampled only, not 100% tested.
Table 3. Input Parameters (1) (TA = 25 °C, f = 1 MHz )
Table 4. DC Characteristics(TA = 0 to 70°C or –40 to 85°C; VCC = 3V to 5.5V)
ST95P04
Note:1. Not enough characterisation data were available on this parameter at the time of issue this Data Sheet. The typical value is well
below 5ms, the maximum value will be reviewed and lowered when sufficient data is available.
Table 5. AC Characteristics(TA = 0 to 70°C or –40 to 85°C; VCC = 3V to 5.5V)
ST95P04
Figure 5. Output Timing
Figure 6. Serial Input Timing
ST95P04
Figure 7. Hold Timing
Write Protect (W). This pin is for hardware writeprotect. When W is low, non-volatile writes to the
ST95P04 are disabled but any other operation
stays enabled. When W is high, all operations
including non-volatile writes are available. W going
low at any time before the last bit D0 of the data
stream will reset the write enable latch and prevent
programming. No action on W or on the write
enable latch can interrupt a write cycle which has
commenced.
Hold (HOLD). The HOLD pin is used to pauseserial communications with a ST95P04 without
resetting the serial sequence. To take the Hold
condition into account, the product must be se-
lected (S = 0). Then the Hold state is validated by
a high to low transition on HOLD when C is low. To
resume the communications, HOLD is brought high
when C is low. During Hold condition D, Q, and C
are at a high impedance state.
When the ST95P04 is under Hold condition, it is
possible to deselect it. However, the serial commu-
nications will remain paused after a reselect, and
the chip will be reset.
OPERATIONSAll instructions, addresses and data are shifted in
and out of the chip MSB first. Data input (D) is
sampled on the first rising edge of clock (C) after
the chip select (S) goes low. Prior to any operation,
a one-byte instruction code must be entered in the
chip. This code is entered via the data input (D),
and latched on the rising edge of the clock input
(C). T o enter an instruction code, the product must
have been previously selected (S = low). T able 7
shows the instruction set and format for device
operation. When an invalid instruction is sent (one
not contained in Table 7), the chip is automatically
deselected. For operations that read or write data
in the memory array, bit 3 of the instruction is the
MSB of the address, otherwise, it is a don’t care.
Write Enable (WREN) and Write Disable (WRDI)The ST95P04 contains a write enable latch. This
latch must be set prior to every WRITE or WRSR
operation. The WREN instruction will set the latch
and the WRDI instruction will reset the latch. The
latch is reset under all the following conditions: W pin is low Power on WRDI instruction executed WRSR instruction executed WRITE instruction executed
As soon as the WREN or WRDI instruction is
received by the ST95P04, the circuit executes the
instruction and enters a wait mode until it is dese-
lected.
ST95P04
Read Status Register (RDSR)The RDSR instruction provides access to the status
register. The status register may be read at any
time, even during a non-volatile write. As soon as
the 8th bit of the status register is read out, the
ST95P04 enters a wait mode (data on D are not
decoded, Q is in Hi-Z) until it is deselected.
The status register format is as follows: b0
BP1, BP0: Read and Write bits
WEL, WIP: Read only bits.
During a non-volatile write to the memory array, all
bits BP1, BP0, WEL, WIP are valid and can be read.
During a non volatile write to the status register, the
only bits WEL and WIP are valid and can be read.
The values of BP1 and BP0 read at that time
correspond to the previous contents of the status
register.
The Write-In-Process (WIP) read only bit indicates
whether the ST95P04 is busy with a write opera-
tion. When set to a ’1’ a write is in progress, when
set to a ’0’ no write is in progress.
The Write Enable Latch (WEL) read only bit indi-
cates the status of the write enable latch. When set
to a ’1’ the latch is set, when set to a ’0’ the latch is
reset.
The Block Protect (BP0 and BP1) bits indicate the
extent of the protection employed. These bits are
set by the user issuing the WRSR instruction.
These bits are non-volatile.
Write Status Register (WRSR)The WRSR instruction allows the user to select the
size of protected memory. The ST95P04 is divided
into four 1024 bit blocks. The user may read the
blocks but will be unable to write within the selected
blocks.
The blocks and respective WRSR control bits are
shown in Table 6.
When the WRSR instruction and the 8 bits of the
Status Register are latched-in, the internal write
cycle is then triggered by the rising edge of S. This
rising edge of S must appear after the 8th bit of the
Status Register content (it must not appear a 17th
clock pulse before the rising edge of S), otherwise
the internal write sequence is not performed.
Read OperationThe chip is first selected by putting S low. The serial
one byte read instruction is followed by a one byte
address (A7-A0), each bit being latched-in during
the rising edge of the clock (C). Bit 3 of the read
instruction contains address A8 (most significant
address bit). This bit is used to select the first or
second page of the device. Then, the data stored
in the memory at the selected address is shifted out
on the Q output pin; each bit being shifted out
during the falling edge of the clock (C). The data
stored in the memory at the next address can be
read in sequence by continuing to provide clock
Table 6. Array Addresses Protect
Table 7. Instruction Set
Notes: A = 1, Upper page selected
A = 0, Lower page selected
X = Don’t care
ST95P04
