93L425ADC ,-0.5 V to +7 V, 1024 x 1-bit static random access memoryFeatures TRl-STATE© output
I Power dissipation decreases with increasing tempera-
ture
Connectio ..
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93L425ADC
-0.5 V to +7 V, 1024 x 1-bit static random access memory
93L425A
National
Semiconductor
93L425A
1024 x 1-Bit Static Random Access Memory
General Description
The 93L425A is a 1024-bit read write Random Access
Memory (RAM), organized 1024 words by one bit. It is de-
signed for high speed cache control and buffer storage ap-
plications. The device includes full on-chip decoding, sepa-
rate Data input and non-inverting Data output, as well as an
active LOW Chip Select line.
Features
a New design to replace old 93425/93L425
n Improved ESD threshoids
11 Alpha hard without die coat
a Commercial address access time
93L425A
II Features TRl-STATE® output
I! Power dissipation decreases with increasing tempera-
25 ns max
Connection Diagram
16-Pln DIP
cs-1 16 -hx
Ao-- 2 15 .-o
A1- 3 14 -w_s
M-- 4 13 -A9
M- 5 12 -" "
M-' 6 11 -A7
0- 7 10 -A6
GND‘ 8 9 -A5
TL/D/lot'
Top View
Order Number 93L425ADC or 93L425APC
See NS Package Number J16A' or N16E'
Optional Processing OR = Burn-ln
"For most current package information, contact product marketing.
Logic Symbol
CS D WE
6-- " 93L425A
Io- A6
. ll- A7
voc -- P|n16
GND = Pine 12-- M
ts- A9 0
TL/D/10004-3
Pln Names
c-s Chip Select (Active LOW)
A0-A9 Address Inputs
WE Write Enable Input (Active LOW)
D Data Input
0 Data Output
Absolute Maximum Ratings
Above which the useful life may be impaired
If Mllltary/Aerospaee specified devices are required,
please contact the National Semiconductor Sales
oftltte/Dlstrlbutortt for avaliablllty and speclflcatlons.
Storage Temperature - 65''C to + 150''C
Guaranteed Operating Ranges
Supply Voltage (Vcc)
Commercial 5.0V i 5%
Case Temperature (T C)
Commercial 0°C to + 75°C
Supply Voltage Range - 0.5V to + 7.0V
Input Voltage (DC) (Note 1) - 0.5V to V00
Input Current (DC) - 12 mA to + 5.0 mA
Voltage Applied to Outputs
(Note 2) - 0.5V to 5.5V
Lead Temperature (Soldering, 10 sec.) 300°C
Maximum Junction Temperature (T J) + 175“C
Output Current + 20 mA
DC Characteristics overoperating temperature ranges (Note 3)
Symbol Parameter Condltlons Min Typ Max Unlts
VOH Output HIGH Voltage Vcc = Min, IOH = -5.2 mA 2.4 V
VOL Output LOW Voltage VCC = Min, IOL = 16 mA 0.45 V
" Input HIGH Voltage Guaranteed Input HIGH Voltage 2.1 V
for All Inputs (Notes 4, 5, 8 6)
" Input LOW Voltage Guaranteed Input LOW Voltage 0.8 V
for All Inputs (Notes 4, 5, & 6)
k Input LOW Current Vcc = Max, VIN == 0.4V -180 -300 pA
I.“ Input HIGH Current Vcc = Max,le = 4.5V 1.0 40 pA
|ng Input Breakdown Current Vcc = Max, VIN = Vcc 1.0 f mA
VIC Input Diode Clamp Voltage Vcc = Max, hN = -10 mA -1.0 -1.5 V
IOZH Output Current (HIGH Z) Vcc = Max, VOUT = 2.4V 50 HA
IQZL Vcc = Max, VOUT = 0.5V -50 p.A
los Output Current Short Circuit Vcc = Max (Note 7) _ 1 00 m A
to Ground (Note 7)
ICC PowerSupply Current Vcc = Max, All Inputs = GND, 65 m A
Output Open
VSZV186
93L425A
AC Electrical Characteristics (Note 6) vcc = 5.0 t5%, GND = ov, Tc = WC to + 75''C
Symbol Parameter Conditions Min Max Units
READ TIMING
tACS Chip Select Access Time Figures 15 ns
tzncs Chip Select to HIGH 2 Sa, a, 15 ns
tAA Address Access Time (Note 8) 25 ns
WRITE TIMING
tw Write PuIse Width to Guarantee 20 ns
Writing (Note 9)
twso Data Setup Time Prior to Write ns
tWHD Data Hold Time after Write 5 ns
tWSA tt'tr'i'tt'2,t,''9T)imt' Prior Figure 4 5 ns
tWHA Address Hold Time after Write 5 ns
twscs Chip Select Setup Time Prior to Write 5 ns
tWHcs Chip Select Hold Time after Write 5 ns
tzws Write Enable to Output Disable 15 ns
twn Write Recovery Time 15 ns
Note 1: Either input voltage limit or input current limit is sufficient to protect the inputs.
Note 2: Output current limit required.
Note & Typical values are at Voc - 5.0V, Tc = + 25°C and maximum loading.
Note 4: Static condition only.
Now 5: Functional testing done at input levels v,” = 0.45v (VOL Max) and V», = 2.4V (VoH Min).
Note 6: AC tssting done at input levels " = 3V, Vit. = 0V.
Note P. Short circuit to ground not to exceed one second.
Note 8: The maximum address access time is guaranteed to be the worst case bit in the memory using a pseudorandom testing pattern.
Note 9: tw measured at twsA = Min. tWSA measured at tw = Min.
Logic Diagram
32 It 32
wono - ARRAY
DRIVER
' SENSE mp5
m rE--Clt-... cs
DRIVERS
3233352: ADDRESS
DECODER _D
AOAtAZASM A5A6A7ABA9
Functional Description
The 93L425A is a fully decoded 1024-bit read write Random
Access Memory organized 1024 words by one bit. Bit stslec-
tion is achieved by means of a 10-bit address Ao-A9.
One Chip Select (E) input is provided for easy memory
array expansion of up to 2048 bits without the need for ex-
ternal decoding. For larger memories the fast chip select
access time permits direct address decoding without an in.
crease in overall memory access time.
The read and write functions of the 93L425A are controlled
by the state of the active LOW Write Enable W input.
When WI? is held LOW and the chip is selected. the data at
D is written into the location specified by the binary address
present at A0 through A9. Since the write function is level
triggered, data must be held stable at the data input for at
least twsmmmpius tW(min) plus tWHD(rnin) to insure a valid
write. When WE is held HIGH and the chip selected, data is
read from the addressed location and presented at the out-
put o.
TL/Df10004-2
The 93L425A has a three-state output which provides an
active puli-up or pull-down when enabled and a high imped-
ance (HIGH Z) state when disabled. The active puil-up pro-
vides drive capability for high capacitive loads while the high
impedance state allows optimization of word expansion in
bus organized systems.
Truth Table or"
- "tl" Outputs Mode
cs WE D o
H H X HIGH Z Not Selected
L L L HIGH 2 Write 0
L L H HIGH Z Write 1
L H X DOUT Read
H = HIGH Voltage Level: 2.4V
L = LOW Voltage Level: 0.45V
X = Don't Care HIGH or LOW
HIGH 2 = High-Impedance
VSZV'EG
93L425A
93L425A soon 300');
LOAD A =
TL/D/10004-4
93L425A soon 3tPpF
LOAD B =
TL/ D/10004- 5
Non: Load A is used for all production testing.
'lncludes lig and probe capacitance.
FIGURE 1. AC Test Output Load
TL/D/10004-8
FIGURE 2. " Test Input Levels
cm? SELECT .
- - HIGH l - .
LOAD A E 0.5V
cm oumn I
LOAD tt 1.5V N J,
o- "IGHZOCOOO -.rllt9H Z.-
- ttcs d
TL/D/10004-6
at. Read Mode Propagation Delay from Chip Select
ADDRESS 1.5V
DATA oumns 1.5V
TL/DM0004-7
3b. Read Mode Propagation Delay from Address
FIGURE 3. Read Mode Tlmlng
CHIP SELECT 1 .5V
ADDRESS 1 .5V
DATA INPUT )6 .5V
WRITE ENABLE N: 1.5V 7
‘wso tmo
trea two
twscs trmcs
'F "-trws %
LOAD a ir, fcr-
DATA OUTPUT 11:11:: 21.1....X
LOAD A__J_ t//'" Cd
TL/D/1OOD4-O
Note 1: Timing Diagram represents one solution which results In an optimum cycle time Timing may be changed to fit various applications as long u my worst
case limits are not violated.
Note 2: Input voltage leveis for worst case AC test are 3.0V-0V.
FIGURE 4. Write Mode Tlmlng
V5317186
This datasheet has been :
www.ic-phoenix.com
Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
corp/docs/irwestor_relations/Pr_09_23_201 1_national_semiconductor.html
This file is the datasheet for the following electronic components:
93L425ADC - product/93I425adc?HQS=T|-nu||-nu|l-dscataIog-df-pf-null-wwe
93L425APC - product/93I425apc?HQS=T|-nuIl-nu|I-dscataIog-df-pf-null-wwe
