93L422APC ,-0.5 V to +7 V, 256 x 4-bit static random access memoryFeatures
The 93L422A is a 1024-bit read/write Random Access I New design to replace old 93422/93 ..
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I Power dissipation decreases with increasing tempera-
ture
Connectio ..
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93L422ADC-93L422APC
-0.5 V to +7 V, 256 x 4-bit static random access memory
93L422A
National
93L422A
Semiconductor
256 x 4-Bit Static Random Access Memory
General Description
The 93L422A is a 1024-bit read/write Random Access
Features
a New design to replace old 93422/93L422
Memory (RAM) organized 256 words by four bits. It is de- " Improved ESD thresholds
signed for high speed cache, control and buffer storage ap- u Alpha hard without die coat
plications. The device includes full on-chip decoding, sepa- a Commercial address access time
rate Data input and non-inverting Data output, as well as
two Chip Select Lines.
93L422A
Fully TTL compatible
:1 Features TRl-STATEO outputs
n Power dissipation decreases with increasing tempera-
Connection Diagram
22-Pin DIP Pln Names
M- 1 V 22 -e AO-A? Address Inputs
M-- 2 21 "-A4 DO-D3 Data Inputs
M- 3 20 "E $1 Chip Selectlnput(Ac1ive LOW)
A0- 4 19 -cs1
A5- 5 18 -tTt CS2 Chip Select Input (Active HIGH)
A5- 5 " -cs2 W_E Write Enable Input (Active LQW)
A7- 7 16 -03 .
GND- 8 15 -03 TE Output Enable Input (Active LOW)
Me s 14 -oe 00-03 Data Outputs
oo-_ 10 13 -t)2
ot- 11 12 -01
TL/D/9996-1
Top View
Order Number 93L422ADC or 93L422APC
See NS Package Number J22A* or N22A*
Optional Processing OR = Burn-In
. For most current package information, contact product marketing
Logic Symbol
19 17 (22) (9)(11)(15)(17)
(21) (mm ' ll 13 15
tls WEDODIDZDS
(4) 4-- M
(3) '- Al
(2) 2--- M
(1) I-- M
(23) tl- "
(5) _ M
(5) _ M
(7) T-. A7
93L422A
tE 00 0102 03
18 10 12 " 16
(20)(IO)(14)(16)(18)
TL/D/9996-3
Absolute Maximum Ratings
Above which the useful life may be impaired
If Mllltary/Aerospace ttpetrified devices are required,
please contact the National Sttrttleondttetttr Sales
OfflttefDlatrhutors for availability and speclflcatlons.
Guaranteed Operating Ranges
Supply Voltage (Vcc)
Case Temperature (T c)
Storage Temperature - 65°C to + 1 50°C
Supply Voltage Range - 0.5V to + 7.0V
Input Voltage (DC) (Note I) - 0.5V to Vcc
Input Current (DC) - 12 mA to + 5.0 mA
Voltage Applied to Outputs (Note 2) -0.5V to + 5.5V
Lead Temperature (Soldering, 10 sec.) 300°C
Maximum Junction Temperature (T J) + 175°C
Output Current + 20 mA
DC Characteristics overoperating temperature ranges (Note 3)
5.0V i 5%
tPC to + 75'C
Symbol Parameter Conditions Mln Typ Max Units
VOL Output LOW Voltage Vcc = Min, IOL = 8 mA 0.3 0.45 V
VIH Input HIGH Voltage Guaranteed Input HIGH Voltage 2.1
for All Inputs (Notes 4, 5 8 6)
" Input LOW Voltage Guaranteed Input LOW Voltage 0.8
for All Inputs (Notes 4, 5 & 6)
VOH Output HIGH Voltage VCC = Min, lor, = -5.2V 2.4 V
Itt. Input LOW Current VCC = Max, VIN = 0.4V - 150 -300 MA
IIH Input HIGH Current VCC == Max, VIN Ir..', 4.5V 1.0 40 pA
|ng Input Breakdown Current VCC = Max, VIN = VCC 1.0 mA
VIC Input Diode Clamp Voltage Vcc = Max, IIN = -10 mA -1.0 -1.5 ' ' V
IOZH OutputCurrent (HIGH Z) Vcc = Max, VOUT = 2.4V 50 ps/k
IOZL Vcc = Max, VOUT = 0.5V -50 “A
los f?.utpet Current Short Vcc = Max (Note 7) - 10 -70 m A
Circuit to Ground
ICC Power Supply Current Vcc = Max, All Outputs Open, 80 m A
All Inputs = GND
VZZV'IEG
93L422A
AC Electrical Characteristics (Note 6) vcc = 5.0V 15%, GND == ov, To == ty'C to +75°c
Symbol l Parameter Condltlons Mln J Max Units
READ TIMING
tAcs Chip Select Access Time 20 ns
tzncs Chip Select to High Z Figures 20 ns
tAOS Output Enable Access Time ae, 3b, a, 20 ns
tzaos Output Enable to HIGH Z 20 ns
tAA Address Access Time (Note 8) 25 ns
WRITE TIMING
tw Write Pulse Width to Guarantee Writing 20 ns
(Note 9)
twso Data Setup Tlme prior to erte 5 ns
mm Data Hold Tlme after erte "
MSA 3315:: Setup Tlme prlor to Write Figure 4 6 n3
tWHA Address Hold Time after erte ns
twscs Chlp Select Setup Tlme prior to Write na
tWHCS Chlp Select Hold Time after Write ns
tzws Write Enable to Output Dlsable 20 n3
twa Write Recovery Time 20 na
Note It Either Input voltage llmlt or Input current limit ttumtMnt to proteetN Inputs.
Nate 2: Output current Ilmlt required.
Note 3: Typical values are at Vcc -- 5.0V. to = +25'C and maximum loading.
Note 4: Static condition only.
Note 5: Functional testing done at input levels " = 0.45V (VOL Max) and V.” - 2.4V (VOH Min).
Note 6.. AC tes0nt; done at input levets " = 3V, " = OV.
Note r.. Short circuit to ground not to exceed one second; ground only one output at a tlme.
Note a: The maximum address access time Is guaranteed to be the womt case bit In the memory using a pseudomndom tasking pattern.
Note P. tw measured at tWSA = Min. twsA measured at tw :- Min.
Logic Diagram
00 0102 03
CONTROL
32 x 32
MEMORY
COLUMN
SELECT
INPUT DATA
A5 A6 A7
TL/D/9996-2
Truth Table
Inputs Outputs
(TE E1 CS2 WE TRl-STATE Mode
X H X X HIGH Z Not Selected
X X L X HIGH 2 Not Selected
L L H H Dom READ
X L H L HIGH Z WRITE
H X X X HIGH 2 Output Disabied
H .. HIGH Voltage Level 2.4V
L " LOW Voltage Level 0.45V
X " Don't Care HIGH or LOW
HiGH I - Hlgh4mpsdatttm
Functional Description
The 93L422A is a fully decoded 1024-blt Random Access
Memory organized 256 words by four bits. Word selection is
achieved by means of an 8-bit address A0-A7.
Two Chip Select Inputs, inverting and non-inverting, are pro-
vided tor logic flexibility. For larger memories, the fast chip
select access time permits the decoding of the chip selects
from the address without increasing address access time.
The read and write operations are controlled by the state of
the active LOW Write Enable WE input. When WE is held
LOW and the chlp is selected, the data at DO-Da is written
into the address location. Since the write function is level-
trlggered. data must be held stable for at least twso (MIn)
plus tw (Min) plus tWHD (Min) to insure a valid write. To read,
WE is held high. the chip is selected. and the data is trans-
ferred to the outputs (OO-OW.
The 93L422A has TRI-STATE outputs which provide active
pull-ups when enabled and high output impedance when
disabled. This allows optimization of word expansion in bus
organized systems.
VZZV'ISG
93L422A
Functional Description (Continued)
Load A Load B
Vet tmo
60011 600.0
00 - N 00 - 03
93L422A 1.2 " 1tPpF 93L422A 1.2 kit 15'pF
TL/D/9996-4 TL/D/9996-5
‘lncludes jig and probe capacitance
Note: Load A is used tor all production testing.
FIGURE t. AC Test Output Load
TL/D/9996-6
FIGURE 2. Ac Test Input Levels
AMESS 1.5V
DATA ourPtns k,,
TLfD/9996-7
3a. Read Mode Propagation Delay from Address
Cttlft sums 1.5V t-itnitttiit
HIGHZ------- mauz HIGHZ------- HIGH:
LOAD A CY LOAD A "
om ouwurs , I om oumns . I
LOAD a ir,f, LOAD l? NT;
mcaz-nn-o mouz HIGHZ'------ HIGHZ
TL/D/9996-tl TL/D/9996-9
3b. Read Mode Propagation Delay from Chlp Select 3c. Read Mode Propagation Delay from Output Enable
FIGURE 3. Read Mode Testing
Functional Description (Continued)
CHIP SE_LECTS
CSI , CS2
ADDRESS
A0 - A7
DATA N
WRITE ENABLE
case limits are not violated.
FIGURE 4. Write Mode Tlmlng
Note 1: Timing Diagram represents one solution which results in an optimium cycle time. Timing may be changed to fit various applications as long as the worst
Note 2: Input voltage levels for worst case AC test are 3.0V-0V.
fl: 1.5V /
‘wsn tmm
tus, ‘WHA
twscs tmas
LOAD B-of-- 't / 1 5V
DAIA OUTPUTS ----HIGH z-----7
00-03 [----chH "Ts
LOAD A --sl-v- 7 N 1.5Y
TL/ D(.9996- 10
VZZV'ISG
This datasheet has been :
www.ic-phoenix.com
Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
corp/docs/irwestor_relations/Pr_09_23_201 1_national_semiconductor.html
This file is the datasheet for the following electronic components:
93L422ADC - product/93I422adc?HQS=T|-nu||-nu|l-dscataIog-df-pf-null-wwe
93L422APC - product/93I4223pc?HQS=T|-nuIl-nu|I-dscataIog-df-pf-null-wwe
