93CS46-ST93CS46M1013TR-ST93CS47M1013TR Fast Delivery |IC PHOENIX CO.,LIMITED

ST93CS46M1013TR ,1K 64 x 16 SERIAL MICROWIRE EEPROMST93CS46ST93CS471K (64 x 16) SERIAL MICROWIRE EEPROMNOT FOR NEW DESIGN1 MILLION ERASE/WRITE CYCLES, ..
ST93CS47M1013TR ,1K 64 x 16 SERIAL MICROWIRE EEPROMLogic DiagramDESCRIPTIONThe ST93CS46 and ST93CS47 are 1K bit Electri-cally Erasable Programmable Me ..
ST93CS66ML6013TR ,4K 256 x 16 SERIAL MICROWIRE EEPROM
ST95010WM6TR ,4K/2K/1K Serial SPI EEPROM with Positive Clock Strobe
ST95020M6TR ,4K/2K/1K Serial SPI EEPROM with Positive Clock Strobe
ST95022M3TR ,2 Kbit Serial SPI EEPROM with High Speed Clock
STR-Z2154 ,STR-Z2154 circuit
STS100 , Multifunction Telecommunications Switch
STS10DN3LH5 ,Dual N-channel 30 V, 0.019 Ohm;, 10 A, SO-8 STripFET (TM); V Power MOSFETElectrical characteristics(T = 25 °C unless otherwise specified)CASE Table 4. Static Symbol Paramet ..
STS10N3LH5 ,N-channel 30 V, 0.019 Ohm;, 10 A, SO-8 STripFET(TM); V Power MOSFETElectrical characteristics(T = 25 °C unless otherwise specified)CASE Table 4. Static Symbol Paramet ..
STS10NF30L ,N-CHANNEL 30VSTS10NF30L®N - CHANNEL 30V - 0.011Ω - 10A SO-8STripFET™ POWER MOSFETPRELIMINARY DATATYPE V R IDSS ..
STS10PF30L ,P-CHANNEL 30VABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V = 0) 30 VDS GSV Drain- ..

93CS46-ST93CS46M1013TR-ST93CS47M1013TR
1K 64 x 16 SERIAL MICROWIRE EEPROM
ST93CS46
ST93CS47 (64x 16) SERIAL MICROWIRE EEPROM
NOT FOR NEW DESIGN
June 1997 1/16
AI00884BCC
ST93CS46
ST93CS47
VSS
PRE
Figure1. Logic Diagram MILLION ERASE/WRITE CYCLES, with YEARS DATA RETENTION
SELF-TIMED PROGRAMMINGCYCLE with
AUTO-ERASE
READY/BUSYSIGNAL DURING
PROGRAMMING
SINGLE SUPPLY VOLTAGE 3Vto 5.5Vfor the ST93CS46 2.5Vto 5.5Vfor the ST93CS47
USER DEFINED WRITE PROTECTED AREA
PAGE WRITE MODE(4 WORDS)
SEQUENTIAL READ OPERATION
5ms TYPICAL PROGRAMMING TIME
ST93CS46 and ST93CS47 are replacedby
the M93S46
DESCRIPTION
The ST93CS46 and ST93CS47 are 1Kbit Electri-
cally Erasable Programmable Memory (EEPROM)
fabricated with SGS-THOMSON’s High Endurance
Single Polysilicon CMOS technology. The memory accessed througha serial inputD and outputQ.
The 1K bit memoryis organized as 64x 16 bit
words.The memoryis accessedbya setof instruc-
tions which include Read, Write, Page Write, Write
All and instructionsusedto set the memory protec-
tion.A Read instruction loads the addressof the
first wordto be read into an internal address
pointer. Chip Select Input Serial Data Input Serial Data Output Serial Clock
PRE Protect Enable Write Enable
VCC Supply Voltage
VSS Ground
Table1. Signal Names
SO8 (M)
150mil Width
PSDIP8 (B)
0.4mm Frame
DESCRIPTION (cont’d)
The datais then clocked out serially. The address
pointeris automaticallyincremented after the data output and,if the Chip Select input (S)is held
High, the ST93CS46/47 can outputa sequential
streamof data words.In this way, the memory can readasa data streamof 16to 1024 bits,or
continuouslyas the address counter automatically
rolls overto 00 when the highest addressis
reached. Within the time requiredbya program-
ming cycle (tW),upto4 words maybe written with
the helpof the Page Write instruction; the whole
memory may alsobe erased,or settoa predeter-
mined pattern,by using the WriteAll instruction.
Within the memory,an user defined area maybe
protected against further Write instructions. The
sizeof this areais defined by the contentofa
VSSQ
PREC
SVCC
AI00885B
ST93CS46
ST93CS47
Figure 2A. DIP Pin Connections
VSSQ
PREC
SVCC
AI00886C
ST93CS46
ST93CS47
Figure 2B. SO Pin Connections
Symbol Parameter Value Unit Ambient Operating Temperature –40 to85 °C
TSTG Storage Temperature –65 to150 °C
TLEAD Lead Temperature, Soldering (SO8 package)
(PSDIP8 package) sec sec
260 °C
VIO Inputor Output Voltages(Q= VOHor Hi-Z) –0.3to VCC +0.5 V
VCC Supply Voltage –0.3to 6.5 V
VESD Electrostatic Discharge Voltage (Human Body model)(2) 3000 V
Electrostatic Discharge Voltage (Machine model)(3) 500 V
Notes:1. Exceptfor therating ”Operating Temperature Range”, stresses above those listedinthe Table ”Absolute MaximumRatings”
may causepermanent damageto thedevice. Theseare stress ratings onlyand operationof thedeviceat theseor anyother
conditions abovethose indicatedinthe Operating sectionsofthis specificationisnot implied. Exposureto Absolute Maximum
Rating conditionsfor extendedperiods may affect device reliability.Refer alsotothe SGS-THOMSON SURE Programand other
relevant quality documents. MIL-STD-883C, 3015.7 (100pF,1500Ω). EIAJ IC-121 (ConditionC) (200pF,0Ω).
Table2. Absolute Maximum Ratings(1)
Protect Register, located outsideof the memory
array.Asa final protection step, data maybe per-
manently protectedby programminga One Time
Programingbit (OTP bit) which locks the Protect
Register content.
Programmingis internally self-timed (the external
clock signalonC input maybe disconnectedor left
running after the startofa Write cycle) and does
not requirean erase cycle priorto the Writeinstruc-
tion. The Writeinstruction writes16 bitsat onetime
intooneof the 64words, the Page Write instruction
writesupto4 wordsof16 bitsto sequentialloca-
tions, assumingin both cases that all addresses
are outside the Write Protected area.
After the start of the programming cycle,a
Ready/Busysignalis availableon the Data output
(Q) when the Chip Select (S) input pinis driven
High.
2/16
ST93CS46, ST93CS47
Input Rise and Fall Times ≤ 20ns (10%to 90%)
Input Pulse Voltages 0.4Vto 2.4V
Input and Output Timing
Reference Voltages 0.8 and2V MEASUREMENT CONDITIONS
Note that Output Hi-Zis definedas the point where datano longer driven.
AI00825
0.8VCC
0.2VCC
0.7VCC
0.3VCC
Figure3. AC Testing Input Output Waveforms
Symbol Parameter Test Condition Min Max Unit
CIN Input Capacitance VIN =0V 5 pF
COUT Output Capacitance VOUT =0V 5 pF
Note:1. Sampled only,not 100% tested.
Table3. Capacitance(1)
(TA =25 °C,f=1 MHz)
Symbol Parameter Test Condition Min Max Unit
ILI Input Leakage Current 0V≤ VIN≤ VCC ±2.5 μA
ILO Output LeakageCurrent 0V≤ VOUT≤ VCC, inHi-Z ±2.5 μA
ICC Supply Current (TTL Inputs) S= VIH,f=1 MHz 3 mA
Supply Current (CMOS Inputs) S= VIH,f=1 MHz 2 mA
ICC1 Supply Current (Standby) S= VSS,C= VSS 50 μA
VIL
Input Low Voltage (ST93CS46,47) 4.5V≤ VCC≤ 5.5V –0.1 0.8 V
Input Low Voltage (ST93CS46) 3V≤ VCC≤ 5.5V –0.1 0.2 VCC V
Input Low Voltage (ST93CS47) 2.5V≤ VCC≤ 5.5V –0.1 0.2 VCC V
VIH
Input High Voltage (ST93CS46,47) 4.5V≤ VCC≤ 5.5V 2 VCC +1 V
Input High Voltage (ST93CS46) 3V≤ VCC≤ 5.5V 0.8 VCC VCC +1 V
Input High Voltage (ST93CS47) 2.5V≤ VCC≤ 5.5V 0.8 VCC VCC +1 V
VOL Output Low Voltage IOL= 2.1mA 0.4 V
IOL =10μA 0.2 V
VOH Output High Voltage IOH= –400μA 2.4 V
IOH= –10μAVCC –0.2 V
Table4. DC Characteristics (TA=0to 70°Cor –40to 85°C; VCC= 3Vto 5.5Vfor ST93CS46 and
VCC= 2.5Vto 5.5V for ST93CS47)
3/16
ST93CS46, ST93CS47
Symbol Alt Parameter Test Condition Min Max Unit
tPRVCH tPRES Protect Enable Validto Clock High 50 ns
tWVCH tPES Write Enable Validto Clock High 50 ns
tSHCH tCSS Chip Select Highto Clock High 50 ns
tDVCH tDIS Input Validto Clock High 100 ns
tCHDX tDIH Clock Highto Input Transition 100 ns
tCHQL tPD0 Clock Highto Output Low 500 ns
tCHQV tPD1 Clock Highto Output Valid 500 ns
tCLPRX tPREH Clock Lowto Protect Enable Transition 0 ns
tSLWX tPEH Chip Select Lowto Write Enable Transition 250 ns
tCLSL tCSH Clock Lowto Chip Select Transition 0 ns
tSLSH tCS Chip Select Lowto Chip Select High Note1 250 ns
tSHQV tSV Chip Select Highto Output Valid 500 ns
tSLQZ tDF Chip Select Lowto Output Hi-Z 300 ns
tCHCL tSKH Clock Highto Clock Low Note2 250 ns
tCLCH tSKL Clock Lowto Clock High Note2 250 ns tWP Erase/Write Cycle time 10 ms fSK Clock Frequency 0 1 MHz
Notes:1. Chip Select mustbe broughtlowfora minimumof250ns (tSLSH) betweenconsecutive instruction cycles. The Clock frequency specification callsfora minimum clockperiodof1μs, thereforethe sumofthe timings tCHCL +tCLCH
mustbe greateror equalto 1μs.For example, iftCHCLis 250ns, then tCLCH mustbeat least 750ns.
Table5. DC Characteristics (TA=0to 70°Cor –40to 85°C; VCC= 3Vto 5.5Vfor ST93CS46 and
VCC= 2.5Vto 5.5V for ST93CS47)
PRE OP CODE OP CODESTART
START CODEINPUT
tCHDXtDVCH
tSHCH tCLCH
tCHCLtWVCH
tPRVCH
AI00887
Figure4. Synchronous Timing, Start and Op-Code Input
4/16
ST93CS46, ST93CS47
Figure5. Synchronous Timing,Reador Write
AI00820C
ADDRESS INPUT
Hi-Z
tDVCH
tCLSL
DATA OUTPUT
tCHQVtCHDX
tCHQL
tSLSH
tSLQZ
Q15/Q7 Q0
PRE
Hi-Z
tDVCH
AI00888B
tCLPRX
tSLWX
tCLSL
tCHDX
tSLSH
tSLQZ
BUSY
tSHQV
READY
WRITE CYCLEADDRESS/DATA INPUT A0/D0
5/16
ST93CS46, ST93CS47
POWER-ON DATA PROTECTION orderto prevent data corruption and inadvertent
write operations during power up,a Power On
Reset(POR) circuit resetsall internalprogramming
circuitry and sets the devicein the Write Disable
mode. When VCC reachesits functional value, the
deviceis properlyreset(in the Write Disable mode)
andis readyto decode and executean incoming
instruction.A stable VCC mustbe applied before
any logic signal.
INSTRUCTIONS
The ST93CS46/47 has eleven instructions, as
shownin Table6. Each instructionis precededby
the rising edgeof the signal appliedon the Chip
Select (S) input (assuming that the ClockCis low),
followedbya’1’ readonD input during the rising
edgeof the clockC. The op-codesof the instruc-
tions are made upof the2 following bits. Some
instructionsuse only these first two bits, othersuse
also the first two bitsof the address fieldto define
the op-code. The address fieldis six bits long
(A5-A0).
The ST93CS46/47is fabricatedin CMOS technol-
ogyandis thereforeableto run from zeroHz (static
input signals)upto the maximum ratings (specified Table5).
Read
The Read instruction (READ) outputs serial data the Data Output (Q). Whena READinstruction received, the instruction and address are de-
coded and the data from the memoryis transferred
intoan outputshiftregister.Adummy’0’bit isoutput
first followedby the16 bitword with the MSB first.
Instruction Description W
Pin(1) PRE
Pin
Code Address(1) Data Additional
Information
READ Read Data from Memory X ’0’ 10 A5-A0 Q15-Q0
WRITE Write Datato Memory ’1’ ’0’ 01 A5-A0 D15-D0
Writeis executedif
the addressisnot
inside the Protected
area
PAWRITE Page Writeto Memory ’1’ ’0’ 11 A5-A0 D15-D0
Writeis executedif
all the addresses
are not inside the
Protected area
WRALL WriteAll Memory ’1’ ’0’ 00 01XXXX D15-D0
Writeall dataifthe
Protect Registeris
cleared
WEN Write Enable ’1’ ’0’ 00 11XXXX
WDS Write Disable X ’0’ 00 00XXXX
PRREAD Protect Register Read X ’1’ 10 XXXXXX Q8-Q0
Data Output=
Protect Register
content+ Protect
Flagbit
PRWRITE Protect Register Write ’1’ ’1’ 01 A5-A0
Data above
specified address
A5-A0 are protected
PRCLEAR Protect Register Clear ’1’ ’1’ 11 111111
Protect Flagis also
cleared (cleared
Flag=1)
PREN Protect Register Enable ’1’ ’1’ 00 11XXXX
PRDS Protect Register Disable ’1’ ’1’ 00 000000 OTPbitisset
permanently
Note:1.X =don’t carebit.
Table6. Instruction Set
6/16
ST93CS46, ST93CS47
Output data changes are triggeredby the Lowto
High transitionof the Clock (C). The ST93CS46/47
will automatically increment the address and will
clock out the next wordas longas the Chip Select
input (S)is held High.In this case the dummy’0’bit NOT output between words anda continuous
streamof data canbe read.
Write Enable and Write Disable
The Write Enable instruction (WEN) authorizesthe
following Write instructionsto be executed, the
Write Disable instruction (WDS) disables the exe-
cutionof the following Erase/Write instructions.
When poweris first applied, the ST93CS46/47
enters the Disable mode. When the Write Enable
instruction (WEN)is executed, Write instructions
remain enabled untila Write Disable instruction
(WDS)is executedorif the Power-on reset circuit
becomes active duetoa reduced VCC.To protect
the memory contents from accidental corruption,it advisableto issue the WDS instruction after
every write cycle.
The READ instructionis not affectedby the WEN WDS instructions.
Write
The Write instruction (WRITE)is followedby the
address and the wordto be written. The Write
Enable signal (W) must be held high during the
WRITE instruction. Data inputDis sampledon the
Lowto High transitionof the clock. After the last
databit has been sampled, Chip Select (S) must brought Low before the next rising edgeof the
clock (C),in orderto startthe self-timed program-
ming cycle, providing thatthe addressis NOT inthe
protected area.If the ST93CS46/47is still per-
forming the programming cycle, the Busy signal(Q0) will be returnedif the Chip Select input (S)is
driven high, and the ST93CS46/47will ignore any
dataonthe bus. Whenthewrite cycle iscompleted,
the Ready signal(Q=1) will indicate(ifSis driven
high) that the ST93CS46/47is readyto receivea
new instruction.
Page Write Page Write instruction (PAWRITE) contains the
first addresstobe written followedbyupto4 data
words. The Write Enable signal (W) mustbe held
High duringtheWrite instruction.Inputaddress and
data are readon the Lowto High transitionof the
clock. After the receiptof each data word, bits
A1-A0of the internal address register are incre-
mented, the high order bits A5-A2 remaining un-
changed. Users must take care by softwareto
ensure that the last word address has the same
four upper order address bitsas the initial address
transmittedto avoid address roll-over.
After the LSBof the last data word, Chip Select (S)
mustbe brought Low before the next rising edgeof
the Clock (C). The falling edgeof Chip Select (S)
initiates the internal, self-timed write cycle. The
Page Write operation will not be performedif any the4 wordsis addressing the protected area.If
the ST93CS46/47is still performing the program-
ming cycle, the Busy signal(Q=0) willbe returned the Chip Select input (S)is driven high, and the
ST93CS46/47 will ignore any data on the bus.
When the write cycleis completed, the Ready
signal(Q=1) will indicate(ifSis driven high) that
the ST93CS46/47is readyto receivea new instruc-
tion.
Write All
The WriteAll instruction (WRALL)is valid only after
the ProtectRegisterhas been cleared byexecuting PRCLEAR (Protect Register Clear) instruction.
The WriteAll instructionsimultaneously writes the
whole memory with the same data word included the instruction. The WriteEnablesignal (W) must held High before and during the Write instruc-
tion. Input address and data are readon the Low High transitionof theclock.If the ST93CS46/47 still performing the programming cycle, the Busy
signal (Q=0) will be returnedif the Chip Select
input (S)is driven high, and the ST93CS46/47 will
ignore any dataon the bus. When the write cycle completed,the Ready signal(Q=1) will indicate
(ifSis driven high) that theST93CS46/47is ready receivea new instruction.
MEMORY WRITE PROTECTION AND PROTECT
REGISTER
The ST93CS46/47 offersa Protect Register con-
taining the bottom addressof the memory area
which hasto be protected against write instruc-
tions.In additionto this Protect Register, two flag
bits are usedto indicate theProtectRegisterstatus:
the Protect Flag enabling/disabling the protection theProtect Register andtheOTPbit which, when
set, disables accessto the Protect Register and
thus prevents any further modificationsof this Pro-
tect Register value. The contentof the Protect
Registeris defined when using the PRWRITEin-
struction,it maybe read when using the PRREAD
instruction.A specific instruction PREN (Protect
Register Enable) allows the userto execute the
protect instructions PRCLEAR, PRWRITE and
PRDS; this PREN instruction being used together
with the signals appliedon the input pins PRE
(Protect Register Enable pin) andW (Write En-
able).
7/16
ST93CS46, ST93CS47
AI00889D0An A0 Q0
DATA OUT
WRITE
ADDR
OP
CODE0 An A0
DATAIN
OP
CODE D01
BUSY READY
WRITE
ENABLE0 XnX0D
OP
CODE01
WRITE
DISABLE0 XnX0D
OP
CODE0
CHECK
STATUS
ADDR
PREREAD
PRE
PRE
PRE
Figure6. READ, WRITE, WEN, WDS Sequences
8/16
ST93CS46, ST93CS47

Partno	Mfg	Dc	Qty	Available	Descript
ST93CS46M1013TR	ST	N/a	1034	avai	1K 64 x 16 SERIAL MICROWIRE EEPROM
ST93CS47M1013TR	STM	N/a	135	avai	1K 64 x 16 SERIAL MICROWIRE EEPROM
93CS46	ROHM	N/a	96	avai	1K 64 x 16 SERIAL MICROWIRE EEPROM