NM93C66N ,Electrically Erasable Programmable MemoriesFeatures
I Typical active current 400 FA; Typical standby current
25 “A
I Reliable CMOS floa ..
NM93CS06EN ,(MICROWIRETM Bus Interface) 256-/1024-/2048-/4096-Bit Serial EEPROM with Data Protect and Sequential ReadNM93CS06/CS46/CS56/CS66(MICROWIREBusInterface)256-/1024-/2048-/4096-BitSerialEEPROMwithDataProtecta ..
NM93CS06N ,(MICROWIRETM Bus Interface) 256-/1024-/2048-/4096-Bit Serial EEPROM with Data Protect and Sequential Readfeatures MICROWIRE interface Typical active current of 200µ Awhich is a 4-wire serial bus with chi ..
NM93CS06N ,(MICROWIRETM Bus Interface) 256-/1024-/2048-/4096-Bit Serial EEPROM with Data Protect and Sequential ReadNM93CS06/CS46/CS56/CS66(MICROWIREBusInterface)256-/1024-/2048-/4096-BitSerialEEPROMwithDataProtecta ..
NM93CS46LEM8 , 256-/1024-/2048-/4096-Bit Serial EEPROM with Extended Voltage (2.7V to 5.5V) and Data Protect (MICROWIRE-TM Bus Interface)
NM93CS46M8 ,(MICROWIRETM Bus Interface) 256-/1024-/2048-/4096-Bit Serial EEPROM with Data Protect and Sequential ReadNM93CS06/CS46/CS56/CS66(MICROWIREBusInterface)256-/1024-/2048-/4096-BitSerialEEPROMwithDataProtecta ..
OD9602N , 3.3-V Photo Diode Preamp Modules
ODC24 , I/O Modules
OES021ZC-A ,One - Ultra-Dense 40W converter
OM4068H ,LCD driver for low multiplex ratesGENERAL DESCRIPTION1⁄3The OM4068 is a low-power CMOS LCD driver, designed• 32 segment driversto dri ..
OM4068H/2 ,OM4068; LCD driver for low multiplex rates
OM4085T/F1 ,OM4085; Universal LCD driver for low multiplex rates
93C56-NM93C56EN-NM93C56M-NM93C56N-NM93C66EN-NM93C66N-NMC93C56
2K 5.0V Automotive Temperature Microwire Serial EEPROM
National
Semiconductor
NMC93C56/C66 2048-Bit/ 40
96-Bit Serial
Electrically Erasable Programmable Memories
General Description
The NMC93C56/NMG93C66 are 2048/4096 bits of CMOS
electrically erasable memory divided into 128/256 16-bit
registers. They are fabricated using National Semiconduc-
tor's floating-gate CMOS process for high speed and low
power. They operate from a single 5V supply since Vpp is
generated on-board. The serial organization allow the
NMC93056/66 to be packaged in an 8-pin DIP or 14-pin so
package to save board space.
The memories feature a serial interface with the instruction,
address, and write data, input on the Data-In (DI) pin. All
read data and device status come out on the Data-Out (DO)
pin. A Iow-to-high transition of shift clock (SK) shifts all data
in and out. This serial Interface is MICROWIFIETM compati-
ble for simple interface to standard microcontrollers and mi-
croprocessors. There are 7 instructions: Read, Erase/Write
Enable, Erase, Erase All, Write, Write All, and Erase/Write
Disable. The NMC93056/66 do not require an erase cycle
prior to the Write and Write All instructions. The Erase and
Erase All instructions are available to maintain complete
read and programming capability with the NMOS NMC9346.
All programming cycles are completely self-timed for simpli-
fied operation. The busy status is available on the DO pin to
indicate the completion of a programming cycle. EEPROMs
are shipped in the erased state where all bits are logical I's.
Compatibility with Other Devices
These memories are pin compatible to Natlonai Semicon-
ductor's NMOS EEPROMs, NMC9306 and NMC9346 and
CMOS EEPROMs NMC93C06/46. The NMC93C56/66 are
both pin and function compatible with the NMC93C06/46,
256/1024-bit EEPROM with the one exception that the
NMC93C56/66 require 2 additional address bits.
Features
a Typical active current 400 FA; Typical standby current
a Reliable CMOS floating gate technology
I: 5V only operation in all modes
I: MICROWIRE compatible serial I/O
n Self-timed programming cycle
" Device status signal during programming mode
a Sequential register read
It Over 40 years data retention
u Designed for 100,000 write cycles
Block Diagram
QQOSSOWNIQSOESOWN
CS " msmucnou - Vcc
SK DEDODER,
msmucnou CONTROL LOGIC,
th mm a AND CLOCK
GENERATORS.
ADDRESS HIGH vomc:
mm“ GENERATOR
PROGRAM
Vpp “KER
mac» ARRAY
1 J/c/Ita 2045/4095 ens
(123/255 x 16)
READ/WRITE MIPS V
I6 " - vss
mm M/ OUT nzmsm cum
16 ans kt
om our
A----------- "
w aumn
TL/D/9617-1
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g Connection Diagrams
'si Dual-In-Line Package (N) Pin Names
E , , CS Chip Select
S cs- 1 a ‘Vcc SK Serial Data Clock
9, SK--? 7-NC DI s ialDatal t
8 m_ 3 6 -rlo ena a npu
E m_ 4 5 -GND DO Serial Data Output
a GND Ground
TLtD/96t7-2
Top View Vcc Power Supply
See NS Package Number NOBE
Ordering Information
Commercial Temp. Range (tt'C to + 70°C)
Order Number
NMC93C56N/NMC93C66N
NMC93C56M/NMC93C66M
Extended Temp. Range (- 40"C to + 85°C)
Order Number
NMC93C56EN/NMC93C66EN
NMC93C56EM/NMC93C66EM
Military Temp. Range (- ssvc to + 125°C)
Order Number
NMC93C56MN/NMC93C66MN
NMC93C56MM/NMC93C66MM
SO Package (M)
NC- 1 14 -Nc
cs- 2 15 -a
Sk- 3 12 --Nt7
NC-' 4 tt -NC
Dl- 5 10 -Nc
Do- 6 , -Grlt)
NC--? -rl0
TL/D/9617-3
Top View
See NS Package Number M14A
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Absolute Maximum Ratings (Note 1) Operating Conditions
If Mllltary/Aerospace speclfled devices are required, Ambient Operating Temperature
please contact the National Semiconductor Sakes NMC93C56/NMC93C66 0''C to + 1ty'C
OffltttuDlattittutttrtt for availability and sperrifittatlontt. NMC93C56E/NM093C66E -40'C to + 85°C
Ambient Storage Temperature - 65''C to + 1 50''C NhfP3f56M/NMc93c66M o o
All Input or Output Voltages + 6.5V to - 0.3V (MIL Temp.) - 55 C to + 125 C
Lead Temp. (Soldering, 10 sec.) + 300°C
ESD Rating 2000V
DC and AC Electrical Characteristics Vcc = 5V i10% (unless otherwise specified)
Symbol Parameter Part Number Conditions Min Max Units
ICC, Operating Current NMC93C56/NMC93C66 cs = VIH, SK = 1 MHz 2
CMOS Input Levels NMC93C56E/NMC93C66E SK = 0.5 MHz 2 mA
NMC93C56M/NMC93C66M* SK = 0.5 MHz 2
'CCZ Operating Current NMC93C56/NMC93C66 GS = VIH- SK = 1 MHz 3
TTL Input Levels NMC93C56E/NMC93C66E SK = 0.5 MHz 3 mA
NMC93C56M/NMC93C66M SK = 0.5 MHz 4
'CCS Standby Current NMC93C56/NMC93C66 cs = 0V 50
NMC93C56E/NMC93C66E 100 pA
NMC93C56M/NMC93C66M 100
lit. Input Leakage NMC93C56/NMG93C66 " = 0V to Vcc - 2.5 2.5 A
NMC93C56E/NMC93C66E - 10 10 ”A
NMC93C56M/NMC93C66M - 10 10 "
IOL Output Leakage NMC93C56/NMC93C66 VIN = 0V to Vcc -2.5 2.5 A
NMC93C56E/NMC93C66E - 10 IO _ I
NMC93C56M/NMC93C66M -10 10 "
VIL Input Low Voltage - 0.1 0.8 V
VIH Input High Voltage 2 Vcc + 1 V
VOL1 Output Low NMC93CS56/NMC93C566 IOL = 2.1 mA 0.4
Voltage NMC93CS56E/NMC93C566E IOL = 2.1 mA 0.4 V
NMC93CS56M/NMC93C566M IOL = 1.8 mA 0.4
Vom Output High 'OH = 400 p.A
Voltage
V0L2 Output Low Voltage IOL = 10 psA 0.2 V
V0H2 Output High Voltage km = --10 FA Vcc - 0.2 V
fSK SK Clock Frequency NMG93C56/NMC93C66 0 1
NMC93C56E/NMC93C66E 0 0.5 MHz
NMC93C56M/ NMCQSCBBM 0 0.5
tSKH SK High Time NMC93C56/NMC93C66 (Note 2) 250
NM093C56E/NMC93C66E (Note 3) 500 ns
NMC93C56M/NMC93C66M (Note 3) 500
tskL SK Low Time NMC93C56/NMC93C68 (Note 2) 250
NMC93056E/NMC93066E (Note 3) 500 ns
NMC93C56M/NMC93C66M (Note 3) 500
tcs Minimum CS NMC93C56/NMC93C66 (Note 4) 250
Low Time NMC93C56E/NMC93C66E (Note 5) 500 ns
NMC93C56M/NMC93C66M (Note 5) 500
toss CS Setup Time NMC93C56/NMC93C66 Relative to SK 50
NMC93C56E/NMC93C66E 100 ns
NMC93C56M/NMC93C66M 100
'Nolc: Throughout this table "M" re1ers to temperatuve range (- 55% to F 125''C), tttat package type.
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990863WN/950863WN
9, DC and AC Electrical Characteristics VCC = 5V :2 10% (unless otherwise specified) (Continued)
8 Symbol Parameter Part Number Condltlons Mln Max Units
, trys DI Setup Time NMC93C56/NMC93C66 Relative to SK 100
a NMC93C56E/NMC93C66E 200 ns
3 NMC93C56M/NMC93C66M 200
i?, tCSH CS Hold Time Relative to SK 0 ns
E ttNH DI Hold Time NMC93C56/NMC93C66 Relative to SK 100
Z NMC93C56E/NMC93C66E 200 ns
NMC93C56M/NMC93C66M 200
tpm Output Delay to "1 '' NMC93C56/NMC93C66 AC Test 500
NMC93C56E/NMC93C66E 1000 ns
NMC93C56M/NMC93C66M 1000
tpDo Output Delay to "o" NMC93C56/NMC93G66 AC Test 500
NMC93C56E/NMC93C66E 1000 ns
NMC93C56M/NMC93C66M 1000
tsv cs to Status Valid NMC93C56/NMC93C66 AC Test 500
NMC93C56E/NMC93C66E 1000 ns
NMC93C56M/NMC93C66M 1000
top CS to DO in NM093C56/NMC93C66 AC Test 100
TRl-STATE® NMC93C56E/NMC93C66E CS = " 200 ns
NMC93C56M/ NMC93G66M 200
twp Write Cycle Time 10 ms
Note 1: Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections tat the specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note 2: The SK 1requency specification for Commercial parts specifies a minimum SK clock period of 1 "s, therefore in an SK clock cycte tstar+ tst must be
greater than or equal to 1 us. For example it tau. = 250 us then the minimum gm -- 750 ns in order to meet the SK frequency specification.
Note & The SK frequency spatritication for Extended Temperature and Military parts specifies a minimum SK clock period of 2 M, therefore in an SK clock cycle
ttyo, + tSKL must be greater than or equal to 2 us. For example, if the 'SKL = 500 ns then the minimum 13m = 1.5 ps in order to meet the SK frequency
specmtation,
Note 4: For Commercial parts CS must be brought low for a minimum of 250 ns (tcs) between consecutive instruction cycles,
Note 5: For Extended Temperature and Military parts CS must be brought low tor a minimum of 500 ns tics) between consecutive instruction cycles.
Note 6: This parameter is periodically sampled and not 100% tested,
Capacitance (Note 6) AC Test Conditions
TA = 25°Cf = 1 MHz Output Load 1 TTL Gate and CL -- 100 pF
Symbol Test Typ Max Units Input Pulse Levels 0.4V to 2.4V
. Timin Measurement Reference Level
Cour Output Capacitance 5 pF lnpgt 1V and 2V
Cm Input Capacitance 5 pF Output 0.8V and 2V
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Functional Description
The NM093056 and NMC93C66 have 7 instructions as de-
scribed below. Note that the MSB of any instruction is a "I''
and is viewed as a start bit in the interface sequence. The
next 10-bits carry the op code and the 8-bit address for
register selection.
Read (READ):
The Read (READ) instruction outputs serial data on the DO
pin. After a READ instruction is received, the instruction and
address are decoded. followed by data transfer from the
selected memory register into a 16-bit serial-out shift regis-
ter. A dummy bit (logical 0) precedes the 16-bit data output
string. Output data changes are initiated by a low to high
transition of the SK clock.
Erase/Write Enable (EWEN):
When Vcc is applied to the part, it powers up in the Erase/
Write Disable (EWDS) state. Therefore, all programming
modes must be preceded by an Erase/Write Enable
(EWEN) instruction. Once an Erase/Write Enable instruc-
tion is executed, programming remains enabled until an
Erase/Write Disable (EWDS) instruction is executed or Vcc
is removed from the part.
Erase (ERASE):
The ERASE instruction will program all bits in the specified
register to the logical 'I' state. CS is brought low following
the loading of the last address bit. This falling edge of the
CS pin initiates the seIf-timed programming cycle.
The DO pin indicates the READY/BUSY status of the chip if
cs is brought high after a minimum of 250 ns (tcs).
DO = logical 'ty indicates that programming is still in prog-
ress. DO = logical 'I' indicates that the register, at the
address specified in the instruction, has been erased, and
the part is ready for another instruction.
Write (WRITE):
The Write (WRITE) instruction is followed by 16 bits of data
to be written into the specified address, After the last bit of
data is put on the data-in (DI) pin, CS must be brought low
before the next rising edge of the SK clock. This falling edge
of CS initiates the self-timtad programming cycle. The DO
pin indicates the READY/BUSY status of the chip if CS is
brought high after a minimum of 250 ns (tcs). DO = logical
0 indicates that programming is still in progress. DO = logi-
cal 1 indicates that the register at the address specified in
the instruction has been written with the data pattern speci-
fied in the instruction and the part is ready for another in-
struction.
Erase All (ERAL):
The ERAL instruction will simultaneously program all regis-
ters in the memory array and set each bit to the logical 'I'
state. The Erase All cycle is identical to the ERASE cycle
except for the different op-code. As in the ERASE mode,
the DO pin indicates the READY/BUSY status of the chip if
CS is brought high after a minimum of 250 ns (tog).
Write All (WRAL):
The (WRAL) instruction will simultaneously program all reg-
isters with the data pattern specified in the instruction. As in
the WRITE mode, the DO pin indicates the READY/BUSY
status of the chip if CS is brought high after a minimum of
250 ns (tcs).
Erase/Write Disable (EWDS):
To protect against accidental data disturb, the Erase/Write
Disable (EWDS) instruction disables all programming rhodes
and should follow all programming operations. Execution of
a READ instruction is independent of both the EWEN and
EWDS instructions.
Instruction Set for the NMC93056 and NMC93C66
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Instruction SB Op Code Address Data Comments
READ 1 10 A7-.A0 Reads data stored in memory.
EWEN 1 00 11XXXXXX Write enable must precede all programming modes.
ERASE 1 1 1 A7-AO Erase register A7A6A5A4A3A2A1A0.
ERAL 1 00 10XXXXXX Erases all registers.
WRITE 1 01 A7-A0 DI 5- DO Writes register if address is unprotected.
WRAL 1 00 01 XXXXXX D15-Do Writes all registers. Valid only when Protect Register
is cleared.
EWDS 1 00 OOXXXXXX Disables all programming instructions.
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990860WN/990860WN
Timing Diagrams
Synchronous Data Tlmlng
NMCQ3C56/NMC93066
DI hr;
D0 READ
oo (PROGRAM) VOL STATUS VALID
TLftV9617-4
'This is the minimum SK period (Note 2).
" " i , ,
fit -I' It L
cs/ "ty"
'n n n
‘11 u "
s1fkf)ti'1f2fitf,ir-
TL/D/9617-5
'Address bit Ar becomes a "don't care" for NMC93C66.
cs/ " "tty""-"-"-"-
surlflflfLrlfLrLf1rlflflfLf1flfL
01 1 0 0 I 1 ... X
TL/D/9617-6
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Timing Diagrams (Continued)
TL/D/9617-r
WRITE:
D0 " n BUSY READY
TL/D/96t7-8
'Address bit Ar becomes a "don't care" for NMC93C56.
00 Ag I' BUSY RWY
TL/D/ 961 7-9
QSOEGOWN/QSOSBOWN
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Timing Diagrams (Continued)
ERASE:
" -r'u""LrLrtrLrLr"Lt'LrLt'LrLr1g""Lr"LrLrt.
y, mi"cs
cs yr CHECK smus STANDBY
NMC93C56/NMC93066
on_/1 1 1‘(A1XA5XA5)G~D( "N rr rr
"" -/ -ts'v' -A cat,,,
oo m-SWE ff 5'r BUSY READY tau""-'''"
TL/D/9617-10
SK -rLrLrLr"LrLrLrLrLru'"urt,rtfLrLrtrL.
cs ./ tNCtht smus STANDBY
Ol 1 0 0 I 0 . rr
l A JJ t
--tiv' -A - 1H
TRI-STATE £2 ausv READY ae2w
-f/ryr
TL/D/9617-11
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This datasheet has been :
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Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
corp/docs/irwestor_relations/Pr_09_23_201 1_national_semiconductor.html
This file is the datasheet for the following electronic components:
NM93C56MN - product/nm93056mn?HQS=TI-nuIl-nu|l-dscatalog-df-pf—nulI-wwe
NMC93C56 - product/nm093056?HQS=T|-nu||-nu|I-dscataIog-df-pf-null-wwe
NM93C66N - product/nm93c66n?HQS=T|-nu|I-nu|I-dscatalog-df—pf—nulI-wwe
93C56 - product/93c56?HQS=TI—nu|I—nu|I-dscataIog-df-pf-null-wwe
NM93C66MN - product/nm93066mn?HQS=T|—nuIl-nu|l-dscatalog-df-pf—nulI-wwe
NM93C66MM - product/nm93066mm?HQS=T|-nu||-nu|I-dscatalog-df-pf-nulI-wwe
NM93C66M - product/nm93066m?HQS=T|-nu|I-nulI-dscatalog-df-pf-nuII—wwe
NM93C66EN - product/nm93c66en?HQS=T|-nu|I-nulI-dscatalog-df-pf-nulI-wwe
NM93C66EM - product/nm93066em?HQS=T|-nu||-nu|l-dscataIog-df-pf-null-wwe
NM93C56N - product/nm93c56n?HQS=T|-nu|I-nu|I-dscatalog-df—pf—nulI-wwe
NM93C56MM - product/nm93056mm?HQS=T|-nu|I-nu|I-dscatalog-df-pf-nulI-wwe
NM93C56M - product/nm93c56m?HQS=T|—nu||-nu|I-dscataIog-df-pf-null-wwe
NM93C56EN - product/nm93c56en?HQS=T|-nu|I-null-dscataIog-df-pf-null-wwe
NM93C56EM - product/nm93056em?HQS=T|-nu|I-null-dscataIog-df-pf-null-wwe
