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9301
1-of-10 Line Decoder
TL/F/6601
9301/DM9301
1-of-10
Decoders
June 1989
9301/DM9301
1-of-10 Decoders
General Description
These BCD-to-decimal decoders consistof eight inverters
and ten4-inputNAND gates.The inverters areconnectedin
pairsto make BCD input data availablefor decodingbythe
NAND gates.Full decodingof valid input logic ensuresthat
all outputs remain ‘‘OFF’’forall invalid input conditions.
Thesecircuits provide familiar TTL inputsand outputs which
are compatibleforusewith otherTTLand DTL circuits.DC
noise marginsare typically1Vand power dissipationis typi-
cally 125 mW. The diode-clamped, buffered inputs repre-
sent onlyone normalized Series 54/74 load.
Features Direct replacementfor Signetics 8252 Diode-clamped inputsAll outputsare highfor invalid BCD input conditions Typical power dissipation 125mW Typical propagation delay20ns
Connection Diagram
Dual-In-Line Package
TL/F/6601–1
Order Number9301DMQB, 9301FMQBor DM9301N
SeeNS Package Number J16A, N16Eor W16A
Function Table
No. BCD Inputs Decimal OutputsCBA 0123456789 LLLLL HHHHHHHHH LLL HHLH HHHHHHH LLHLHHL HHHHHHH LL HHHHHLH HHHHH LHLLH HHHL HHHHH LHL HHHHHHLH HHH LH HLHHHHH HLHHH L HHHHHHHHHHLHH HLLLH HHHHHHHLH HLL HHHHHHHHHHL HLHLH HHHHHHHHH HL HHHHHHHHHHHH HHLLH HHHHHHHHH HHL HHHHHHHHHHH H HHLH HHHHHHHHH H HHHHHHHHHHHHH
C1995National SemiconductorCorporation RRD-B30M105/PrintedinU.S.A.
