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9300-93-00
4-Bit Positive-Edge-Triggered Parallel or Serial Access Shift Register
TL/F/6600
9300/DM9300
4-Bit
Parallel-Access
Shift
Register
June 1989
9300/DM9300 4-Bit Parallel-Access Shift Register
General Description
The 9300 4-bit registers feature parallel inputs, parallelout-
puts,JK serial inputs, shift/load control input,anda direct
overridingclear.The registers have twomodesof operation:
parallel (broadside) load and shift(in directionQA toward
QD).
Parallel loadingis accomplishedby applyingthefourbitsof
dataand takingthe shift/load control inputlow.The datais
loaded intothe associatedflip-flops,and appearsat theout-
puts afterthe positive transitionofthe clock input. During
loading, serial data flowis inhibited.
Shiftingis accomplished synchronously whenthe shift/load
control inputis high. Serial dataforthis modeis enteredat
theJK inputs. These inputs permitthefirst stageto perform
asaJK,Dor T-type flip-flopas showninthe function table.
These shift registersare fully compatible with most other
TTL and DTL families.All inputs, includingthe clock,are
bufferedto lowerthe drive requirementstoone normalized
Series 54/74 load.
Features Fully buffered inputs Direct overriding clear Synchronous parallel load Parallel inputsand outputs from each flip-flop Positive edge-triggered clockingJandK inputstofirst stage Typical shift frequencyÐ39 MHz
Connection Diagram
Dual-In-LinePackage
TL/F/6600–1
OrderNumber9300DMQB,
9300FMQBor DM9300N
SeeNS Package Number
J16A,N16EorW16A
Function Table
Inputs Outputs
Clear Shift/ Clock Serial Parallel QA QB QC QD QDLoad JK P0 P1 P2 P3 X X X X XXXX L L L L H u XX a b c d a b c d d H L X X XXXX QA0 QB0 QC0 QD0 QD0 u L H XXXX QA0 QA0 QBn QCn QCn u L L XXXX L QAn QBn QCn QCn u H H XXXX H QAn QBn QCn QCn u H L XXXX QAn QAn QBn QBn QCneHigh Level (SteadyState)eLow Level (SteadyState)e Don’tCaree Transitionfrom low-to-highlevel
a,b,c,d,eThelevelof steadystateinputatP0,P1,P2,orP3 respectively.
QA0,QB0,QC0,QD0eThelevel ofQA,QB,QC,orQD, respectively beforethe indicated steadystate inputconditionswere established.
QAn,QBn,QCneThe levelof QA,QB,QC, respectively, before themost recentu transitionofthe clock.
C1995National SemiconductorCorporation RRD-B30M105/PrintedinU.S.A.
