SN54HC11J ,Triple 3-Input Positive-AND Gatesmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN54HC125J ,Quadruple Bus Buffer Gates With 3-State OutputsLogic Diagram (Positive Logic)1 101OE 3OE2 3 9 81A 1Y 3A 3Y4 132OE 4OE5 6 12 112A 2Y 4A 4YPin numbe ..
SN54HC125J ,Quadruple Bus Buffer Gates With 3-State OutputsMaximum Ratings(1)over operating free-air temperature range (unless otherwise noted)MIN MAX UNITV S ..
SN54HC126J ,Quadruple Bus Buffer Gates With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN54HC132J ,Quadruple Positive-NAND Gates With Schmitt-trigger InputsLogic Diagram (Positive Logic)AYB1An IMPORTANT NOTICE at the end of this data sheet addresses avail ..
SN54HC138J ,3-Line To 8-Line Decoders/DemultiplexersFeatures 3 DescriptionThe SNx4HC138 devices are designed to be used in1• Targeted Specifically for ..
SN74F241N ,Octal Buffers/Drivers With 3-State Outputslogic diagram (positive logic)111OE1OE EN2 18 1821Y11A1 1Y11A14 161A2 1Y26 14161A3 1Y3 41Y21A28 121 ..
SN74F241NSR ,Octal Buffers/Drivers With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only andfunctio ..
SN74F241NSR ,Octal Buffers/Drivers With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74F243DR ,Quad bus transceivers 14-SOIC 0 to 70
SN74F243N ,Quad bus transceivers 14-PDIP 0 to 70
SN74F243N ,Quad bus transceivers 14-PDIP 0 to 70
8408801EA-SN54HC112J
Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset
±4-mA Output Drive at 5 V
Low Input Current of 1 µA Maxdescription/ordering informationThe ’HC112 devices contain two independent J-K
negative-edge-triggered flip-flops. A low level at
the preset (PRE) or clear (CLR) inputs sets or
resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive
(high), data at the J and K inputs meeting the
setup time requirements are transferred to the
outputs on the negative-going edge of the clock
(CLK) pulse. Clock triggering occurs at a voltage
level and is not directly related to the fall time of the
CLK pulse. Following the hold-time interval, data
at the J and K inputs may be changed without
affecting the levels at the outputs. These versatile
flip-flops perform as toggle flip-flops by tying J and
K high.
ORDERING INFORMATION†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
2CLR
2CLK
1PRE1CLKNC1CLR
GND
SN54HC112... FK PACKAGE
(TOP VIEW)NC − No internal connection
1PRE
GND
2CLR
2CLK
2PRE
2PRE
