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8169
DIGITAL AUDIO PROCESSOR WITH MULTICHANNEL DDX⑩
STA304A STA304AEND TO END DIGITAL AUDIO
INTEGRATED SOLUTION · DSP Functions:
- DIGITAL VOLUME CONTROL
- SOFT MUTE
- BASS and TREBLE
- PARAMETRIC EQ PER CHANNEL
- BASS MANAGEMENT FOR SUBWOOFER
- AUTO MUTE ON ZERO INPUT DETECTION 4+1 DIRECT DIGITAL AMPLIFICATION
(DDX™) OUTPUT CHANNELs 6 CHANNELs PROGRAMMABLE SERIAL
OUTPUT INTERFACE (by default I2S) 4 CHANNELs PROGRAMMABLE SERIAL
INPUT INTERFACE (by default I2S) STEREO S/PDIF INPUT INTERFACE Intel AC'97 LINK (rev. 2.1) INPUT INTERFACE
FOR AUDIO AND CONTROL ON CHIP AUTOMATIC INPUT SAMPLING
FREQUENCY DETECTION 100 dB SNR SAMPLE RATE CONVERTER
(1KHz SINUSOIDAL INPUT)I2 C CONTROL BUS LOW POWER 3.3V CMOS TECHNOLOGY EMBEDDED PLL FOR INTERNAL CLOCK
GENERATION (1024x48 kHz = 49.152 MHz) 6.144 MHz EXTERNAL INPUT CLOCK OR
BUILT-IN INDUSTRY STANDARD XTAL
OSCILLATOR VARIABLE DIGITAL GAIN UP TO 24dB
(0.75dB STEP)
1.0 DESCRIPTIONThe STA304A Digital Audio Processor is a single
chip device implementing end to end digital solution
for audio application. In conjunction with STA500
power bridge it gives the full digital DSP-to-power
high quality chain with no need for audio Digital-to-
Analog converters between DSP and power stage.
PRODUCT PREVIEWDIGITAL AUDIO PROCESSOR WITH MULTICHANNEL DDX™
STA304A 2/30
1.0 DESCRIPTION (continued)The device supports two main configurations as far as input sources: AC'97 input or IIS/SPDIF input: selection
is made via a dedicated pin (AC97_MODE pin). The AC`97 can be configured to work in two different ways:
'Full Compliant' mode and 'Proprietary' mode which enables more features. The selection of the operating mode
is done via a specific bit in a Vendor Reserved register (see bit 0: AC97_FC_mode in the CRA register, address
5Ah).
The 'Full Compliant' mode is compliant with rev. 2.1 of AC`97 link specifications.
This link can provide up to 6 input audio channels with sampling frequency of 44.1, 48, 88.2, 96 kHz, and the
related controls.
In the IIS/SPDIF mode, a stereo S/PDIF and a 4 channels three-wires programmable serial input interface work
in mutually exclusive way. Two channels with sampling frequency in the continuous range from 32 to 96 kHz
are supported by the S/PDIF interface. Up to four channels with sampling frequency varying continuously from
32kHz up to 96 kHz are supported by the programmable serial interfaces. Among the different configurations,
also the standard IIS protocol is supported.
An embedded high quality sample rate converter (SRC) resamples input data at the internal fixed sampling fre-
quency of 48 kHz for DSP operations.
The DSP is a 20x20 bit core audio processor performing several user controlled parametric algorithms, among
them are dynamic and static equalization, Bass, Treble, Volume control and more. The DSP operates at
49.152MHz (1024xfs). This frequency is generated by an internal PLL with programmable multiplication factor
(x2 or x8).
This device has 5 channels Direct Digital Amplification (DDX™ technology), performing high efficiency class-D
PWM output signals used to drive directly external power bridge stages (STA500).
In addition a 6 channel digital output programmable interface (supporting IIS standard protocol) is embedded
for applications with commercial audio D/A converters. The output sampling frequency is fixed at 48 kHz when
the interface operates as master. In addition an oversampled clock (256xfs or 512xfs) is provided externally for
the D/A converters.
An IIC interface allows full programmability of internal algorithms and control registers via an external controller.
An arbitration logic handles access conflicts to embedded control registers (which may occur as a consequence
of contemporary access to control registers by AClink, IIC and DSP blocks).
Figure 1. DSP data processing
3/30
STA304A
PIN CONNECTION (Top view)
PIN FUNCTION
STA304A 4/30
PIN FUNCTION (continued)
5/30
STA304A
ABSOLUTE MAXIMUM RATINGS
THERMAL DATA
ELECTRICAL CHARACTERISTCS (VDD = 3.3V ± 0.3V; Tamb = 0 to 70 °C; unless otherwise specified)
DC OPERATING CONDITIONS
GENERAL INTERFACE ELECTRICAL CHARACTERISTICSNote 1: The leakage currents are generally very small, < 1na. The value given here is a maximum that can occur after an electrostatic stress
on the pin.
Note 2: Human Body Model
STA304A 6/30
DC ELECTRICAL CHARACTERISTICS
2.0 AC’97 BANK REGISTER OVERVIEWThe AC `97 interface is compliant to ‘Audio Codec `97 – Revision 2.1’ specification, as far as the protocol used.
All the registers described in this specification, including Standard, Vendor Reserved and Extended Audio (AC
`97 2.0) registers, are available in this device, but just relevant registers which are described in paragraph 11
(Register Summary) are implemented.
The ATE mode feature has been implemented for test purpose: for related details refer to the ‘Audio Codec `97
– Revision 2.1’ specification.
2.1 Reading AC `97 RegistersSince the AC`97 register bank has been implemented as a contiguous RAM space (from a DSP point of view)
the content of the RAM itself will be returned as the result of a read operation. This should be followed as a
general rule of thumb but, where not possible, a different approach has been used. Hereby is a list of the reg-
isters, and bits, that do not follow this rule or that have a particular handling: CodecID_0, CodecID_1:
These two bit are respectively bits 14 and 15 of registers 28h (Extended Audio ID) and 3Ch (EWxtended
Modem ID). When a read operation of these registers is performed the returned value is based on the status
of the SA pin: CodecID_0 report the status of SA pin, CodecID_1 always report 0. Other bits of these regis-
ters return the related RAM register contents. Also note that the status of the SA pin is not readable by the
DSP.
•PR4:
The bit 12 of register 26h (Powerdown, ctrl/start) is used to set the AC`97 BIT_CLK and SDATA_IN signal
to a low state. In response to a Warmers the status of this bit is set back to its default 0 value. In response
Note 1: Takes into account 200mV voltage drop in both supply lines
Note 2: X is the source/sinc current under worst case conditions and is reflected in the name of the I/O cell according to the drive capability.
Note 1: Min condition: Vdd = 3.0V, 125°C Min process; Max. condition: Vdd = 3.6 V, -20°C max process.
DIGITAL CHARACTERISTICS-SPDIF RECEIVER (RXP ,RXN pins only, SPDIF - MODE = ANALOG)
7/30
STA304Ato a read request the actual value of this signal is returned, not the RAM content. Due to this fact the relative
RAM register content can be incongruous. Regs. 2Ch, 2Eh and 30h (Audio Sample Rate Control):
These three registers are used to setup the sample rate when the Variable Rate Mode is enabled. In re-
sponse to a read request on one of these registers the actual value returned can be either BB80h or AC44h,
depending on the status of an internal hardware signal; the status of this signal is updated every time a write
operation into one of these register is performed.
For more details regarding a specific bit please refer to the appropriate paragraph.
In order to be as much compliant to the specification as possible two different mode of operation has been in-
troduced. Using the AC97_FC_Mode configuration bit the interface can be configured in Full-Compliant mode
(default): in this mode the value returned as response to a read operation will be properly masked in order to
set ‘reserved’ bits to 0, as from specification. This operation is performed on all registers included the Standard
or Extended Audio address space. If the Full-Compliant mode is not selected the full 16 bits data from the cor-
responding RAM register will be returned with no further manipulation.
If an odd-addressed register reading operation is performed the following scheme is adopted: Slot 0: report valid bit set to 1 for both slot 1 and slot 2 Slot 1 (address):report the odd address Slot 2 (data): report all 0s
2.2 Writing AC `97 RegistersWhen a write operation into one of the available AC`97 registers is performed the entire 16 bits data word is
written into the related RAM register (also reserved bits are passed through). Some bits of some register may
have a corresponding hardware register (Flip-Flop), used to control the internal status of the device: in this case
the value of the FF is also updated every time a write to the related RAM register is performed. The status of
these FF is reverted to their default values after a hardware reset or a software reset (writing to reg. 00h) request
has been issued; as a consequence also the DSP will have to reset the RAM register contents.
Some register may have a different behaviour from the one depicted above. Here is a brief summary of those
registers. Regs. 7Ch and 7Eh:
These are the Vendor ID1 and ID2 registers. Any write request to one of these will be ignored. Regs. 28h:
The ‘Extended Audio ID Register’ is read only. Therefore any write request will be ignored. Regs. 26h:
When a write request is issued the actual data written into the RAM register is ‘xxxxxxxxxxxx1110’, where
‘x’ stands for the incoming data. Regs. 2Ah:
When a write request is issued the actual data written into the RAM register is ‘xxxxxx0111xxxxxx’, where
‘x’ stands for the incoming data. Regs. 32h and 34h:
Any write request into one of these ADC sample rate register will result in the value BB80h written into the
corresponding RAM register.
STA304A 8/30
3.0 I2S INPUT INTERFACE CONFIGURATIONIn order to configure the I2S input interface the Configuration Register B (CRB) can be used. Using the 3
I2SI_Align_x bits one of 6 configuration mode can be selected. Following is a table describing each one of them.
By default standard I2S input interface slave is provided (mode 1 in bits 0,1,2 of register CRB, I2 S_BICK_Pol = 1 and
I2SI_LRCK_Pol = 0 with some register)
3.1 Switching characteristics (10 pf load; Fsm=32 KHz to 96KHz):
Figure 2.
9/30
STA304A
4.0 I2S OUTPUT INTERFACE CONFIGURATIONIn order to configure the I2S output interface the Configuration Register B (CRB) can be used. Using the 3
I2SO_Align_x bits one of 6 configuration mode can be selected. Following is a table describing each one of
them.
By default standard I2S output interface master is provided (mode 1 in bits 8,9,10 of register CRB,
I2SO_BICK_Pol = 1 and I2SO_LRCK_Pol = 0 in the same register)
4.1 Switching characteristics (10 pf load; Fsm=48 KHz):
Figure 3.
STA304A 10/30
5.0 SAMPLE RATE CONVERTERThe sample rate converter resamples the selected input data source in order to send to the DSP an audio
stream with a fixed frequency of 48 KHz. The following picture show the basic architecture.
Figure 4. The selection between X2 Fir interpolation or direct antialiasing Filter on input data is made automatically by the
threshold selector block. If the input sampling frequency (measured by DRLL) is high than the SRC threshold
(see Table 2 section 12.9), the direct antialising filter is selected, otherwise if the input frequency is lower than
the SRC threshold, the X2 FIR filter is added the data path. A 1kHz hysteresis is fixed around the SRC threshold
nominal values of tab. 2 section 12.9, to prevent unstable oscillations. In figure 5 the DRLL lock phase is shown
for 32kHz,44.1kHz, 48kHz and 96kHz input frequency. Note that only after this phase (including the flat part of
the graph) the SRC performances are in spec.
Figure 5. DRLL lock delay
11/30
STA304A
6.0 DAP INPUT STAGEThe device provides 3 mutually exclusive input interfaces: I2S, S/PDIF and AC`97. Hereby is a small description
of the characteristics for each of them and a table showing how to select it.
6.1 Input from I2SUsing this input interface a maximum of 4 channels can be sent to the DSP. As detailed in the related paragraph
this I/F can be configured both as master or slave. When in master the sampling frequency is fixed to 48 KHz
and the SRC can be bypassed using the SRC_Bypass configuration bit (in CRA register). If slave operation is
selected the full range between 32KHz and 96KHz is supported but the SRC must always be in the processing
path (no bypass). In order to select this interface the AC97_MODE pin must be tied to GND and the
I2S_SPDIF_Sel bit must be 0.
6.2 Input from S/PDIFThis interface is compliant with the AES/EBU IEC 958, S/PDIF and EIAJ CP-340/1201 professional and con-
sumer standards. The full range from 32 KHz up to 96 KHz is supported but the SRC bypass option must be
switched off. Using the SPDIF_Mode bit this interface can be configured as digital or analog input. If the analog
mode is selected the line receiver can decode differential as well as single ended inputs. The receiver consists
of a differential input Schmitt Trigger comparator with 50 mV of hysteresis, which prevents noisy signals from
corrupting the data recovered. The minimum input differential voltage is 200 mV.
If the digital mode is selected only the single ended operation is supported; the input signal should be CMOS
compliant.
In order to select this interface the AC97_MODE pin must be tied to GND and the I2S_SPDIF_Sel must be 1.
6.3 Input from AC`97In order to select this interface the AC97_MODE pin must be tied to VDD (I2S_SPDIF_Sel bit ‘is don’t care).
The AC`97 interface can be configured either as primary or secondary device using the external configuration
pin SA.
This interface support 4 sampling frequencies, according to the Variable and Double Rate Audio Codec `97
STA304A 12/30
specification. The following table summarize the slot usage for each one the these frequencies:
* Slots 3, 4 and 6 are always requested. Slots 10, 11 and 12 are requested only when needed.
The following table summarize the different input possibilities:
* In this configuration the BYPASS is always active, regardless SRC_Bypass bit in reg. 5Ah
7.0 PLLIn order to generate the internal 49.152 MHz clock a low-jitter PLL has been included in the device. It can be config-
ured to work either with a multiplication factor of x8 or x2, in order to fit an external frequency reference of 6.144 MHz
or, respectively, 24.576 MHz. This could be useful when the device is configured to work in AC`97 slave mode where
the master clock is 24.576 MHz. To select the multiplication factor the PLL_Factor bit can be used.
Using the PLL_Bypass bit the PLL section can be bypassed, allowing direct connection of the internal clock to
the XTI pin. When this option is selected an external frequency of 49.152 MHz should be provided to the device.
In this condition the PLL is automatically powered-down.
8.0 POWERDOWN MANAGEMENTThe powerdown capability and its logic behaviour is shown in Figure 7 - Powerdown management . Basically
there are three powerdown requests which comes from the extern of the device and will cause a different pow-
erdown condition: External PWDN pin – this signal will turn-off the device which, as a consequence, will enter the power-
down mode (all the device clocks are stopped). The device will exit this state as soon as the PWDN pin
is deasserted. PR5 bit (reg. 26h, bit 13) – Setting this bit will cause a partial powerdown of the device: infact all the clocks
will be suspended, except that used to keep the AC97 and I2C cells alive. In this way, using either of these
input interfaces, it’ll be possible to resume from this state simply resetting the PR5 bit. EAPD bit (reg.26h, bit 15) – The External Amplifier PowerDown bit controls the state of the related pin
(EAPD) which, in turn, is used to switch off the external power chip.
13/30
STA304A
Figure 7. Powerdown managementIn order to avoid any possible pop-noise while switching between the various powerdown modes a particular
masking technique has been adopted to drive the actual controlling signals: as shown in the above figure the 3
powerdown requests will inform the DSP using the related bits in specific registers. After that the DSP performs
a software fade-out of the channels volume and, finally, activates the MUTE flags of the various channels.
The actual controlling lines are the result of a logical AND operation between the relative request signals and
the 4 channel MUTE bits (LR, LFE, SL and SR).
Moreover the external power chip will be turned off (via the EAPD pin) not only as a consequence of an EAPD request,
but also as a consequence of a PR5 or PWDN requests: this solution will prevent any possible noise or glitch.
STA304A 14/30
9.0 BASS MANAGEMENTAND EQ The STA304A has the ability to redirect the sound to the SBW channel and to pass each channel through a 4-
stage cascaded 2nd order IIR filter. With the combination of the DDX gain/compressor (CRA register bits 2-3)
a dynamic EQ can be implemented. Beside that, a special Side-Firing sound can be achieved by enabling this
feature available with the ready made filter topology on the surround channels.
9.1 Bass Redirection
Figure 8. There is an option to redirect each input channel to the SBW output channel. The Scale factor of each channel
should be set with values in the range of 0 (no redirection) to -1 (full redirection). About setting the scaling factors
registers, see paragraph 10.
The redirection is taking place when the bit 0 of the Bass Management Register (add.72h) is set (see section
12.13).
Together with the static EQ option (following section), by setting appropriate filters, a full bass management so-
lution is available.
(*) Note: C and LFE channels are available only with 6 channels AC97 input. In case of 4 channels I2 S, only L, R, LS, RS are
available
9.2 Static EQ
Figure 9.
15/30
STA304AEach channel has a 4 stage cascaded 2nd order filter. The user can set each filter coefficients (see paragraph
10). The coefficient for the Left and Right channels are common, as well as the coefficients for the surrounds.
There is also an input scaling factor for each channel which can be set with values from 0 to -1. The scaling
factor should be set to an appropriate value that will prevent the filter going into saturation.
The Static EQ filters are activated by setting Static EQ and Side Firing register (add. 70h, see section 12.12).
9.3 Surround Side FiringInstead of the normal filters described in the previous section above, a special topology is available for the sur-
round channels:
Figure 10. By designing appropriate filters special surround sound can be achieved for a system which its surround speak-
ers are located next to the front speakers and are rotated to the sides (see picture). The Side firing topology is
enabled by setting Static EQ and Side Firing register (add. 70h, see section 12.12).
Figure 11. Speaker System with Side-Firing positioning
