78Q2123/F ,10/100 Fast Ethernet MicroPHYapplications. The MDI isnegotiation and 10BASE-T signal receptionconnected to the line media via du ..
78SR105HC , 1.5 AMP POSITIVE STEP-DOWN INTEGRATED SWITCHING REGULATOR
78SR112SC , 1.5 AMP POSITIVE STEP-DOWN INTEGRATED SWITCHING REGULATOR
78SR112SC , 1.5 AMP POSITIVE STEP-DOWN INTEGRATED SWITCHING REGULATOR
78SR112SC , 1.5 AMP POSITIVE STEP-DOWN INTEGRATED SWITCHING REGULATOR
78SR174HC , 1.5 AMP POSITIVE STEP-DOWN INTEGRATED SWITCHING REGULATOR
9202-12-10 , Surface Mount Reed Relays
926882-3 , Pins and Sockets standard version
9300 ,4-Bit Positive-Edge-Triggered Parallel or Serial Access Shift RegisterFeaturesParallel loading is accomplished by applying the four bits ofYdata and taking the shift/loa ..
93-00 ,4-Bit Positive-Edge-Triggered Parallel or Serial Access Shift Register9300/DM93004-BitParallel-AccessShiftRegisterJune19899300/DM93004-BitParallel-AccessShiftRegisterGen ..
9301 ,1-of-10 Line DecoderFeaturesYDirect replacement for Signetics 8252These BCD-to-decimal decoders consist of eight invert ..
9308 ,Dual 4-Bit Latchapplications in digital systems. Each latchcontains both an active LOW Master Reset input an active ..
78Q2123-78Q2123/F
10/100 Fast Ethernet MicroPHY
DESCRIPTIONThe78Q2123and78Q2133,MicroPHYTM, arethe
smallest10BASE-T/100BASE-TXFastEthernet
transceiversinthemarket. Theyincludeintegrated
MII,ENDECs,scrambler/descrambler,dual-speed
clockrecovery,andfull-featuredauto-negotiation
functions.The transmitterincludesanon-chippulse-
shaper and a low-powerlinedriver.The receiverhasadaptive equalizerand a baselinerestoration
circuitrequiredforaccurate clockanddatarecovery.
The transceiverinterfacestoCategory-5 unshielded
twistedpair (Cat-5 UTP)cablingfor100BASE-TX
applications,andCategory-3 unshieldedtwistedpair
(Cat-3 UTP)for10BASE-T applications.The MDIis
connectedtothelinemediaviadual 1:1isolation
transformers.Noexternalfilter isrequired. InterfacetheMACisaccomplishedthroughanIEEE-802.3
compliantMedia IndependentInterface(MII). The
78Q2123/78Q2133areintendedtoservethe
embeddedEthernetmarket,tailoredspecificallytothe
needsofgameconsoles,broadbandmodems,
printers,settopboxesandaudio/visualequipment.Itdesignedforlow-powerconsumptionandoperates
from a single3.3Vsupply. The 78Q2123isratedfor
commercialtemperature rangeandthe78Q2133is
ratedforindustrialtemperaturerange.
FEATURESxSmallest10/100PHYavailablex10BASE-T/100BASE-TXIEEE-802.3compliantandRXfunctionsrequiring a dual1:1isolation
transformerinterface tothelinexIntegratedMII,10BASE-T/100BASE-TXENDEC,
100BASE-TXscrambler/descrambler,and
full-featuredauto-negotiationfunctionxFull duplexoperationcapablexAutomaticMDI/MDI-X crossovercorrectionxRegister-programmable transmitamplitudexAutomaticpolaritycorrectionduringauto-
negotiationand10BASE-T signalreceptionxPower-savingandpower-downmodesincluding
transmitterdisablex2 ProgrammableLEDindicators(Linkand
Activitybydefault)xUserprogrammableInterruptpinxPackages: 32-QFN (5x5 mm) and 32-TQFN (5x5mm)xLowPower(~290mW)xSingle3.3 V r0.3VSupplyx78Q2123ratedfor0°C to70°Coperationx78Q2133ratedfor -40°C to85°Coperation
RXC
TXC
RXD
TXD
SMI
MII
100M
10M
Scrambler,
Parallel/Serial
Parallel/Serial,
ManchesterEncoder
MRZ/NRZI
MLT3EncoderCLKGEN
Auto
Auto
MDI-X
Mux
Tx/Rx
Rx/Tx
CarrierSense,
CollisionDetect
CLK
Recovery
10M100M
AdaptiveEQ,
BaselineWanderCorrect,
MLT3Decode,NRZI/NRZ
ClockReferenceLEDs
LinkAct
DATASHEET
78Q2123/78Q2133 MicroPHY™
10/100BASE-TX Transceiver
SimplifyingSystemIntegrationTMPulseShaper
andFilter
ManchesterDecoder,
Parallel/Serial
MII
RegistersSerial/Parallel
Descrambler,
5B/4BDecoder
78Q2123/78Q2133Data SheetDS_21x3_001
TableofContentsFunctionalDescription.......................................................................................................................... 5 1.1 General........................................................................................................................................... 5
1.1.1 PowerManagement............................................................................................................ 5
1.1.2 AnalogBiasingandSupplyRegulation................................................................................ 5
1.1.3 ClockSelection.................................................................................................................... 5
1.1.4 TransmitClockGeneration.................................................................................................. 5
1.1.5 ReceiveSignalQualification................................................................................................ 6
1.1.6 ReceiveClockRecovery..................................................................................................... 6
1.2 100BASE-TX OPERATION........................................................................................................... 6
1.2.1 100BASE-TXTransmit........................................................................................................ 6
1.2.2 100BASE-TXReceive......................................................................................................... 6
1.2.3 PCSBypassMode(Auto-negotiatemustbeoff)................................................................. 6
1.3 10BASE-T OPERATION............................................................................................................... 7
1.3.1 10BASE-T Transmit............................................................................................................ 7
1.3.2 10BASE-T Receive............................................................................................................. 7
1.3.3 PolarityCorrection............................................................................................................... 7
1.3.4 SQETEST.......................................................................................................................... 7
1.3.5 NaturalLoopback................................................................................................................ 7
1.3.6 RepeaterMode................................................................................................................... 7
1.4 Auto-Negotiation............................................................................................................................ 8
1.5 MediaIndependentInterface......................................................................................................... 9
1.5.1 MIITransmitandReceiveOperation................................................................................... 9
1.5.2 StationManagementInterface............................................................................................ 9
1.6 AdditionalFeatures......................................................................................................................10
1.6.1 LEDIndicators...................................................................................................................10
1.6.2 InterruptPin.......................................................................................................................10
1.6.3 AutomaticMDI/MDI-X Configuration................................................................................10
PinDescription.....................................................................................................................................11 2.1 Legend..........................................................................................................................................11
2.2 MII(MediaIndependentInterface)..............................................................................................11
2.3 ControlandStatus.......................................................................................................................12
2.4 MDI(MediaDependentInterface)...............................................................................................12
2.5 Oscillator/Clock............................................................................................................................12
2.6 PowerSupplyandGround...........................................................................................................12
2.7 LEDSignals(ProgrammabilityIsSecondaryRequirement)......................................................13
Register Description...........................................................................................................................14 3.1 MR0:ControlRegister.................................................................................................................15
3.2 MR1:StatusRegister...................................................................................................................16
3.3 MR2:PHYIdentifierRegister 1...................................................................................................17
3.4 MR3:PHYIdentifierRegister 2...................................................................................................17
3.5 MR4:Auto-NegotiationAdvertisementRegister.........................................................................17
3.6 MR5:Auto-NegotiationLinkPartnerAbilityRegister................................................................18
3.7 MR6:Auto-NegotiationExpansionRegister...............................................................................18
3.8 MR16:VendorSpecificRegister.................................................................................................18
3.9 MR17:InterruptControl/StatusRegister.....................................................................................20
3.10 MR18:DiagnosticRegister..........................................................................................................21
3.11 MR19:TransceiverControl.........................................................................................................21
3.12 MR20:Reserved..........................................................................................................................21
3.13 MR21:Reserved..........................................................................................................................21
3.14 MR22:Reserved..........................................................................................................................21
3.15 MR23:LEDConfigurationRegister.............................................................................................22
3.16 MR24:MDI/MDIXControlRegister.............................................................................................22
DS_21x3_00178Q2123/78Q2133Data Sheet
ElectricalSpecifications......................................................................................................................23 4.1 AbsoluteMaximumRatings.........................................................................................................23
4.2 RecommendedOperatingConditions.........................................................................................23
4.3 DCCharacteristics.......................................................................................................................23
4.4 DigitalI/OCharacteristics............................................................................................................24
4.5 DigitalTimingCharacteristics......................................................................................................25
4.5.2 MIITransmitInterface.......................................................................................................25
4.5.3 MIIReceiveInterface.........................................................................................................26
4.6 MDIOInterfaceInputTiming........................................................................................................26
4.6.1 MDIOInterfaceOutputTiming..........................................................................................27
4.6.2 MDIOInterfaceOutputTiming..........................................................................................28
4.6.3 100BASE-TXSystemTiming............................................................................................29
4.6.4 10BASE-T SystemTiming.................................................................................................29
4.7 AnalogElectricalCharacteristics.................................................................................................30
4.7.1 100BASE-TXTransmitter..................................................................................................30
4.7.2 100BASE-TXTransmitter(Informative).............................................................................30
4.7.3 100BASE-TXReceiver......................................................................................................30
4.7.4 10BASE-T Transmitter......................................................................................................31
4.7.5 10BASE-T Transmitter(Informative).................................................................................31
4.7.6 10BASE-T Receiver..........................................................................................................31
4.8 IsolationTransformers.................................................................................................................33
4.9 ReferenceCrystal.........................................................................................................................33
4.9.1 ExternalXTLPOscillatorCharacteristics...........................................................................34
PackagePinDesignations..................................................................................................................35 PackageInformation............................................................................................................................36 Ordering Information...........................................................................................................................36
RevisionHistory...........................................................................................................................................37
78Q2123/78Q2133Data SheetDS_21x3_001
FiguresFigure1:RSTPulseDuration...........................................................................................................................25
Figure2:TransmitInputstothe78Q2123/78Q2133........................................................................................25
Figure3:Receive Outputsfromthe78Q2123/78Q2133.................................................................................26
Figure4:MDIOasanInputtothe78Q2123/78Q2133....................................................................................26
Figure5:MDIOasanOutputtothe78Q2123/78Q2133.............................................................................27
Figure6:MDIOInterface OutputTiming......................................................................................................28
Figure7:ApplicationDiagramfor78Q2123/78Q2133.....................................................................................32
Figure8:ExternalXTLPOscillatorCharacteristics......................................................................................34
Figure9:PackagePinDesignations.................................................................................................................35
DS_21x3_00178Q2123/78Q2133Data Sheet
FunctionalDescription
1.1General
1.1.1PowerManagementThe 78Q2123and78Q2133havethreepowersavingmodes:xChipPower-DownxReceivePower ManagementxTransmitHighImpedanceMode
Chippower-downisactivatedbysettingthePWRDNbitinMIIregisterMR0.11.Whenthechipisin
power-downmode,allon-chipcircuitryisshutoff,andthedevice consumesminimum power.Whilein
thepower-downstate,the78Q2123/78Q2133 stillrespondtomanagementtransactions.
Receivepowermanagement(RXCCmode) isactivatedbysettingtheRXCCbitinMIIregisterMR16.0.thismodeofoperation,theadaptive equalizer,theclockrecoveryphaselockloop(PLL),andallother
receive circuitrywillbepowereddownwhennovalidMLT-3 signalispresentattheUTPreceive line
interface. Assoonas a validsignalisdetected,allcircuitswillautomaticallybepowereduptoresume
normaloperation. Duringthismodeofoperation,RX_CLKwillbeinactivewhenthereisnodatabeing
received. Note thattheRXCCmodeisnotsupportedduring10BASE-T operation.
Transmithighimpedance modeisactivatedbysettingtheTXHIMbitinMIIregisterMR16.12.Inthis
modeofoperation,thetransmitUTPdriversarein a highimpedance stateandTX_CLKistri-stated. A
weakinternalpull-upisenabledonTX_CLK.The receivecircuitryremainsfullyoperational.The default
stateofMR16.12is a logiclowfordisablingthetransmithighimpedance mode.Only a resetconditionwill
automaticallyclear MR16.12.The transmitterisfullyfunctionalwhenMR16.12iscleared. Thisfeatureis
usefulwhenconfiguring a systemforWake-OnLAN(whenthe78Q2123/78Q2133arecoupledwith a
Wake-OnLANcapable MAC).
1.1.2AnalogBiasingandSupplyRegulationThe 78Q2123/78Q2133requirenoexternalcomponenttogenerate on-chipbiasvoltagesandcurrents.
Highaccuracyismaintainedthrough a closed-looptrimmedbiasingnetwork.
On-chipdigitallogicrunsoff aninternalvoltage regulator. Henceonly a single3.3V (r0.3V)supplyis
requiredtopower-upthedevice. The on-chipregulatorisnotaffectedbythepower-downmode.
1.1.3ClockSelectionThe 78Q2123/78Q2133haveanon-chipcrystaloscillatorwhichcanalsobedrivenbyanexternaloscillator.thismodeofoperation, a 25MHzcrystalshouldbeconnectedbetweentheXTLPandXTLNpins.
Alternatively,anexternal25MHzclockinput canbeconnectedtotheXTLP pin.Inthismode ofoperation,
a crystalisnotrequiredandtheXTLNpinmustbetied toground.
1.1.4TransmitClockGenerationThe transmitterusesanon-chipfrequencysynthesizertogeneratethetransmitclock. In 100BASE-TX
operation,thesynthesizermultipliesthereferenceclockby 5 toobtaintheinternal125MHzserialtransmit
clock.In10BASE-T mode,itgeneratesaninternal20MHztransmitclockbymultiplying thereferenceMHzclockby4/5.Thesynthesizerreferenceseitherthelocal25MHzcrystaloscillator, ortheexternally
appliedclock, dependingontheselectedmode ofoperation.
78Q2123/78Q2133Data SheetDS_21x3_001
1.1.5ReceiveSignalQualificationTheintegratedsignalqualifierhasseparatesquelchandunsquelchthresholds.Italsoincludes a built-intimerensurefastandaccuratesignaldetectionandlinenoiserejection.Upondetectionoftwoormorevalid
10BASE-T or100BASE-TXpulsesonthelinereceiveport,signaldetectisindicated.Thesignaldetect
thresholdisthenloweredbyabout40%.Alladaptivecircuitsarereleasedfromtheirinitialstatesandallowedlock ontotheincomingdata.In100BASE-TXoperation,signaldetectisde-assertedwhennosignalis
presentedfor a periodofabout1.2 μs.In10BASE-T operation,signaldetectisde-assertedwheneverno
Manchesterdataisreceived.Ineithercase,thesignaldetectthresholdwillreturntothesquelchedlevel
wheneverthesignaldetectindicationisde-asserted.Signaldetectisalsousedtocontroltheoperationofthe
clock/datarecoverycircuittoassurefastacquisition.
1.1.6ReceiveClockRecovery100BASE-TXmode,the125MHzreceiveclockisextractedusing a digitalDLL-basedloop.Whenno
receivesignalispresent,theCDRisdirectedtolock ontothe125MHztransmitserialclock.Whensignal
detectisasserted,theCDRwillusethereceivedMLT-3 signalastheclockreference.Therecoveredclockis
usedtore-timethedatasignalandforconversionofthedatatoNRZformat.10BASE-T mode,the20MHzreceiveclockisrecovereddigitallyfromtheManchesterdatausing a
DLLlocked tothereferenceclock. WhenManchester-codedpreamblesaredetected,theCDR
immediatelyre-alignsthephase oftheclocktosynchronizewiththeincomingdata.Henceclock
acquisitionisfastandimmediate.
1.2100BASE-TX OPERATION
1.2.1100BASE-TXTransmitThe 78Q2123/78Q2133containallofthenecessarycircuitrytoconvertthetransmitMIIsignaling from a
MACtoanIEEE-802.3compliantdata-streamdrivingCat-5UTPcabling. The internalPCSinterface
maps 4 bitnibblesfromtheMIIto 5 bitcodegroupsasdefinedinTable24-1 ofIEEE-802.3.These 5 bit
codegroupsarethenscrambledandconvertedto a serialstreambeforebeingsenttotheMLT-3 pulse
shapingcircuitryandlinedriver. The pulse-shaper usescurrentmodulationtoproducethedesiredoutput
waveform. Controlledrise/falltimeintheMLT-3 signalisachievedusinganaccuratelycontrolledvoltage
rampgenerator. The linedriverrequiresanexternal1:1isolationtransformertointerfacewiththeline
media. The center-tapoftheprimarysideofthetransformer mustbeconnectedtotheVccsupply(3.3Vr0.3V).
1.2.2100BASE-TXReceiveThe 78Q2123/78Q2133receive a 125MBaudMLT-3 signalthrough a 1:1transformer. The signalthen
goesthrough a combination ofadaptiveoffsetadjustment(baseline wandercorrection)andadaptive
equalization. The effectofthesecircuitsistosensetheamountofdispersionandattenuationcaused by
thecableandtransformer,andrestorethereceivedpulsestologiclevels. The amountofgainand
equalizationappliedtothepulsesvarieswiththedetectedattenuationanddispersionand,therefore,with
thelengthofthecable.The 78Q2123/78Q2133cancompensate forcablelossofupto10dBat16MHz.
Thislossisrepresentedastest_chan_5inAnnex A oftheANSIX3.263:199X. TheequalizedMLT-3 data
signalisbi-directionallyslicedandtheresultingNRZIbit-streamispresentedtotheCDRwhereitis
re-timedanddecodedtoNRZformat.The re-timedserialdatapassesthrough a serial-to-parallel
converter,thendescrambledandalignedinto 5 bitcodegroups. The receivePCSinterface mapsthese
codegroupsto 4 bitdatafortheMIIasoutlinedinTable24-1 inClause24ofIEEE-802.3.
1.2.3PCSBypassMode(Auto-negotiatemustbeoff)The PCSBypassmodeisenteredbysettingregisterbitMR16.1.Inthismodethe78Q2123/78Q2133
acceptscrambled 5 bitcodewordsattheTX_ERandTXD[3:0]pins,TX_ERbeingtheMSBofthedata
input.The 5 bitcodegroupsareconvertedtoMLT-3 signalfortransmission.
DS_21x3_00178Q2123/78Q2133Data Sheet
The receivedMLT-3 signalisconvertedto 5 bitNRZcodegroupsandoutputfromtheRX_ERand
RXD[3:0]pins,RX_ERbeingtheMSBofthedataoutput.The RX_DVandTX_ENpinsareunusedin
PCSBypassmode.
1.310BASE-T OPERATION
1.3.110BASE-T TransmitThe 78Q2123/78Q2133take 4-bitparallelNRZdataviatheMIIinterface andpassesitthrough a parallelserialconverter. The dataisthenpassedthrough a Manchesterencoder,pre-emphasispulse-shaper,
mediafilter,andfinallytothetwisted-pairlinedriver. The pulse-shaper andfilterensuretheoutput
waveformsmeetthevoltagetemplateandspectralcontentrequirementsdetailedinClause14of
IEEE-802.3.Interfacetothetwisted-pairmediaisthrough a center-tapped1:1transformer. Noexternal
filteringisrequired.Duringauto-negotiationand10BASE-T idleperiods,linkpulsesaretransmitted.
The 78Q2123/78Q2133employanonboardtimertopreventtheMACfromcapturing a networkthrough
excessivelylongtransmissions.Whenthistimerexpires,thechipentersthejabberstateand
transmissionishalted.The jabber stateisexitedaftertheMIIgoesidlefor500r250ms.
1.3.210BASE-T ReceiveThe 78Q2123/78Q2133receiveManchester-encoded10BASE-T datathroughthetwistedpair inputsand
re-establisheslogiclevelsthrough a slicerwith a smartsquelchfunction.The slicerautomaticallyadjusts
itslevelafterdetectionofvaliddatawiththeappropriate levels. Data ispassedontotheCDRwherethe
clockisrecovered,andthedataisre-timedanddecoded.Fromthere,dataenterstheserial-to-parallel
converterfortransmissiontotheMACviatheMedia IndependentInterface. Interfacetothetwisted-pair
mediaisthroughanexternal1:1transformer. Polarityinformationisdetectedandcorrectedwithin
internalcircuitry.
1.3.3PolarityCorrectionThe 78Q2123/78Q2133arecapableofeitherautomaticormanualpolarityreversalfor10BASE-T and
auto-negotiationfunctions.RegisterbitsMR16.5andMR16.4controlthisfeature. The defaultis
automaticmodewhereMR16.5islowandMR16.4indicatesifthedetectioncircuitryhasinvertedthe
inputsignal. Toentermanualmode,MR16.5shouldbesethighandMR16.4willthencontrolthesignal
polarity.
1.3.4SQETESTThe 78Q2123/78Q2133supporttheSignalQualityError(SQE)functiondetailedinIEEE-802.3.Atan
intervalof 1Ps aftereachnegative transitionoftheTX_ENpinin10BASE-T mode,theCOLpinwillgo
highfor a periodof 1 Ps. SQEisnotsignaledduringtransmissionaftercollisionisdetected. SQEis
automaticallydisabledwhenrepeatermodeisenabled.Thisfunctioncanbedisabledthroughregisterbit
MR16.11.
1.3.5NaturalLoopbackWhenenabled,wheneverthe78Q2123/78Q2133aretransmittingandnotreceivingonthetwistedpair
media(10BASE-T HalfDuplexmode),dataontheTXD3-0 pinsareloopedbackontotheRXD3-0 pins.
During a collision,datafromtheRXIpinsisroutedtotheRXD3-0 pins.The naturalloopbackfunctionis
enabledthroughregisterbitMR16.10. Thisfeatureisoffbydefault.
1.3.6RepeaterModeWhenregisterbitMR16.15isset,the78Q2123/78Q2133areplacedinrepeatermode. Inthismode,full
duplexoperationisprohibited,CRSrespondsonlytoreceive activityand,in10BASE-T mode,theSQE
testfunctionisdisabled.
78Q2123/78Q2133Data SheetDS_21x3_001
1.4Auto-NegotiationThe 78Q2123/78Q2133supporttheauto-negotiationfunctionsofClause28ofIEEE-802.3for10/100
Mbpsoperationovercopperwiring. Thisfunctioncanbeenabledviaregistersettings.The
auto-negotiationfunctiondefaultstoON andbitMR0.12(ANEGEN) ishighafterreset. Softwarecan
disabletheauto-negotiationfunctionbywritingtobitMR0.12.
The contentsofregisterMR4aresenttothe78Q2123/78Q2133’slinkpartner duringauto-negotiationvia
fastlinkpulsecoding.
The defaultvaluesoftheauto-negotiationregistersaresetasfollows:
Register.BitsFunctionDefaultValue0.13SpeedSelect1 (100 BASETX)
0.12ANEnable1 (enabled)
0.8Duplex1 (fullduplex)
4.8/1.14100BASE-TX
Full Duplex
4.7/1.13100BASE-TX1
4.6/1.1210BASE-T
Full Duplex
4.5/1.1110BASE-T 1
Thesedefaultvaluescanbechanged bywritingdifferentvaluestotheregisters,thenrestarting
auto-negotiation.
Withauto-negotiationenabled,the78Q2123/78Q2133willstartsendingfastlinkpulsesatpoweron,losslinkorupon a commandtorestart.Atthesame time,itwilllookfor either10BASE-T idle,100BASE-TX
idle,orfastlinkpulsesfromitslinkpartner. Ifeitheridlepatternisdetected,the78Q2123/78Q2133
configurethemselvesinhalf-duplexmodeattheappropriate speed.Ifitdetectsfastlinkpulses,it
decodesandanalyzesthelinkcodetransmittedbythelinkpartner.Whenthreeidenticallinkcodewords
arereceived(ignoringtheacknowledgebit)thelinkcodewordisstoredinregisterMR5. Uponreceiving
threemoreidenticallinkcodewords,withtheacknowledge bitset,the78Q2123/78Q2133configure
themselvestothehighestprioritytechnologycommontothetwolinkpartners. Thetechnologypriorities
are,indescendingorder:
100BASE-TX,Full Duplex
100BASE-TX,HalfDuplex
10BASE-T,Full Duplex
10BASE-T,HalfDuplex
Onceauto-negotiationiscomplete,registerbitsMR18.11:10willreflecttheactualspeedandduplexthat
waschosen.auto-negotiationfailstoestablish a linkforanyreason,registerbitMR18.12willreflectthisandauto
negotiationwillrestartfromthebeginning.Writing a ‘1’tobitMR0.9(RANEG)willalso cause
auto-negotiationtorestart.
DS_21x3_00178Q2123/78Q2133Data Sheet
1.5MediaIndependentInterface
1.5.1MIITransmitandReceiveOperationThe MIIinterfaceonthe78Q2123/78Q2133provide independenttransmitandreceivepathsforboth
10Mb/sand100Mb/sdataratesasdescribedinClause22oftheIEEE-802.3standard.
The transmitclock,TX_CLK,providesthetimingreference forthetransfer ofTX_EN,TXD3-0,and
TX_ERsignalsfromtheMACtothe78Q2123/78Q2133.TXD3-0iscapturedon the risingedgeof
TX_CLKwhenTX_ENisasserted.TX_ERisalso capturedontherisingedge ofTX_CLKandis
assertedbytheMACtorequestthatanerrorcodegroupistobetransmitted. TheassertionofTX_ERis
ignoredwhenthe78Q2123/78Q2133areoperatingin10BASE-T mode.
The receive clock,RX_CLK,providesthetimingreferencetotransfer RX_DV,RXD3-0,andRX_ER
signalsfromthe78Q2123/78Q2133totheMAC. RX_DVtransitionssynchronouslywithrespectto
RX_CLKandisassertedwhenthe78Q2123/78Q2133 arepresentingvaliddataonRXD3-0. RX_ERis
assertedandissynchronoustoRX_CLKwhen a codegroupviolationhasbeendetectedinthecurrent
receive packet.
1.5.2StationManagementInterfaceThe stationmanagementinterfaceconsistsofcircuitrywhichimplementstheserialprotocolasdescribedClause22.2.4.4ofIEEE-802.3. A 16-bitshiftregisterreceivesserialdataappliedtotheMDIOpinat
therising-edgeoftheMDCclocksignal.Oncethepreambleisreceived,thestation managementcontrol
logiclooksforthestart-of-frame sequenceand a readorwrite op-code,followedbythePHYADand
REGADfields. The defaultaddressforthe78Q2123/78Q2133is1.For a readoperation,theMDIOport
becomesenabledasanoutputandtheregisterdataisloadedinto a shiftregisterfortransmission.The
78Q2123/78Q2133can workwith a one-bitpreambleratherthanthe32bitsprescribedbyIEEE-802.3.
Thisallowsforfasterprogrammingoftheregisters.If a registerdoesnotexistatanaddressindicatedby
theREGADfieldorifthePHYADfielddoesnotmatchthe78Q2123/78Q2133PHYAD, a readofthe
MDIOportwillreturnallones. For a writeoperation,thedataisshiftedinandloadedintotheappropriate
registerafterthesixteenthdatabithasbeenreceived.Writestoregistersnotsupportedbythe
78Q2123/78Q2133areignored.
WhenthePHYADfieldisallzeros,theStationManagementEntity(STA)isrequesting a broadcastdata
transaction.AllPHYssharingthesameManagementInterfacemustrespondtothisbroadcastrequest.
The 78Q2123/78Q2133willrespondtothebroadcastdatatransaction.
78Q2123/78Q2133Data SheetDS_21x3_001
1.6AdditionalFeatures
1.6.1LEDIndicatorsThere aretwoLEDpinsthatcanbeusedtoindicatevariousstatesofoperationofthe
78Q2123/78Q2133.The functionofthesepinsisprogrammable viatheMR23registerasshowninthe
tablebelow:
LEDStateIndication0 1 = LinkOK(DefaultLED0)
1 1 = RXorTXActivity(DefaultLED1)
2 1 = TXActivity
3 1 = RXActivity
4 1 = Collision
5 1 = 100BASE-TXmode
6 1 = 10BASE-T mode
7 1 = Full Duplex
8 1=LinkOK & Blink = RXorTXActivity
The defaultstatusoftheseLEDsare“LinkOK”forLED0and“RXorTXActivity”forLED1.
1.6.2InterruptPinThe 78Q2123and78Q2133haveanInterruptpin(INTR)thatisassertedwheneveranyoftheeight
interruptbitsofMR17.7:0areset. TheseinterruptbitscanbedisabledviatheMR17.15:8Interrupt
Enablebits. The InterruptPolaritybit,MR16.14,controlstheactiveleveloftheINTRpin.WhentheINTR
pinisnot asserted,thepinisheldin a highimpedancestate.Anexternalpull-uporpull-downresistormayrequiredforusewiththeINTRpin.
1.6.3AutomaticMDI/MDI-X ConfigurationThe 78Q2123and78Q2133implementtheautomaticMDI/MDI-X configurationdetailedinIEEE-802.3
2002. Thisfunctioneliminatestheneedforcrossover cableswhenconnectingtoanotherdevice. When
auto-switchingisenabled,the78Q2123/78Q2133willattempttodetectactivityonitsgivenconfiguration.noactivityisseenfor60ms,thedevicewillswitchtotheotherconfigurationdependingon a random
numbersequence.The initialseedoftherandomnumbergeneratorcanbesetviaMR24.3:0.In
addition,thepartincludesanasynchronousMDIXresetthatvariesfrom1.29secondsto1.57secondsto
ensurelockstepwillnotoccur betweentwodevices.
The 78Q2123and78Q2133willalso allowforauto-switchingwhile thepartisnotinauto-negotiation
mode. The IEEE802.3 specificationwillnotworkinthiscase iftheotherdevice isinauto-negotiation
mode. The 78Q2123and78Q2133defaulttoautoMDIXenabledwith paralleldetection. Registerbits
MR24.6andMR24.7arebothdefaultedto1.The 78Q2123and78Q2133willresolvetheproper
configurationwithin 5 seconds.
DS_21x3_00178Q2123/78Q2133Data Sheet
2 Pin Description
2.1Legend
TypeDescriptionTypeDescriptionA AnalogPinCITTL-levelInput
CIUTTL-levelInputwithPull-upCIOTTL-compatibleBi-directionalPin
CISTTL-levelInputwithSchmittTriggerCOZTristate-able CMOSOutputCMOSOutput
S SupplyG Ground
2.2MII(MediaIndependentInterface)
SignalPinTypeDescriptionTX_CLK15COZTRANSMITCLOCK:TX_CLKis a continuousclock,whichprovides a
timingreferencefortheTX_EN,TX_ERandTXD[3:0]signalsfromthe
MAC. The clockfrequencyis25MHzin100BASE-TXmodeand2.5MHz10BASE-T mode. Thispinistri-statedinisolate modeandtheTXHIM
mode.
TX_EN16CITRANSMITENABLE:TX_ENisassertedbytheMACtoindicate that
validdatafortransmissionispresentontheTXD[3:0]pins.
TXD[3:0][20:17]CITRANSMITDATA: TXD[3:0]receivesdatafromtheMACfortransmission
on a nibblebasis.ThisdataiscapturedontherisingedgeofTX_CLK
whenTX_ENishigh.
TX_ER14CITRANSMITERROR:TX_ERisassertedhighbytheMACtorequestthaterrorcode-groupbetransmittedwhenTX_ENishigh.InPCSbypass
mode,thispinbecomestheMSBofthetransmit 5-bitcodegroup.
CRS22COZCARRIERSENSE:Whenthe78Q2123/78Q2133arenotinrepeater
mode,CRSishighwhenever a non-idleconditionexistsoneitherthe
transmitterorthereceiver.Inrepeatermode,CRSisonlyactivewhen a
non-idleconditionexistsonthereceiver.Thispinistri-statedinisolate
mode.
COL21COZCOLLISION:COLisassertedhighwhen a collisionhasbeendetected on
themedia.In10BASE-T modeCOLisalso usedfortheSQEtestfunction.
Thispinistri-statedinisolate mode.During halfduplexoperation,the
risingedge ofCOLwilloccasionallyoccur upontherisingedge of
TX_CLK.
RX_CLK12COZRECEIVECLOCK:RX_CLKis a continuousclock,whichprovidesa
timingreferencetotheMACfortheRX_DV,RX_ERandRXD[3:0]signals.
The clockfrequencyis25MHzin100BASE-TXmodeand2.5MHzin
10BASE-T mode. Toreducepowerconsumptionin100BASE-TXmode,
the78Q2123/78Q2133 provide anoptionalmode,enabledthrough
MR16.0,inwhichRX_CLKisheldinactive(low) whennoreceive datais
detected. Thispinistri-statedinisolate mode.
RX_DV11COZRECEIVEDATAVALID: RX_DVisassertedhightoindicate thatvalid
dataispresentontheRXD[3:0]pins.In100BASE-TXmode,ittransitions
highwiththefirstnibbleofthepreamble andispulledlowwhenthelast
datanibblehasbeenreceived.In10BASE-T modeittransitionshighwhen
thestart-of-frame delimiter (SFD) isdetected. Thispinistri-statedin
isolate mode.
78Q2123/78Q2133Data SheetDS_21x3_001
RXD[3:0][5:8]COZRECEIVEDATA:ReceiveddataisprovidedtotheMACviaRXD[3:0].
Thesepinsaretri-statedinisolate mode.
RX_ER13COZRECEIVE ERROR:RX_ERisassertedhighwhenanerrorisdetected
during framereception.InPCS bypassmode, thispinbecomestheMSB of
thereceive 5-bitcodegroup.Thispin istri-statedinisolatemode.
MDC2 CISMANAGEMENTDATACLOCK:MDCistheclockusedfortransferring
dataviatheMDIOpin.
MDIO1 CIOMANAGEMENTDATAINPUT/OUTPUT:MDIOis a bi-directionalport
usedtoaccessmanagementregisterswithinthe78Q2123/78Q2133.This
pinrequiresanexternalpull-upresistorasspecifiedinIEEE-802.3.
2.3ControlandStatus
SignalPinTypeDescriptionRST23CISACTIVELOWRESET:Whenpulledlowthepinresetsthechip.The reset
pulsemustbelongenough toguarantee stabilizationofthesupply
voltage andstartupoftheoscillator.RefertotheElectricalSpecifications
fortheresetpulserequirements.Therearetwootherwaystoresetthe
chip:Throughtheinternalpower-on-reset(activatedwhenthechipis
beingpoweredup).ThroughtheMIIregisterbit(MR0.15).
INTR32COZINTERRUPTPIN:Thispinisusedtosignalaninterrupttothemedia
accesscontroller.The pinisheldinthehighimpedance statewhenan
interruptisnotindicated.The pinwillbeforcedhighorlowtosignalan
interruptdependinguponthevalueoftheINPOLbit(MR16.14).The
eventswhichtriggeraninterruptcan beprogrammedviatheInterrupt
ControlRegisterlocatedataddressMR17.
2.4MDI(MediaDependentInterface)
SignalPinTypeDescriptionTXOP,
TXON
30,31A TRANSMITOUTPUTPOSITIVE/NEGATIVE:Transmitterdifferential
outputsforboth10base-T and100base-TX.
RXIP,
RXIN
28,27A RECEIVEINPUTPOSITIVE/NEGATIVE:Receiverdifferentialinputsfor
both10BASE-T and100BASE-TX.
2.5Oscillator/Clock
SignalPinTypeDescriptionXTLP 24A CRYSTALINPUT:Shouldbeconnectedto a 25MHzcrystal. Ifan
externallygeneratedTTLcompatibilityclocksignalisused,thatsignalis
appliedhere.
XTLN 25A CRYSTALOUTPUT: Shouldbeconnectedto a 25MHzcrystal.Whenan
externalclocksourceisbeingused,thispinmustbegrounded.
2.6PowerSupplyandGround
SignalPinTypeDescriptionPWR 9,26S +3.3VDCSUPPLY
GND10,29G GROUND
DS_21x3_00178Q2123/78Q2133Data Sheet
2.7LEDSignals(ProgrammabilityIsSecondaryRequirement)
SignalPinTypeDescriptionLED0 4 COPROGRAMMABLELED.Active low. Defaultstatus:LINKOK.Activeto
indicatelinkwithfarendPHY.
LED1 3 COPROGRAMMABLELED.Active low. Defaultstatus:RXorTXACTIVITY.
Active toindicateTXorRXactivityontheMDI. OtherLEDoptionsselectable viaMR23:
TRANSMIT:ON whenthereis a transmission(normallyOFF).
RECEIVE:ON whenthereis a reception(normallyOFF).
COLLISION:Inhalfduplexmode,thisis a collisionindicatorandturns-ONwhen
a collisionoccurs.Infullduplexmode,thisLEDisheldOFF.
BASE-TX:ON for100BASE-TXconnectionandOFFforother
connections.LEDBTXisOFFduringauto-negotiation.
BASE-T:ON for10BASE-T connectionandOFFforotherconnections.
LEDBTisOFFduringauto-negotiation.
FULLDUPLEX:ON wheninfullduplexmodeandOFFwheninhalf
duplexmode.
LINK/ACT:ON forlink,blinkforactivity.
78Q2123/78Q2133Data SheetDS_21x3_001
Register DescriptionThe 78Q2123/78Q2133implement1316-bitregisters,whichareaccessible viatheMDIOandMDCpins.
The supportedregistersareshownbelowinthefollowingtable. Attemptstoreadunsupportedregisters
willbeignoredandtheMDIOpinwillnotbeenabled asanoutput,asper theIEEE 802.3specification.
All oftheregistersexceptthosethatareuniquetothe78Q2123/78Q2133 willrespondtothebroadcast
PHYADvalueof‘00000’.The registersspecifictothe78Q2123/78Q2133 occupyaddressspace
MR16-24.
AddressSymbolNameDefault(Hex)0 MR0Control(3100)
1 MR1Status(7849)
2 MR2PHYIdentifier 1 000E
3 MR3PHYIdentifier 2 7237
4 MR4Auto-NegotiationAdvertisement(01E1)
5 MR5Auto-NegotiationLinkPartner Ability0000
6 MR6Auto-NegotiationExpansion0000
7 MR7NotImplemented0000
8-14MR8-14Reserved0000MR15NotImplemented0000MR16Vendor Specific(0140)MR17InterruptControl/StatusRegister0000MR18DiagnosticRegister0000MR19TransceiverControl4XXX
20-22MR20-22Reserved0000MR23LEDConfigurationRegister0010MR24MDI/MDIXControlRegister(00C0)
Legend
TypeDescriptionTypeDescriptionR Readable bymanagement.W Writeablebymanagement.Writeablebymanagement.Self
Clearing.Readable bymanagement.
Clearedupon a readoperation.
0/1Defaultvalueuponpowerupor
reset.
DS_21x3_00178Q2123/78Q2133Data Sheet
3.1MR0:ControlRegister
BitSymbolTypeDefaultDescription0.15RESETR/WC0 Reset: Settingthisbitto‘1’resetsthedevice andsetsall
registerstotheir defaultstates. Thisbitisself-clearing.
0.14LOOPBKR/W0 Loopback:Whenthisbitissetto‘1’,inputdataatTXD[3:0]is
outputatRXD[3:0]. Notransmission ofdataonthenetwork
medium occursandreceivedataonthenetworkmediumis
ignored.Bydefault,theloopbacksignalpathencompasses
mostofthedigitalfunctionalblocks. Thisbitallowsfor
diagnostictesting.
0.13SPEEDSLR/W1 SpeedSelection:Thisbitdeterminesthespeedofoperationthe78Q2123/78Q2133.Settingthisbitto‘1’indicates
100Base-TXoperationand a ‘0’ indicates10Base-T mode.
Thisbitwilldefaultto a ‘1’ uponreset.Whenauto-negotiationenabled,thisbitwillnotbewritableandwillhavenoeffectthe78Q2123/78Q2133.Ifauto-negotiationisnotenabled,
thisbitmaybewrittentoforce manual configuration.
0.12ANEGENR/W1 Auto-NegotiationEnable: The auto-negotiationprocessis
enabledbysettingthisbitto‘1’.Thisbitwilldefaultto‘1’.If
thisbitisclearedto‘0’,manualspeedandduplexmode
selectionisaccomplishedthroughbits0.13 (SPEEDSL)and
0.8 (DUPLEX)oftheControlRegister.
0.11PWRDNR/W0 Power-Down: The devicemaybeplacedin a lowpower
consumptionstatebysettingthisbitto‘1’.Whileinthepower-
downstate,thedevice willstillrespondtomanagement
transactions.
0.10ISOR/W0Isolate:Whensetto‘1’,thedevice willpresentahigh-
impedanceonitsMIIoutputpins.Thisallowsformultiple
PHY’stobeattachedtothesame MIIinterface. Whenthe
device isisolated,itstillrespondstomanagement
transactions.
0.9RANEGR/WC0 RestartAuto-Negotiation: Normally,theAuto-Negotiation
processisstartedatpowerup. The processcanberestartedsettingthisbitto‘1’.Thisbitisself-clearing.
0.8DUPLEXR/W1 DuplexMode: Thisbitdetermineswhetherthedevice
supportsfull- duplexorhalf-duplex. A ‘1’indicatesfull-duplex
operationand a ‘0’ indicateshalf-duplex. Thisbitwilldefault‘1’ uponreset.Whenauto-negotiationisenabled,thisbit
willnotbewritableandwillhavenoeffectonthe
78Q2123/78Q2133.Ifauto-negotiationisnotenabled,thisbit
maybewrittentoforce manual configuration.
0.7COLTR/W0 CollisionTest:Whenthisbitissetto‘1’,thedevice willassert
theCOLsignalinresponsetotheassertionoftheTX_EN
signal. CollisiontestisdisabledifthePCSBPbit,MR16.1,is
high. Collisiontestcan beactivatedregardlessoftheduplex
modeofoperation.
0.6:0RSVDR 0 Reserved
78Q2123/78Q2133Data SheetDS_21x3_001
3.2MR1:StatusRegisterBits1.15through1.11reflecttheabilityofthe78Q2123/78Q2133.Theydonotreflectanyabilitychanges
madeviatheMIIManagementInterfacetobits0.13 (SPEEDSL) , 0.12 (ANEGEN) and0.8 (DUPLEX)in
theControlRegister.
BitSymbolTypeDefaultDescription1.15100T4R 0 100BASE-T4Ability: Reads‘0’toindicate the
78Q2123/78Q2133donotsupport100Base-T4mode.
1.14100X_FR 1 100BASE-TXFull DuplexAbility:
0 : Notable
1 : Able
1.13100X_HR 1 100BASE-TXHalfDuplexAbility:
0 : Notable
1 : Able
1.1210T_FR 1 10BASE-T Full DuplexAbility:
0 : Notable
1 : Able
1.1110T_HR 1 10BASE-T HalfDuplexAbility:
0 : Notable
1 : Able
1.10100T2_FR 0 100BASE-T2Full DuplexAbility:Reads‘0’ toindicate the
78Q2123/78Q2133donotsupport100Base-T2fullduplex
mode.
1.9100T2_HR 0 100BASE-T2HalfDuplexAbility:Reads‘0’ toindicatethe
78Q2123/78Q2133donotsupport100Base-T2fullduplex
mode.
1.8EXTSR 0 ExtendedStatusInformationAvailability: Reads‘0’ toindicate
the78Q2123/78Q2133 donotsupportExtendedStatus
informationonMR15.
1.7RSVDR 0 Reserved
1.6MFPSR 0 ManagementFramePreambleSuppressionSupport: A “0”
indicatesthatthe78Q2123/78Q2133canreadmanagement
frameswith a preamble.
1.5ANEGCR 0 Auto-NegotiationComplete: A logiconeindicatesthatthe
Auto-Negotiationprocesshasbeencompleted,andthatthe
contentsofregistersMR4,5,6arevalid.
1.4RFAULTRC0 Remote Fault: A logiconeindicatesthat a remote fault
conditionhasbeendetectedanditremainssetuntilitis
cleared. Thisbitcanonlybeclearedbyreadingthisregister
(MR1) viathemanagementinterface.
1.3ANEGAR (1)Auto-NegotiationAbility:Whenset,thisbitindicatesthe
device’sabilitytoperformAuto-Negotiation. The valueofthis
bitisdeterminedbytheANEGENbit(MR0.12).
1.2LINKR 0 LinkStatus: A logiconeindicatesthat a validlinkhasbeen
established.Ifthelinkstatusshouldtransition fromanOK
statusto a NOT-OKstatus,thisbitwillbecomeclearedand
remainscleareduntilitisread.
1.1JABRC0 Jabber Detect: In 10Base-T mode,thisbitissetduring a
jabber event.Afterajabber event,thebitremainssetuntil
DS_21x3_00178Q2123/78Q2133Data Sheet clearedbyareadoperation.
1.0EXTDR 1 ExtendedCapability: Reads’1’toindicatethe
78Q2123/78Q2133provide anextendedregisterset(MR2
andbeyond).
3.3MR2:PHYIdentifierRegister 1
BitSymbolTypeValueDescription2.15:0OUI[23:6]R 000EhOrganizationallyUniqueIdentifier: Thisvalueis00-C0-39for
TeridianSemiconductor Corporation. Thisregistercontainsthe
first16-bitsoftheidentifier.
3.4MR3:PHYIdentifierRegister 2
BitSymbolTypeValueDescription3.15:10OUI[5:0]R 1ChOrganizationallyUniqueIdentifier: Remaining 6 bitsofthe
OUI.
3.9:4MNR 23hModelNumber: The last 2 digitsofthemodelnumber
78Q2123areencodedinto the 6 bitsforboth78Q2123and
78Q2133.
3.3:0RNR 07hRevisionNumber: The value‘0111’correspondstothe
seventhrevisionofthesilicon.
3.5MR4:Auto-NegotiationAdvertisementRegister
BitSymbolTypeDefaultDescription4.15NPR 0 NextPage: Notsupported.Readslogiczero.
4.14RSVDR 0 Reserved
4.13RFR/W0 Remote Fault:Settingthisbitto‘1’allowsthedevice to
indicatetothelinkpartner a Remote FaultCondition.
4.12A7R 0 Reserved.
4.11A6R/W0 AsymmetricPAUSESupportIndicationforFull DuplexLinks.
Defaultis 0 indicatingnotsupported.IftheMACsupports
AsymmetricPAUSE,thisbitcanbewrittenas1.Writingtothis
registerhasnoeffectuntilauto-negotiationisre-initiated.
4.10A5R 0 PAUSESupportIndicationforFull DuplexLinks.Defaultis 0
indicatingnotsupported.IftheMACsupportsPAUSE,thisbit
canbewrittenas1.Writingtothisregisterhasnoeffectuntil
auto-negotiationisre-initiated
4.9A4R 0 100BASE-T4: The 78Q2123/78Q2133donotsupport
100BASE-T4operation.
4.8A3R/W(1)100BASE-TXFull Duplex:IftheMR1.14bitis‘1’,thisbitwillsetto‘1’uponresetandwillbewriteable.Otherwise,this
bitcannotbesetto‘1’bythemanagement.
4.7A2R/W(1)100BASE-TX: IftheMR1.13 bitis‘1’,thisbitwillbesetto‘1’
uponresetandwillbewriteable. Otherwise,thisbitcannotbe
setto‘1’ bythemanagement.
4.6A1R/W(1)10BASE-T Full Duplex:IftheMR1.12bitis‘1’,thisbitwillbe
setto‘1’ uponresetandwillbewriteable.Otherwise,thisbit
cannotbesetto‘1’bythemanagement.
78Q2123/78Q2133Data SheetDS_21x3_001
4.5A0R/W(1)10BASE-T: IftheMR1.11 bitis‘1’,thisbitwillbesetto‘1’
uponresetandwillbewriteable. Otherwise,thisbitcannotbe
setto‘1’ bythemanagement.
4.4:0S4:0R 01hSelectorField: Hardcodedwiththevalueof‘00001’ forIEEE
Note:TechnologyAbilityField: MR4.12:5aretheTechnologyAbilityFieldbits(A7:0). The defaultvaluethisfieldisdependentupontheMR1.15:11registerbits.Thisfieldcanbeoverwrittenbymanagementauto-negotiate toanalternate commontechnology.Writingtothisregisterhasnoeffectuntil
auto-negotiationisre-initiated.
3.6MR5:Auto-NegotiationLinkPartnerAbilityRegister
BitSymbolTypeDefaultDescription5.15NPR 0 NextPage:When‘1’ isread,itindicatesthelinkpartner
wishestoengageinNextPageexchange.
5.14ACKR 0 Acknowledge:When‘1’isread,itindicatesthelinkpartner has
successfullyreceivedatleast 3 consecutive andconsistent
FLPbursts.
5.13RFR0Remote Fault:When‘1’ isread,itindicatesthelinkpartnerhas
a fault.
5.12:5A7:0R 0 TechnologyAbilityField: Thisfieldcontainsthetechnology
abilityofthelinkpartner.The bitdefinitionisthesameas
MR4.12:5.
5.4:0S4:0R 00hSelectorField:Thisfieldcontainsthetypeofmessagesentby
thelinkpartner.ForanIEEE 802.3compliantlinkpartner,this
fieldshouldbe‘00001’.
3.7MR6:Auto-NegotiationExpansionRegister
BitSymbolTypeDefaultDescription6.15:5RSVDR 0 Reserved
6.4PDFRC0 ParallelDetectionFault:When‘1’isread,itindicatesthat
morethanonetechnologyhasbeendetectedduringlinkup.
Thisbitisclearedwhenread.
6.3LPNPAR 0 LinkPartner NextPageAble:When‘1’isread,itindicatesthe
linkpartner supportstheNextPagefunction.
6.2NPAR0NextPageAble:Reads‘0’ since the78Q2123/78Q2133donot
supportNextPagefunction.
6.1PRXRC0 PageReceived:Reads‘1’ when a newlinkcodewordhas
beenreceivedintotheAuto-NegotiationLinkPartner Ability
Register. Thisbitiscleareduponread.
6.0LPANEGAR 0 LinkPartner Auto-NegotiationAble:When‘1’ isread,it
indicatesthelinkpartner isabletoparticipateintheAuto-
Negotiationfunction.
3.8MR16:VendorSpecificRegister
BitSymbolTypeDefaultDescription16.15RPTRR/W(0)RepeaterMode:Whenset,the78Q2123/78Q2133areput
DS_21x3_00178Q2123/78Q2133Data Sheet prohibited,CRSrespondstoreceiveactivityonlyand,in
10Base-T mode,theSQEtestfunctionisdisabled.
16.14INPOLR/W0 Whenthisbitis‘0’,theINTRpinisforcedlowtosignalan
interrupt.Settingthisbitto‘1’causestheINTRpintobe
forcedhightosignalaninterrupt.
16.13RSVDR 0 Reserved
16.12TXHIMR/W0 Transmitter High-Impedance Mode:Whenset,the
TXOP/TXONtransmitpinsandtheTX_CLKpinareputinto a
high-impedancestate. The receivecircuitryremainsfully
functional.
16.11SQEIR/W0 SQETestInhibit:Settingthisbitto‘1’disables10Base-T
SQEtesting.Bydefault,thisbitis‘0’ and theSQEtestis
performedbygenerating a COLpulsefollowingthe
completionof a packettransmission.
16.10NL10R/W0 10Base-T NaturalLoopback:Settingthisbitto‘1’causes
transmitdatareceivedontheTXD0-3 pinstobeautomatically
loopedbacktotheRXD0-3 pinswhen 10Base-T modeis
enabled.
16.9 RSVDR 0 Reserved
16.8 RSVDR 1 Reserved
16.7 RSVDR 0 Reserved
16.6RSVDR1Reserved
16.5 APOLR/W0 AutoPolarity: Duringauto-negotiationand10BASE-T mode,
the78Q2123/78Q2133 areabletoautomaticallyinvertthe
receivedsignaldueto a wrongpolarityconnection. Itdoessodetectingthepolarityofthelinkpulses.Settingthisbitto
‘1’ disablesthisfeature.
16.4 RVSPOLR/W0 ReversePolarity: The reverse polarityisdetectedeither
through 8 inverted10Base-T linkpulses(NLP)orthroughone
burstofinvertedclockpulsesintheauto-negotiationlink
pulses(FLP).Whenthereversepolarityisdetectedandifthe
AutoPolarityfeatureisenabled,the78Q2123/78Q2133will
invertthereceivedatainputandsetthisbitto‘1’.IfAuto
Polarityisdisabled,thenthisbitiswriteable.Writing a ‘1’to
thisbitforcesthepolarityofthereceive signaltobereversed.
16.3:2RSVDR/W0hReserved: Mustsetto‘00’.
16.1 PCSBPR/W0 PCSBypassMode:Whenset,the100Base-TXPCSand
scrambling/descramblingfunctionsarebypassed. Scrambled
5-bitcodegroupsfortransmissionareappliedtotheTX_ER,
TXD3-0 pinsandreceivedontheRX_ER,RXD3-0pins.The
RX_DVandTX_ENsignalsarenotvalidinthismode.
PCSBPmodeisvalidonlywhen100Base-TXmodeis
enabledandauto-negotiationisdisabled.
16.0 RXCCR/W0 ReceiveClockControl: Thisfunctionisvalidonlyin100Base- mode.Whensetto‘1’,theRX_CLKsignalwillbeheldlow
whenthereisnodatabeingreceived(tosave power). The
RX_CLKsignalwillrestart 1 clockcycle beforetheassertion RX_DVandwillbeshutoff 64clockcyclesafterRX_DV
goeslow. RXCCisdisabledwhenloopbackmodeisenabled
(MR0.14ishigh). Thisbitshouldbekeptatlogiczero when
PCSBypassmodeisused.
