74VHCT573AN ,Octal D-Type Latch with 3-STATE OutputsFunctional Description Truth TableThe VHCT573A contains eight D-type latches with 3-Inputs OutputsS ..
74VHCT573AN ,Octal D-Type Latch with 3-STATE OutputsFeaturesThe VHCT573A is an advanced high speed CMOS octal High speed: t = 7.7 ns (typ) at T = 25°C ..
74VHCT574A ,Octal D-Type Flip-Flop with 3-STATE OutputsFunctional Description Truth TableThe VHCT574A consists of eight edge-triggered flip-flopsInputs Ou ..
74VHCT574A ,Octal D-Type Flip-Flop with 3-STATE OutputsFeaturessimilar to equivalent Bipolar Schottky TTL while maintain-ing the CMOS low power dissipatio ..
74VHCT574AMTC ,Octal D-Type Flip-Flop with 3-STATE OutputsFeaturessimilar to equivalent Bipolar Schottky TTL while maintain-ing the CMOS low power dissipatio ..
74VHCT574AMTCX ,Octal D-Type Flip-Flop with 3-STATE OutputsGeneral Descriptionmatched supply and input voltages.The VHCT574A is an advanced high speed CMOS oc ..
892NCF-101M , Fixed Inductors for Surface Mounting
74VHCT573AM-74VHCT573AMTC-74VHCT573AMTCX-74VHCT573AMX-74VHCT573AN
Octal D-Type Latch with 3-STATE Outputs
74VHCT573A Octal D-Type Latch with 3-STATE Outputs January 1998 Revised April 1999 74VHCT573A Octal D-Type Latch with 3-STATE Outputs General Description Features The VHCT573A is an advanced high speed CMOS octal � High speed: t = 7.7 ns (typ) at T = 25°C PD A latch with 3-STATE output fabricated with silicon gate � High Noise Immunity: V = 2.0V, V = 0.8V IH IL CMOS technology. It achieves the high speed operation � Power Down Protection is provided on all inputs and similar to equivalent Bipolar Schottky TTL while maintain- outputs ing the CMOS low power dissipation. This 8-bit D-type latch is controlled by a Latch Enable input (LE) and an Out- � Low Noise: V = 1.6V (max) OLP put Enable input (OE). When the OE input is HIGH, the � Low Power Dissipation: eight outputs are in a high impedance state. I = 4 μA (max) @ T = 25°C CC A Protection circuits ensure that 0V to 7V can be applied to � Pin and function compatible with 74HCT573 the input and output (Note 1) pins without regard to the supply voltage. This device can be used to interface 3V to 5V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mis- matched supply and input voltages. Note 1: Outputs in OFF-State. Ordering Code: Order Number Package Number Package Description 74VHCT573AM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74VHCT573ASJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHCT573AMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHCT573AN N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram IEEE/IEC Pin Descriptions Pin Names Description D –D Data Inputs 0 7 LE Latch Enable Input OE 3-STATE Output Enable Input O –O 3-STATE Outputs 0 7 © 1999 DS500028.prf
