74VHCT373AMTCX ,Octal D-Type Latch with 3-STATE Outputs74VHCT373A Octal D-Type Latch with 3-STATE OutputsJuly 1997Revised April 199974VHCT373AOctal D-Type ..
74VHCT373AMX ,Octal D-Type Latch with 3-STATE OutputsFunctional Description Truth TableThe VHCT373A contains eight D-type latches with 3-Inputs OutputsS ..
74VHCT373AN ,Octal D-Type Latch with 3-STATE OutputsGeneral Descriptionup. This circuit prevents device destruction due to mis-The VHCT373A is an advan ..
74VHCT374AM ,OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT NON INVERTINGFunctional Description Truth TableThe VHCT374A consists of eight edge-triggered flip-flops Inputs O ..
74VHCT374AMTC ,Octal D-Type Flip-Flop with 3-STATE OutputsGeneral Descriptionmatched supply and input voltages.The VHCT374A is an advanced high speed CMOS oc ..
74VHCT374AMTCX ,Octal D-Type Flip-Flop with 3-STATE OutputsFunctional Description Truth TableThe VHCT374A consists of eight edge-triggered flip-flops Inputs O ..
892NCF-101M , Fixed Inductors for Surface Mounting
74VHCT373AMTC-74VHCT373AMTCX-74VHCT373AMX-74VHCT373AN
Octal D-Type Latch with 3-STATE Outputs
74VHCT373A Octal D-Type Latch with 3-STATE Outputs July 1997 Revised April 1999 74VHCT373A Octal D-Type Latch with 3-STATE Outputs 5V systems and two supply systems such as battery back General Description up. This circuit prevents device destruction due to mis- The VHCT373A is an advanced high speed CMOS octal D- matched supply and input voltages. type latch with 3-STATE output fabricated with silicon gate Note 1: Outputs in OFF-State. CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintain- Features ing the CMOS low power dissipation. This 8-bit D-type latch is controlled by a latch enable input (LE) and an out- � High speed: t = 7.7 ns (typ) at T = 25°C PD A put enable input (OE). The latches appear transparent to � High Noise Immunity: V = 2.0V, V = 0.8V IH IL data when latch enable (LE) is HIGH. When LE is LOW, the � Power Down Protection is provided on all inputs and data that meets the setup time is latched. When the OE input is HIGH, the eight outputs are in a high impedance outputs state. � Low Power Dissipation: Protection circuits ensure that 0V to 7V can be applied to I = 4 μA (max) @ T = 25°C CC A the input and output (Note 1) pins without regard to the � Pin and Function Compatible with 74HCT373 supply voltage. This device can be used to interface 3V to Ordering Code: Order Number Package Number Package Description 74VHCT373AM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74VHCT373ASJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHCT373AMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHCT373AN N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code Logic Symbol Connection Diagram IEEE/IEC Pin Descriptions Pin Names Description D –D Data Inputs 0 7 LE Latch Enable Input OE Output Enable Input O –O 3-STATE Outputs 0 7 © 1999 DS500027.prf
