74VHC74TTR ,DUAL D-TYPE FLIP FLOP WITH RESET AND CLEAR74VHC74DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR ■ HIGH SPEED: ..
74VHC74TTR ,DUAL D-TYPE FLIP FLOP WITH RESET AND CLEARAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
74VHC86 ,QUAD EXCLUSIVE OR GATE
74VHC86 ,QUAD EXCLUSIVE OR GATE
74VHC86 ,QUAD EXCLUSIVE OR GATE
74VHC86FT ,74VHC CMOS logic IC seriesabsolute maximum ratings, even briefly, lead to deterioration in IC performance or evendestruction. ..
74VHC74TTR
DUAL D-TYPE FLIP FLOP WITH RESET AND CLEAR
1/11June 2001 HIGH SPEED:
fMAX = 170 MHz (TYP .) at VCC = 5V
� LOW POWER DISSIPATION:CC = 2 μA (MAX.) at TA =25°C HIGH NOISE IMMUNITY:
VNIH = VNIL = 28% VCC (MIN.) POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT IMPEDANCE:OH | = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL OPERATING VOLTAGE RANGE:CC (OPR) = 2V to 5.5V PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 74 IMPROVED LATCH-UP IMMUNITY
DESCRIPTIONThe 74VHC74 is an advanced high-speed CMOS
DUAL D-TYPE FLIP FLOP WITH PRESET AND
CLEAR fabricated with sub-micron silicon gate
and double-layer metal wiring C2 MOS technology.
A signal on the D INPUT is transferred to the Q
OUTPUTS during the positive going transition of
the clock pulse.
CLR and PR are independent of the clock and
accomplished by a low setting on the appropriate
input.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74VHC74DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
74VHC742/11
INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE X : Don’t Care
LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays
74VHC743/11
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
RECOMMENDED OPERATING CONDITIONS 1) VIN from 30% to 70% of VCC
74VHC744/11
DC SPECIFICATIONS
74VHC745/11
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3ns)
(*) Voltage range is 3.3V ± 0.3V
(**) Voltage range is 5.0V ± 0.5V
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/2 (per
flip-flop)
74VHC746/11
TEST CIRCUIT CL =15/50pF or equivalent (includes jig and probe capacitance)
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)
