74VHC595 ,8-Bit Shift Register with Output Latches74VHC595 8-Bit Shift Register with Output LatchesAugust 1993Revised April 199974VHC5958-Bit Shift R ..
74VHC595 ,8-Bit Shift Register with Output LatchesGeneral Descriptionapplied to the input pins without regard to the supply volt-The VHC595 is an adv ..
74VHC595 ,8-Bit Shift Register with Output LatchesGeneral Descriptionapplied to the input pins without regard to the supply volt-The VHC595 is an adv ..
74VHC595 ,8-Bit Shift Register with Output LatchesGeneral Descriptionapplied to the input pins without regard to the supply volt-The VHC595 is an adv ..
74VHC595FT ,74VHC CMOS logic IC seriesFunctional Description• 8-Bit Shift Register/Latch (3-state)2. 2. General General2. 2. General Gene ..
74VHC595M ,8-Bit Shift Register with Output Latches74VHC595 8-Bit Shift Register with Output LatchesAugust 1993Revised April 199974VHC5958-Bit Shift R ..
74VHC595
8-Bit Shift Register with Output Latches
74VHC595 8-Bit Shift Register with Output Latches August 1993 Revised April 1999 74VHC595 8-Bit Shift Register with Output Latches An input protection circuit insures that 0V to 7V can be General Description applied to the input pins without regard to the supply volt- The VHC595 is an advanced high-speed CMOS Shift Reg- age. This device can be used to interface 5V to 3V systems ister fabricated with silicon gate CMOS technology. It and two supply systems such as battery backup. This cir- achieves the high-speed operation similar to equivalent cuit prevents device destruction due to mismatched supply Bipolar Schottky TTL while maintaining the CMOS low and input voltages. power dissipation. This device contains an 8-bit serial-in, parallel-out shift reg- Features ister that feeds an 8-bit D-type storage register. The stor- � High Speed: t = 5.4 ns (typ) at V = 5V age register has eight 3-STATE outputs. Separate clocks PD CC are provided for both the shift register and the storage reg- � Low power dissipation: I = 4 μA (max) at T = 25°C CC A ister. The shift register has a direct-overriding clear, serial � High noise immunity: V = V = 28% V (min) NIH NIL CC input, and serial output (standard) pins for cascading. Both � Power down protection is provided on all inputs the shift register and storage register use positive-edge triggered clocks. If both clocks are connected together, the � Low noise: V = 0.9V (typ) OLP shift register state will always be one clock pulse ahead of � Pin and function compatible with 74HC595 the storage register. Ordering Code: Order Number Package Number Package Description 74VHC595M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74VHC595SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHC595MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC595N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram IEEE/IEC © 1999 DS011640.prf
