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74VHC573T ,OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING74VHC573 OCTAL D-TYPE LATCHWITH 3 STATE OUTPUT NON INVERTINGn HIGH SPEED: t = 5.0 ns (TYP.) at V = ..
74VHC573TTR ,OCTAL D-TYPE LATCH WITH 3-STATE OUTPUTS NON INVERTINGABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Supply Voltage-0.5 to +7.0 VCCV DC Input Volta ..
74VHC574 ,Octal D-Type Flip-Flop with TRI-STATE(RM) OutputsAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
74VHC574M ,OCTAL D-TYPE FLIP FLOP WITH 3-STATE OUTPUT NON INVERTING74VHC574OCTAL D-TYPE FLIP FLOPWITH 3 STATE OUTPUTS NON INVERTING■ HIGH SPEED: ■ f = 180 MHz (TYP. ..
74VHC574MTC ,Octal D-Type Flip-Flop with 3-STATE OutputsFunctional Description Truth TableThe VHC574 consists of eight edge-triggered flip-flops withInputs ..
74VHC574MTC ,Octal D-Type Flip-Flop with 3-STATE OutputsFunctional Description Truth TableThe VHC574 consists of eight edge-triggered flip-flops withInputs ..

74VHC573T
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING
74VHC573
OCTAL D-TYPE LATCH
WITH3 STATE OUTPUT NON INVERTING
June 1999 HIGH SPEED:tPD =5.0ns (TYP.)at VCC =5V LOWPOWER DISSIPATION:
ICC =4 μA (MAX.)atTA =25oC HIGH NOISE IMMUNITY:
VNIH =VNIL =28% VCC (MIN.) POWERDOWN PROTECTIONON INPUTS SYMMETRICAL OUTPUT IMPEDANCE:
|IOH|=IOL=8 mA(MIN) BALANCED PROPAGATIONDELAYS:
tPLH≅ tPHL OPERATINGVOLTAGERANGE:
VCC (OPR)= 2Vto 5.5V PIN AND FUNCTION COMPATIBLE WITH SERIES573 IMPROVEDLATCH-UP IMMUNITY LOWNOISE: VOLP= 0.9V (Max.)
DESCRIPTION
The 74VHC573 is an advanced high-speed
CMOS OCTAL D-TYPE LATCH with3 STATE
OUTPUT NON INVERTING fabricated with
sub-micron silicon gate and double-layer metal
wiringC2 MOS technology.
This8 bit D-Type latchis controlled bya latch
enable input (LE) and an output enable input
(OE).
While the LE inputis heldata high level, theQ
outputswill follow the data inputs precisely.
When the LEis taken low, theQ outputs will be
latched preciselyat the logic levelofD input data.
While the (OE) inputis low, the8 outputs will bea normal logic state (highor low logic level)
and while high level the outputs will beina high
impedance state.
Power down protectionis provided on all inputs
and0to 7V can be acceptedon inputs with no
regardto the supply voltage. This device canbe
usedto interface5Vto 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES:
74VHC573M 74VHC573T
(Micro Package)
(TSSOP Package)
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INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No SYMBOL NAME AND FUNCTION OE 3 State Output Enable
Input (Active LOW)3,4,6,7,9toD7 Data Inputs
12, 13,14,
15, 16,17,
18,19toQ7 3 State Latch Outputs LE Latch Enable
Input GND Ground (0V) VCC Positive Supply Voltage
TRUTH TABLE
INPUTS OUTPUTS LE D Q XXZ L X NO CHANGE*
LHL L H H
X:Don’t care
Z:Highimpedance QoutputsarelatchedatthetimewhentheLEinputistaken lowlogiclevel.
LOGIC DIAGRAM
74VHC573
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ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
VCC Supply Voltage -0.5to +7.0 V DC Input Voltage -0.5to +7.0 V DC Output Voltage -0.5to VCC+ 0.5 V
IIK DC Input Diode Current -20 mA
IOK DC Output Diode Current ±20 mA DC Output Current ±25 mA
ICCor IGND DC VCCor Ground Current ±75 mA
Tstg Storage Temperature -65to +150 oC Lead Temperature (10 sec) 300 oC
AbsoluteMaximumRatingsarethosevalues beyond whichdamage tothedevicemayoccur. Functionaloperationunderthese condition isnot implied.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Value Unit
VCC Supply Voltage 2.0to5.5 V Input Voltage 0to5.5 V Output Voltage 0to VCC V
Top Operating Temperature -40to +85 oC
dt/dv Input Rise and Fall Time (see note1) (VCC =3.3± 0.3V)
(VCC =5.0± 0.5V)to 100
0to20
ns/V
ns/V
1)VINfrom30%to70%ofVCC SPECIFICATIONS
Symbol Parameter Test Conditions Value Unit
VCC
(V) =25oC -40to85oC
Min. Typ. Max. Min. Max.
VIH High Level Input
Voltage
2.0 1.5 1.5 V3.0to5.5 0.7VCC 0.7VCC
VIL Low Level Input
Voltage
2.0 0.5 0.5 V
3.0to5.5 0.3VCC 0.3VCC
VOH High Level Output
Voltage
2.0 IO=-50μA 1.9 2.0 1.9
3.0 IO=-50μA 2.9 3.0 2.9
4.5 IO=-50μA 4.4 4.5 4.4
3.0 IO=-4 mA 2.58 2.48
4.5 IO=-8 mA 3.94 3.8
VOL Low Level Output
Voltage
2.0 IO=50 μA 0.0 0.1 0.1
3.0 IO=50μA 0.0 0.1 0.1
4.5 IO=50μA 0.0 0.1 0.1
3.0 IO=4 mA 0.36 0.44
4.5 IO=8 mA 0.36 0.44
IOZ High Impedance
Output Leakage
Current
5.5 =VIHorVIL =VCCor GND
±0.25 ±2.5 μA Input Leakage Current 0 to5.5 VI= 5.5Vor GND ±0.1 ±1.0 μA
ICC Quiescent Supply
Current
5.5 VI =VCCor GND 4 40 μA
74VHC573
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CAPACITIVE CHARACTERISTICS
Symbol Parameter Test Conditions Value Unit =25oC -40to85oC
Min. Typ. Max. Min. Max.
CIN Input Capacitance 4 10 10 pF
COUT Output Capacitance 6 pF
CPD Power Dissipation
Capacitance (note1) pF
1)CPDisdefinedasthevalueoftheIC’sinternalequivalentcapacitance whichiscalculatedfromtheoperatingcurrentconsumption withoutload.(Referto
TestCircuit).Average operatingcurrent canbeobtained bythefollowingequation. ICC(opr)= CPD• VCC• fIN+ICC/8(per Latch) ELECTRICAL CHARACTERISTICS (Inputtr =tf=3 ns)
Symbol Parameter Test Condition Value Unit
VCC
(V)
(pF) =25oC -40to85oC
Min. Typ. Max. Min. Max.
tPLH
tPHL
Propagation Delay
Time (LEtoQ)
3.3(*) 15 7.6 11.9 1.0 14.03.3(*) 50 10.1 15.4 1.0 17.5
5.0(**) 15 5.0 7.7 1.0 9.0
5.0(**) 50 6.5 9.7 1.0 11.0
tPLH
tPHL
Propagation Delay
Time(DtoQ)
3.3(*) 15 7.0 11.0 1.0 13.03.3(*) 50 9.5 14.5 1.0 16.5
5.0(**) 15 4.5 6.8 1.0 8.0
5.0(**) 50 6.0 8.8 1.0 10.0
tPZL
tPZH
Output EnableTime 3.3(*) 15 RL =1KΩ 7.3 11.5 1.0 13.53.3(*) 50 RL =1KΩ 9.8 15.0 1.0 17.0
5.0(**) 15 RL =1KΩ 5.2 7.7 1.0 9.0
5.0(**) 50 RL =1KΩ 6.7 9.7 1.0 11.0
tPLZ
tPHZ
Output Disable Time 3.3(*) 50 RL =1KΩ 10.7 14.5 1.0 16.5 ns
5.0(**) 50 RL =1KΩ 6.7 9.7 1.0 11 Pulse Width (LE) HIGH 3.3(*) 5.0 5.0 ns
5.0(**) 5.0 5.0 Setup TimeDtoLE
HIGHor LOW
3.3(*) 3.5 3.5 ns5.0(**) 3.5 3.5 Hold TimeDtoLE
HIGHor LOW
3.3(*) 1.5 1.5 ns5.0(**) 1.5 1.5
tOSLH
tOSHL
Outputto Output Skew
Time (note1)
3.3(*) 50 1.5 1.5 ns
5.0(**) 50 1.0 1.0
(*) Voltagerangeis3.3V ±0.3V
(**) Voltagerangeis 5V±0.5V
Note1:Parameterguaranteed bydesign.tsoLH=|tpLHm-tpLHn|,tsoHL=|tpHLm-tpHLn|
74VHC573
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DYNAMIC SWITCHING CHARACTERISTICS
Symbol Parameter Test Conditions Value Unit
VCC
(V) =25oC -40to85oC
Min. Typ. Max. Min. Max.
VOLP Dynamic Low Voltage
Quiet Output (note1,2)
5.0 =50pF
0.6 0.9
VOLV -0.9 -0.6
VIHD Dynamic High Voltage
Input (note1,3)
5.0 3.5
VILD Dynamic Low Voltage
Input (note1,3)
5.0 1.5
1)Worst case package.
2)Maxnumber ofoutputs defined as(n).Datainputs aredriven0Vto5.0V,(n -1)outputs switching andoneoutput atGND.
3)Maxnumber ofdatainputs(n)switching.(n-1)switching0Vto5.0V.Inputsunder testswitching: 5.0Vtothreshold(VILD),0Vtothreshold(VIHD),f=1MHz.
TEST CIRCUIT
TEST SWITCH
tPLH,tPHL Open
tPZL,tPLZ VCC
tPZH,tPHZ GND =15/50 pForequivalent (includes jigand probecapacitance) =R1 =1KΩorequivalent
RT=ZOUTofpulsegenerator (typically50Ω)
74VHC573
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WAVEFORM1: LE TO Qn PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH, TO LE SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)
74VHC573
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Partno	Mfg	Dc	Qty	Available	Descript
74VHC573T	ST	N/a	8	avai	OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING