74VHC573MX ,Octal D-Type Latch with 3-STATE OutputsGeneral Descriptionand input voltages.The VHC573 is an advanced high speed CMOS octal latchwith 3-S ..
74VHC573MX ,Octal D-Type Latch with 3-STATE OutputsFeaturestechnology. It achieves the high speed operation similar toequivalent Bipolar Schottky TTL ..
74VHC573MX ,Octal D-Type Latch with 3-STATE OutputsFunctional Description Truth TableThe VHC573 contains eight D-type latches with 3-STATEInputs Outpu ..
74VHC573SJX ,Octal D-Type Latch with 3-STATE OutputsFeaturestechnology. It achieves the high speed operation similar toequivalent Bipolar Schottky TTL ..
74VHC573SJX ,Octal D-Type Latch with 3-STATE OutputsGeneral Descriptionand input voltages.The VHC573 is an advanced high speed CMOS octal latchwith 3-S ..
74VHC573SJX ,Octal D-Type Latch with 3-STATE Outputs74VHC573 Octal D-Type Latch with 3-STATE OutputsMarch 1993Revised April 199974VHC573Octal D-Type La ..
74VHC573MTC-74VHC573MTCX-74VHC573MX-74VHC573SJX
Octal D-Type Latch with 3-STATE Outputs
74VHC573 Octal D-Type Latch with 3-STATE Outputs March 1993 Revised April 1999 74VHC573 Octal D-Type Latch with 3-STATE Outputs cuit prevents device destruction due to mismatched supply General Description and input voltages. The VHC573 is an advanced high speed CMOS octal latch with 3-STATE output fabricated with silicon gate CMOS Features technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the � High Speed: t = 5.0 ns (typ) at V = 5V PD CC CMOS low power dissipation. This 8-bit D-type latch is con- � High Noise Immunity: V = V = 28% V (Min) NIH NIL CC trolled by a latch enable input (LE) and an Output Enable � Power Down Protection is provided on all inputs input (OE). When the OE input is HIGH, the eight outputs are in a high impedance state. � Low Noise: V = 0.6V (typ) OLP An input protection circuit ensures that 0V to 7V can be � Low Power Dissipation: I = 4 μA (Max) @ T = 25°C CC A applied to the input pins without regard to the supply volt- � Pin and function compatible with 74HC573 age. This device can be used to interface 5V to 3V systems and two supply systems such as battery back up. This cir- Ordering Code: Order Number Package Number Package Description 74VHC573M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide 74VHC573SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHC573MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC573N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram IEEE/IEC Pin Descriptions Pin Names Description D –D Data Inputs 0 7 LE Latch Enable Input OE 3-STATE Output Enable Input O –O 3-STATE Outputs 0 7 © 1999 DS011563.prf
