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74VHC573TOSN/a3885avaiOCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING


74VHC573 ,OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING74VHC573 74VHCT573OctalD-TypeLatchwithTRI-STATEOutputs#November199574VHC573 74VHCT573#OctalD-TypeLa ..
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74VHC573
Octal D-Type Latch with TRI-STATE Outputs
TL/F/11563
74VHC573
74VHCT573
Octal
D-Type
Latch
with
TRI-STATE
Outputs
November 1995
74VHC573# 74VHCT573
Octal D-Type Latch with TRI-STATEÉ Outputs
General Description
The VHC/VHCT573isan advancedhigh speed CMOSoctal
latch with TRI-STATE output fabricated with silicon gate
CMOS technology.It achievesthe high speed operation
similarto equivalent Bipolar Schottky TTL while maintaining
the CMOSlow power dissipation. This 8-bit D-type latchis
controlledbya latch enable input (LE) andan OutputEn-
able input (OE). Whenthe OEinputis high, theeightoutputs
areina high impedance state. input protection circuit ensures that 0V–7Vcanbeap-
pliedtothe input pins without regardtothe supply voltage.
This devicecanbe usedto interface5Vto3V systemsand
two supply systems suchas battery backup. This circuit
prevents device destructiondueto mismatched supplyand
input voltages.
Features High Noise Immunity: VHC: VNIHe VNILe 28% VCC (Min) VHCT:VIHe 2.0V,VILe 0.8V Power Down Protection: VHCe inputs only VHCTe inputsand outputs Low Noise: VHC VOLPe 0.6V (typ) VHCT VOLPe 0.8V (typ) Low Power Dissipation:
ÐICCe4mA (Max)@TAe 25§C Balanced propagation delays: tPLHj tPHLPinand function compatible with 74HC/HCT573
Note: ’VHCT specificationsare preliminary
Commercial Package Number PackageDescription
74VHC573M M20B 20-Lead MoldedJEDECSOIC
74VHC573SJ M20D 20-Lead MoldedEIAJSOIC
74VHC573MSC MSC20 20-Lead MoldedEIAJTypeISSOP
74VHC573MTC MTC20 20-Lead MoldedJEDECTypeITSSOP
74VHC573N N20A 20-Lead MoldedDIP
74VHCT573M M20B 20-Lead MoldedJEDECSOIC
74VHCT573SJ M20D 20-Lead MoldedEIAJSOIC
74VHCT573MTC MTC20 20-Lead MoldedJEDECTypeITSSOP
74VHCT573N N20A 20-Lead MoldedDIP
Note:Surface mountpackagesare alsoavailableonTape andReel.Specify byappendingthesuffixletter
‘‘X’’tothe ordering code.
Logic Symbol
IEEE/IEC
TL/F/11563–1
Connection Diagram
Pin Assignmentfor
DIP, SSOP, TSSOPand SOIC
TL/F/11563–2
Pin Names Description
D0–D7 Data Inputs Latch Enable Input TRI-STATE Output
Enable Input
O0–O7 TRI-STATE Outputs
TRI-STATEÉ isaregistered trademarkof National SemiconductorCorporation.
C1995National SemiconductorCorporation RRD-B30M125/PrintedinU.S.A.
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