74VHC541TTR ,OCTAL BUS BUFFER WITH 3 STATE OUTPUTS (NON INVERTED)Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
74VHC573 ,OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING74VHC573 74VHCT573OctalD-TypeLatchwithTRI-STATEOutputs#November199574VHC573 74VHCT573#OctalD-TypeLa ..
74VHC573M ,OCTAL D-TYPE LATCH WITH 3-STATE OUTPUTS NON INVERTING74VHC573OCTAL D-TYPE LATCHWITH 3 STATE OUTPUTS NON INVERTING■ HIGH SPEED: t = 5.0 ns (TYP.) at V =5 ..
74VHC573MTC ,Octal D-Type Latch with 3-STATE Outputs74VHC573 Octal D-Type Latch with 3-STATE OutputsMarch 1993Revised April 199974VHC573Octal D-Type La ..
74VHC573MTC ,Octal D-Type Latch with 3-STATE OutputsGeneral Descriptionand input voltages.The VHC573 is an advanced high speed CMOS octal latchwith 3-S ..
74VHC573MTCX ,Octal D-Type Latch with 3-STATE OutputsFunctional Description Truth TableThe VHC573 contains eight D-type latches with 3-STATEInputs Outpu ..
74VHC541MTR-74VHC541TTR
OCTAL BUS BUFFER WITH 3 STATE OUTPUTS (NON INVERTED)
1/9June 2001 HIGH SPEED: tPD = 3.5 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION:
ICC = 4 μA (MAX.) at TA=25°C HIGH NOISE IMMUNITY:NIH = VNIL = 28% VCC (MIN.) POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT IMPEDANCE:OH | = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: PLH ≅ t PHL OPERATING VOLTAGE RANGE:CC (OPR) = 2V to 5.5V PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 541 IMPROVED LATCH-UP IMMUNITY LOW NOISE: VOLP = 0.9V (MAX.)
DESCRIPTIONThe 74VHC541 is an advanced high-speed
CMOS OCTAL BUS BUFFER (3-STATE)
fabricated with sub-micron silicon gate and
double-layer metal wiring C2 MOS technology.
The 3 STATE control gate operates as two input
AND such that if either G1 or G2 are high, all eight
outputs are in the high impedance state.
In order to enhance PC board layout, the
74VHC541 offers a pinout having inputs and
outputs on opposite sides of the package.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74VHC541OCTAL BUS BUFFER
WITH 3 STATE OUTPUTS (NON INVERTED)
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
74VHC5412/9
INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE X : Don’t care
Z : High impedance
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
RECOMMENDED OPERATING CONDITIONS 1) VIN from 30% to 70% of VCC
74VHC5413/9
DC SPECIFICATIONS
74VHC5414/9
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3ns)
(*) Voltage range is 3.3V ± 0.3V
(**) Voltage range is 5.0V ± 0.5V
Note 1 : Parameter guaranteed by design. tsoLH = |tpLHm - tpLHn|, tsoHL = |tpHLm - tpHLn|
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per
Circuit)
74VHC5415/9
DYNAMIC SWITCHING CHARACTERISTICS 1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 5.0V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 5.0V. Inputs under test switching: 5.0V to threshold (VILD), 0V to threshold
(VIHD), f=1MHz.
TEST CIRCUIT CL =15/50pF or equivalent (includes jig and probe capacitance)
RL = R1 = 1KΩ or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
74VHC5416/9
WAVEFORM 1: PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle)
