74VHC373MSCX , Octal D-Type Latch with 3-STATE OutputsFunctional Description Truth TableThe VHC373 contains eight D-type latches with 3-STATEInputs Outpu ..
74VHC373MTCX ,Octal D-Type Latch with 3-STATE OutputsGeneral Descriptionand two supply systems such as battery back up. This cir-The VHC373 is an advanc ..
74VHC373MX ,Octal D-Type Latch with 3-STATE OutputsGeneral Descriptionand two supply systems such as battery back up. This cir-The VHC373 is an advanc ..
74VHC373N ,Octal D-Type Latch with 3-STATE OutputsFunctional Description Truth TableThe VHC373 contains eight D-type latches with 3-STATEInputs Outpu ..
74VHC373SJX ,Octal D-Type Latch with 3-STATE OutputsFunctional Description Truth TableThe VHC373 contains eight D-type latches with 3-STATEInputs Outpu ..
74VHC374 ,OCTAL D-TYPE FLIP FLOP WITH 3-STATE OUTPUT NON INVERTING74VHC374OCTAL D-TYPE FLIP FLOPWITH 3 STATE OUTPUTS NON INVERTING
74VHC373MSCX
Octal D-Type Latch with 3-STATE Outputs
74VHC373 Octal D-Type Latch with 3-STATE Outputs February 1993 Revised April 1999 74VHC373 Octal D-Type Latch with 3-STATE Outputs age. This device can be used to interface 5V to 3V systems General Description and two supply systems such as battery back up. This cir- The VHC373 is an advanced high speed CMOS octal D- cuit prevents device destruction due to mismatched supply type latch with 3-STATE output fabricated with silicon gate and input voltages. CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintain- Features ing the CMOS low power dissipation. This 8-bit D-type latch is controlled by a latch enable input (LE) and an out- � High Speed: t = 5.0 ns (typ) @ V = 5V PD CC put enable input (OE). The latches appear transparent to � High Noise Immunity: V = V = 28% V (Min) NIH NIL CC data when latch enable (LE) is HIGH. When LE is LOW, the � Power Down Protection is provided on all inputs data that meets the setup time is LATCHED. When the OE input is HIGH, the eight outputs are in a high impedance � Low Noise: V = 0.6V (typ) OLP state. � Low Power Dissipation: I = 4 μA (Max) @ T = 25°C CC A An input protection circuit ensures that 0V to 7V can be � Pin and Function Compatible with 74HC373 applied to the input pins without regard to the supply volt- Ordering Code: Order Number Package Number Package Description 74VHC373M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide 74VHC373SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHC373MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC373N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram IEEE/IEC Pin Descriptions Pin Names Description D –D Data Inputs 0 7 LE Latch Enable Input OE Output Enable Input O –O 3-STATE Outputs 0 7 © 1999 DS011555.prf
