74VHC373 ,OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING74VHC373OCTAL D-TYPE LATCHWITH 3 STATE OUTPUTS NON INVERTING
74VHC373
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING
1/14November 2004 HIGH SPEED: tPD = 5.0 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION:
ICC = 4 μA (MAX.) at TA=25°C HIGH NOISE IMMUNITY:
VNIH = VNIL = 28% VCC (MIN.) POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL OPERATING VOLTAGE RANGE:
VCC(OPR) = 2V to 5.5V PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 373 IMPROVED LATCH-UP IMMUNITY LOW NOISE: V OLP = 0.9V (MAX.)
DESCRIPTIONThe 74VHC373 is an advanced high-speed
CMOS OCTAL D-TYPE LATCH with 3 STATE
OUTPUTS NON INVERTING fabricated with
sub-micron silicon gate and double-layer metal
wiring C2 MOS technology.
These 8 bit D-Type latch are controlled by a latch
enable input (LE) and an output enable input (OE).
While the LE inputs is held at a high level, the Q
outputs will follow the data input precisely. When
the LE is taken low, the Q outputs will be latched
precisely at the logic level of D input data. While
the (OE) input is low, the 8 outputs will be in a
normal logic state (high or low logic level) and
while (OE) is in high level, the outputs will be in a
high impedance state.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74VHC373OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUTS NON INVERTING
Figure 1: Pin Connection And IEC Logic Symbols
Table 1: Order Codes Rev. 4
74VHC3732/14
Figure 2: Input Equivalent Circuit Table 2: Pin Description
Table 3: Truth Table X : Don’t Care
Z : High Impedance
* : Q Outputs are Latched at the time when the LE INPUT is taken low logic level
Figure 3: Logic Diagram This logic diagram has not be used to estimate propagation delays
74VHC3733/14
Table 4: Absolute Maximum Ratings Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
Table 5: Recommended Operating Conditions 1) VIN from 30% to 70% of VCC
74VHC3734/14
Table 6: DC Specifications
74VHC3735/14
Table 7: AC Electrical Characteristics (Input tr = tf = 3ns)
(*) Voltage range is 3.3V ± 0.3V
(**) Voltage range is 5.0V ± 0.5V
Note 1 : Parameter guaranteed by design. tsoLH = |tpLHm - tpLHn|, tsoHL = |tpHLm - tpHLn|
Table 8: Capacitive Characteristics 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per Latch)
74VHC3736/14
Table 9: Dynamic Switching Characteristics 1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 5.0V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 5.0V. Inputs under test switching: 5.0V to threshold (VILD), 0V to threshold
(VIHD), f=1MHz.
Figure 4: Test Circuit CL =15/50pF or equivalent (includes jig and probe capacitance)
RL = R1 = 1KΩ or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
74VHC3737/14
Figure 5: Waveform - LE TO Qn Propagation Delays, LE Minimum Pulse Width, Dn To LE Setup
And Hold Times (f=1MHz; 50% duty cycle)
Figure 6: Waveform - Output Enable And Disable Times (f=1MHz; 50% duty cycle)
